path: root/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.195162                       # Number of seconds simulated
sim_ticks                                5195162021000                       # Number of ticks simulated
final_tick                               5195162021000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 926995                       # Simulator instruction rate (inst/s)
host_op_rate                                  1786992                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            37543942770                       # Simulator tick rate (ticks/s)
host_mem_usage                                 611560                       # Number of bytes of host memory used
host_seconds                                   138.38                       # Real time elapsed on the host
sim_insts                                   128273323                       # Number of instructions simulated
sim_ops                                     247275942                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2861312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            823744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9012160                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12697600                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       823744                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          823744                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8123136                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8123136                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        44708                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12871                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140815                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                198400                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          126924                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               126924                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       550765                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               158560                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1734722                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2444120                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          158560                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             158560                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1563596                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1563596                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1563596                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       550765                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              158560                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1734722                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4007716                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        198400                       # Total number of read requests seen
system.physmem.writeReqs                       126924                       # Total number of write requests seen
system.physmem.cpureqs                         327581                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     12697600                       # Total number of bytes read from memory
system.physmem.bytesWritten                   8123136                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               12697600                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                8123136                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       58                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               1624                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 12569                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 12080                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 12233                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 12524                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 12268                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 12127                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 12566                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 12719                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 12479                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 12349                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                12465                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                12500                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                12468                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                12050                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                12371                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                12574                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  8012                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7683                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7790                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  8089                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7865                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7679                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  8084                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  8243                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  8069                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7980                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7953                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7969                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7935                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7628                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7886                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 8059                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                         633                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5195161957500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  198400                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 126924                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    155117                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      8774                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6658                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3415                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3396                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2811                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2249                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2165                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2071                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2021                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1317                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1212                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1130                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1042                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      954                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      971                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1103                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1084                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      505                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      310                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       37                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      5322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5503                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5511                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5512                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5519                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      999                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        7                       # What write queue length does an incoming req see
system.physmem.totQLat                     4073325250                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                7869155250                       # Sum of mem lat for all requests
system.physmem.totBusLat                    991710000                       # Total cycles spent in databus access
system.physmem.totBankLat                  2804120000                       # Total cycles spent in bank access
system.physmem.avgQLat                       20536.88                       # Average queueing delay per request
system.physmem.avgBankLat                    14137.80                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  39674.68                       # Average memory access latency
system.physmem.avgRdBW                           2.44                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.44                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.56                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        12.66                       # Average write queue length over time
system.physmem.readRowHits                     175586                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94818                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   88.53                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.70                       # Row buffer hit rate for writes
system.physmem.avgGap                     15969193.66                       # Average gap between requests
system.iocache.replacements                     47509                       # number of replacements
system.iocache.tagsinuse                     0.124742                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47525                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              5044527520000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.124742                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.007796                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.007796                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          844                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              844                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47564                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47564                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47564                       # number of overall misses
system.iocache.overall_misses::total            47564                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    139479932                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    139479932                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10699969160                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10699969160                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10839449092                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10839449092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10839449092                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10839449092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          844                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            844                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47564                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47564                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47564                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47564                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 165260.582938                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229023.312500                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 229023.312500                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227891.873938                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 227891.873938                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227891.873938                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 227891.873938                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        173195                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16181                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.703603                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          844                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          844                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47564                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47564                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47564                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47564                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     95570962                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     95570962                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   8269165315                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8269165315                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   8364736277                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8364736277                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   8364736277                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8364736277                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.736967                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.736967                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176994.120612                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 176994.120612                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 175862.759167                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 175862.759167                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                      10390324042                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   128273323                       # Number of instructions committed
system.cpu.committedOps                     247275942                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             232011652                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     23157367                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    232011652                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads           567056066                       # number of times the integer registers were read
system.cpu.num_int_register_writes          293242220                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                      22232130                       # number of memory refs
system.cpu.num_load_insts                    13871776                       # Number of load instructions
system.cpu.num_store_insts                    8360354                       # Number of store instructions
system.cpu.num_idle_cycles               9789674914.998116                       # Number of idle cycles
system.cpu.num_busy_cycles               600649127.001884                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.057809                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.942191                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.icache.replacements                 791510                       # number of replacements
system.cpu.icache.tagsinuse                510.376104                       # Cycle average of tags in use
system.cpu.icache.total_refs                144497671                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 792022                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                 182.441486                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle           159800886000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.376104                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996828                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996828                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    144497671                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       144497671                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     144497671                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        144497671                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    144497671                       # number of overall hits
system.cpu.icache.overall_hits::total       144497671                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       792029                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        792029                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       792029                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         792029                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       792029                       # number of overall misses
system.cpu.icache.overall_misses::total        792029                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  10955241500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  10955241500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  10955241500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  10955241500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  10955241500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  10955241500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    145289700                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    145289700                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    145289700                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    145289700                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    145289700                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    145289700                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005451                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.005451                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.005451                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.005451                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.005451                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.005451                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13831.869161                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13831.869161                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13831.869161                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13831.869161                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13831.869161                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13831.869161                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       792029                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       792029                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       792029                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       792029                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       792029                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       792029                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9371183500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   9371183500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9371183500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   9371183500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9371183500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   9371183500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005451                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005451                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005451                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.005451                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005451                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.005451                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11831.869161                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11831.869161                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11831.869161                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11831.869161                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11831.869161                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11831.869161                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements         3425                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        3.077882                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs           8006                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs         3437                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.329357                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5164118674000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.077882                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.192368                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.192368                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         8004                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         8004                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         8006                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         8006                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         8006                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         8006                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4287                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4287                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4287                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4287                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4287                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4287                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     42274000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     42274000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     42274000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     42274000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     42274000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     42274000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12291                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12291                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12293                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12293                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12293                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12293                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.348792                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.348792                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.348735                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.348735                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.348735                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.348735                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9860.975041                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9860.975041                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9860.975041                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9860.975041                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9860.975041                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9860.975041                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks          641                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          641                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4287                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4287                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4287                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         4287                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4287                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         4287                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     33700000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     33700000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     33700000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     33700000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     33700000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     33700000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.348792                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.348792                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.348735                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.348735                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.348735                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.348735                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7860.975041                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7860.975041                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7860.975041                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7860.975041                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7860.975041                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7860.975041                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements         7540                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse        5.062515                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs          13178                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs         7554                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.744506                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5159123845000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.062515                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.316407                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.316407                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13180                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        13180                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13180                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        13180                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13180                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        13180                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8726                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         8726                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8726                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         8726                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8726                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         8726                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     92094500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     92094500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     92094500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total     92094500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     92094500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total     92094500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21906                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        21906                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21906                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        21906                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21906                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        21906                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.398338                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.398338                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.398338                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.398338                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.398338                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.398338                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10554.033922                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10554.033922                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10554.033922                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10554.033922                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10554.033922                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10554.033922                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks         2713                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         2713                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8726                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8726                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8726                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total         8726                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8726                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total         8726                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     74642500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     74642500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     74642500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     74642500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     74642500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     74642500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.398338                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.398338                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.398338                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.398338                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.398338                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.398338                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8554.033922                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8554.033922                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8554.033922                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8554.033922                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8554.033922                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8554.033922                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1618785                       # number of replacements
system.cpu.dcache.tagsinuse                511.997766                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 20025893                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1619297                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  12.367029                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               39012000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997766                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     11988262                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11988262                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8035470                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8035470                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      20023732                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         20023732                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20023732                       # number of overall hits
system.cpu.dcache.overall_hits::total        20023732                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1306602                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1306602                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       314890                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       314890                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1621492                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1621492                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1621492                       # number of overall misses
system.cpu.dcache.overall_misses::total       1621492                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  18343104000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  18343104000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   8556691000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   8556691000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  26899795000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  26899795000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  26899795000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  26899795000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13294864                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13294864                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8350360                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8350360                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21645224                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21645224                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21645224                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21645224                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098279                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.098279                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037710                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037710                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.074912                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.074912                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.074912                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.074912                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.784573                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.784573                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27173.587602                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27173.587602                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.532973                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16589.532973                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.532973                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16589.532973                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1536047                       # number of writebacks
system.cpu.dcache.writebacks::total           1536047                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1306602                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1306602                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       314890                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       314890                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1621492                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1621492                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1621492                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1621492                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15729900000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  15729900000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7926911000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   7926911000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23656811000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23656811000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23656811000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23656811000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94145949000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94145949000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2467832500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2467832500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96613781500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  96613781500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098279                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098279                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037710                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037710                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074912                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.074912                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074912                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.074912                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12038.784573                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12038.784573                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25173.587602                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25173.587602                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.532973                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.532973                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.532973                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.532973                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 86864                       # number of replacements
system.cpu.l2cache.tagsinuse             64770.428925                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3484716                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                151631                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 22.981554                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50336.266909                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker     0.007172                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.140366                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3358.136526                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  11075.877952                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.768070                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.051241                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.169004                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.988318                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6347                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2754                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       779144                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1277462                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2065707                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1539401                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1539401                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          293                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          293                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       199367                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       199367                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6347                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         2754                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       779144                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1476829                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2265074                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6347                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         2754                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       779144                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1476829                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2265074                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12872                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        28385                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        41263                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1364                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1364                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       113358                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       113358                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12872                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141743                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        154621                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12872                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141743                       # number of overall misses
system.cpu.l2cache.overall_misses::total       154621                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker        68500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       345000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    787701500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1647921500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2436036500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16174500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     16174500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5583363000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5583363000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker        68500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       345000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    787701500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7231284500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8019399500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker        68500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       345000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    787701500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7231284500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8019399500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6348                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2759                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       792016                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1305847                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2106970                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1539401                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1539401                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1657                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1657                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       312725                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       312725                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6348                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         2759                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       792016                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1618572                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2419695                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6348                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         2759                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       792016                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1618572                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2419695                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000158                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001812                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016252                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021737                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.019584                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.823174                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.823174                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.362485                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.362485                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000158                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001812                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016252                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087573                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063901                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000158                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001812                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016252                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087573                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063901                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        68500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        69000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61194.958048                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58056.068346                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 59036.824758                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11858.137830                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11858.137830                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49254.247605                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49254.247605                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        68500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        69000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61194.958048                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51016.872085                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51864.879285                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        68500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        69000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61194.958048                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51016.872085                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51864.879285                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        80257                       # number of writebacks
system.cpu.l2cache.writebacks::total            80257                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            1                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12872                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28385                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        41263                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1364                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1364                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113358                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       113358                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12872                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141743                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154621                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12872                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141743                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       154621                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker        56251                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       281255                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    627778857                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1295316957                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1923433320                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14542846                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14542846                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4190411275                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4190411275                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker        56251                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       281255                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    627778857                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5485728232                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6113844595                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker        56251                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       281255                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    627778857                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5485728232                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6113844595                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86591175500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86591175500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2305021500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2305021500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  88896197000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  88896197000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000158                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001812                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016252                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021737                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019584                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.823174                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.823174                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.362485                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.362485                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000158                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001812                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016252                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087573                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063901                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000158                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001812                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016252                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087573                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063901                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        56251                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        56251                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48770.886964                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45633.854395                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46613.996074                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36966.171554                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36966.171554                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        56251                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        56251                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48770.886964                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38701.934007                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39540.842415                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        56251                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        56251                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48770.886964                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38701.934007                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39540.842415                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------