path: root/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.200402                       # Number of seconds simulated
sim_ticks                                5200402495000                       # Number of ticks simulated
final_tick                               5200402495000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1256922                       # Simulator instruction rate (inst/s)
host_op_rate                                  2423033                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            50949381192                       # Simulator tick rate (ticks/s)
host_mem_usage                                 591984                       # Number of bytes of host memory used
host_seconds                                   102.07                       # Real time elapsed on the host
sim_insts                                   128294014                       # Number of instructions simulated
sim_ops                                     247318948                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide      2869888                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            826752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           8970624                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12667648                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       826752                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          826752                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8094016                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8094016                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        44842                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12918                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140166                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                197932                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          126469                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               126469                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       551859                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               158978                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1724986                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2435898                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          158978                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             158978                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1556421                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1556421                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1556421                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       551859                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              158978                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1724986                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3992319                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        197932                       # Number of read requests accepted
system.physmem.writeReqs                       126469                       # Number of write requests accepted
system.physmem.readBursts                      197932                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     126469                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12654528                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     13120                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8092032                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12667648                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8094016                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      205                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1622                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12706                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12058                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12568                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12134                       # Per bank write bursts
system.physmem.perBankRdBursts::4               12521                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12218                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12048                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12245                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12013                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12113                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12409                       # Per bank write bursts
system.physmem.perBankRdBursts::11              12495                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12992                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12976                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12442                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11789                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8349                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7660                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8054                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7772                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8164                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7804                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7601                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7742                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7412                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7677                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8006                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7919                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8539                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8375                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8051                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7313                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
system.physmem.totGap                    5200402431500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  197932                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 126469                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    153822                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2802                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2836                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2322                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2661                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5083                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4526                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4292                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3878                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2499                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2187                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1998                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1775                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1455                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1085                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1035                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      994                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      939                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      873                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      635                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1772                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1931                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4818                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4882                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4906                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4927                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5027                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6982                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5886                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6738                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7068                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7099                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2363                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2044                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     2242                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     2142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     2178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     2139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1001                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      780                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      359                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        6                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        36378                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      449.321238                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     264.022911                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     400.116091                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           9783     26.89%     26.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         7520     20.67%     47.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3398      9.34%     56.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1958      5.38%     62.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1470      4.04%     66.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          950      2.61%     68.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          669      1.84%     70.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          516      1.42%     72.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10114     27.80%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          36378                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6806                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.049956                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      579.203336                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6805     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6806                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6806                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.577432                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.979234                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.072144                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            4358     64.03%     64.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            1673     24.58%     88.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              85      1.25%     89.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              45      0.66%     90.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              78      1.15%     91.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27             127      1.87%     93.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29              53      0.78%     94.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31              38      0.56%     94.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33              25      0.37%     95.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35              74      1.09%     96.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37              52      0.76%     97.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39              16      0.24%     97.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41              72      1.06%     98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43              19      0.28%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45              28      0.41%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47              13      0.19%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49               8      0.12%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               5      0.07%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53               7      0.10%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               5      0.07%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57               2      0.03%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59               2      0.03%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61               1      0.01%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62-63               5      0.07%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-65              13      0.19%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-69               1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::74-75               1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6806                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5807464000                       # Total ticks spent queuing
system.physmem.totMemAccLat                9465482750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    988635000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  2669383750                       # Total ticks spent accessing banks
system.physmem.avgQLat                       29371.12                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    13500.35                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47871.47                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.43                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.44                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.17                       # Average write queue length when enqueuing
system.physmem.readRowHits                     167067                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     99118                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   84.49                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.37                       # Row buffer hit rate for writes
system.physmem.avgGap                     16030784.22                       # Average gap between requests
system.physmem.pageHitRate                      82.11                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               0.28                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                      4355532                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              623246                       # Transaction distribution
system.membus.trans_dist::ReadResp             623246                       # Transaction distribution
system.membus.trans_dist::WriteReq              13777                       # Transaction distribution
system.membus.trans_dist::WriteResp             13777                       # Transaction distribution
system.membus.trans_dist::Writeback            126469                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2149                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1640                       # Transaction distribution
system.membus.trans_dist::ReadExReq            159500                       # Transaction distribution
system.membus.trans_dist::ReadExResp           159500                       # Transaction distribution
system.membus.trans_dist::MessageReq             1656                       # Transaction distribution
system.membus.trans_dist::MessageResp            1656                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3312                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3312                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       480328                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710118                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       390403                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1580849                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       139069                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       139069                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1723230                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       246444                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420233                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14905088                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     16571765                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5856576                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5856576                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            22434965                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               22434965                       # Total data (bytes)
system.membus.snoop_data_through_bus           215552                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           256796000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           359324000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3312000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1349763000                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1656000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2610332746                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy          429200500                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47505                       # number of replacements
system.iocache.tags.tagsinuse                0.134382                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47521                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5049788540000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.134382                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008399                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.008399                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428040                       # Number of tag accesses
system.iocache.tags.data_accesses              428040                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          840                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              840                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47560                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47560                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47560                       # number of overall misses
system.iocache.overall_misses::total            47560                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    142383686                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    142383686                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  12484793248                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  12484793248                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  12627176934                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  12627176934                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  12627176934                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  12627176934                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          840                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            840                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47560                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47560                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47560                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47560                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169504.388095                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 169504.388095                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267225.882877                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 267225.882877                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265499.935534                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 265499.935534                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265499.935534                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 265499.935534                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        224342                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                18183                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.338008                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          840                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          840                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47560                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47560                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47560                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47560                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     98678186                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     98678186                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide  10053057748                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  10053057748                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide  10151735934                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  10151735934                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide  10151735934                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  10151735934                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117474.030952                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 117474.030952                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215176.749743                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 215176.749743                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 213451.134020                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 213451.134020                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.iobus.throughput                        630784                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq               230145                       # Transaction distribution
system.iobus.trans_dist::ReadResp              230145                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57579                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57579                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1656                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1656                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       436684                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27236                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       480328                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3312                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3312                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  578760                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       218342                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio        13618                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       246444                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027264                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027264                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              3280332                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 3280332                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              3953400                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8813000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                77000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            218343000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            20374000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           425604434                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           469469000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            53343500                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1656000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                      10400804990                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   128294014                       # Number of instructions committed
system.cpu.committedOps                     247318948                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             231911784                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                     2299833                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     23159249                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    231911784                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads           434400113                       # number of times the integer registers were read
system.cpu.num_int_register_writes          197801183                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            132752064                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            95494911                       # number of times the CC registers were written
system.cpu.num_mem_refs                      22235692                       # number of memory refs
system.cpu.num_load_insts                    13875118                       # Number of load instructions
system.cpu.num_store_insts                    8360574                       # Number of store instructions
system.cpu.num_idle_cycles               9794078774.998117                       # Number of idle cycles
system.cpu.num_busy_cycles               606726215.001883                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.058335                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.941665                       # Percentage of idle cycles
system.cpu.Branches                          26297154                       # Number of branches fetched
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.icache.tags.replacements            791422                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.352385                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           144521518                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            791934                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            182.491872                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      161455178250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.352385                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996782                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996782                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         146105400                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        146105400                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    144521518                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       144521518                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     144521518                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        144521518                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    144521518                       # number of overall hits
system.cpu.icache.overall_hits::total       144521518                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       791941                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        791941                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       791941                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         791941                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       791941                       # number of overall misses
system.cpu.icache.overall_misses::total        791941                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  11119349759                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  11119349759                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  11119349759                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  11119349759                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  11119349759                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  11119349759                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    145313459                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    145313459                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    145313459                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    145313459                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    145313459                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    145313459                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005450                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.005450                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.005450                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.005450                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.005450                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.005450                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14040.628985                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14040.628985                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14040.628985                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14040.628985                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14040.628985                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14040.628985                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791941                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       791941                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       791941                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       791941                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       791941                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       791941                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9530763241                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   9530763241                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9530763241                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   9530763241                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9530763241                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   9530763241                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005450                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005450                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005450                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.005450                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005450                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.005450                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12034.688494                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12034.688494                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12034.688494                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12034.688494                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12034.688494                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12034.688494                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         3448                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     3.074851                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs         7916                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         3460                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.287861                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5178780288000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.074851                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.192178                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.192178                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        28763                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        28763                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7916                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         7916                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7918                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         7918                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7918                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         7918                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4309                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4309                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4309                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4309                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4309                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4309                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     42842750                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     42842750                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     42842750                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     42842750                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     42842750                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     42842750                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12225                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12225                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12227                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12227                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12227                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12227                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.352474                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.352474                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.352417                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.352417                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.352417                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.352417                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9942.620097                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9942.620097                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9942.620097                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9942.620097                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9942.620097                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9942.620097                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks          776                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          776                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4309                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4309                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4309                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         4309                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4309                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         4309                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     34223750                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     34223750                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     34223750                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     34223750                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     34223750                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     34223750                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.352474                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.352474                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.352417                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.352417                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.352417                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.352417                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7942.388025                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7942.388025                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7942.388025                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7942.388025                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7942.388025                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7942.388025                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements         8116                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse     5.061830                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        12619                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs         8130                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.552153                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5165732872000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.061830                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.316364                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.316364                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses        53134                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses        53134                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12626                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        12626                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12626                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        12626                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12626                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        12626                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9294                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         9294                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9294                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         9294                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9294                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         9294                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     98603000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     98603000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     98603000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total     98603000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     98603000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total     98603000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21920                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        21920                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21920                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        21920                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21920                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        21920                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.423996                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.423996                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.423996                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.423996                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.423996                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.423996                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10609.317839                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10609.317839                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10609.317839                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10609.317839                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10609.317839                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10609.317839                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks         3085                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         3085                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         9294                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         9294                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         9294                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total         9294                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         9294                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total         9294                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     80015000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     80015000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     80015000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     80015000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     80015000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     80015000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.423996                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.423996                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.423996                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.423996                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.423996                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.423996                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8609.317839                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8609.317839                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8609.317839                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8609.317839                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8609.317839                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8609.317839                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1620672                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.997242                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            20026945                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1621184                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             12.353283                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          51279250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.997242                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88213750                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88213750                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     11989262                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11989262                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8035472                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8035472                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      20024734                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         20024734                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20024734                       # number of overall hits
system.cpu.dcache.overall_hits::total        20024734                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1308613                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1308613                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       314792                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       314792                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1623405                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1623405                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1623405                       # number of overall misses
system.cpu.dcache.overall_misses::total       1623405                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  18824282553                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  18824282553                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10745506942                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10745506942                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  29569789495                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  29569789495                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  29569789495                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  29569789495                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13297875                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13297875                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8350264                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8350264                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21648139                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21648139                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21648139                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21648139                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098408                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.098408                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037698                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037698                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.074991                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.074991                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.074991                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.074991                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14384.911775                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14384.911775                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34135.260559                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34135.260559                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18214.671936                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18214.671936                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18214.671936                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18214.671936                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1537729                       # number of writebacks
system.cpu.dcache.writebacks::total           1537729                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308613                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1308613                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       314792                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       314792                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1623405                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1623405                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1623405                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1623405                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  16198393447                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  16198393447                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10064156058                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10064156058                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26262549505                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  26262549505                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26262549505                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26262549505                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94214672500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94214672500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2537739500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2537739500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96752412000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  96752412000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098408                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098408                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037698                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037698                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074991                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.074991                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074991                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.074991                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12378.291708                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12378.291708                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31970.812657                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31970.812657                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16177.447713                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16177.447713                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16177.447713                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16177.447713                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput                49161645                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2696443                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2695917                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13777                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13777                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1541590                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2211                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2211                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       359301                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       312590                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1583869                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5973994                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         7897                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        19197                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7584957                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50683392                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203806901                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       229632                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       633792                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      255353717                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         255333045                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       327296                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     3831359500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       484500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1190263759                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3051445995                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       6464000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      13941000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements            86417                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64729.830083                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3490254                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           151212                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            23.081859                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50287.594494                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.027550                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141486                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3384.035479                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11058.031076                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.767328                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.051636                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.168732                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.987699                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64795                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          115                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2818                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4824                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56981                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.988693                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         32189031                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        32189031                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6817                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2807                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       779009                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1279777                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2068410                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1541590                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1541590                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          307                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          307                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       199552                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       199552                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6817                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         2807                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       779009                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1479329                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2267962                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6817                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         2807                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       779009                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1479329                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2267962                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12919                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        28035                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        40960                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1395                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1395                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       113025                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       113025                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12919                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141060                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        153985                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12919                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141060                       # number of overall misses
system.cpu.l2cache.overall_misses::total       153985                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker        75000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       347500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    948719241                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2091207947                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3040349688                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16786842                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     16786842                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7717314435                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7717314435                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker        75000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       347500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    948719241                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9808522382                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10757664123                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker        75000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       347500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    948719241                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9808522382                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10757664123                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6818                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2812                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       791928                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1307812                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2109370                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1541590                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1541590                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1702                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1702                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       312577                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       312577                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6818                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         2812                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       791928                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1620389                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2421947                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6818                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         2812                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       791928                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1620389                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2421947                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000147                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001778                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016313                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021437                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.019418                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.819624                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.819624                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.361591                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.361591                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000147                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001778                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016313                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087053                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063579                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000147                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001778                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016313                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087053                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063579                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        75000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        69500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73435.965709                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74592.757161                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74227.287305                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12033.578495                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12033.578495                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68279.711878                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68279.711878                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        75000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        69500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73435.965709                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69534.399419                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69861.766555                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        75000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        69500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73435.965709                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69534.399419                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69861.766555                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        79802                       # number of writebacks
system.cpu.l2cache.writebacks::total            79802                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            1                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12919                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28035                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        40960                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1395                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1395                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113025                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       113025                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12919                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141060                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       153985                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12919                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141060                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       153985                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       285000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    786875759                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1740299053                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2527522312                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14883877                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14883877                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6303896565                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6303896565                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       285000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    786875759                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8044195618                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8831418877                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker        62500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       285000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    786875759                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8044195618                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8831418877                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86655869000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86655869000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2371074000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2371074000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89026943000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89026943000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000147                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001778                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016313                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021437                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019418                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.819624                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.819624                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.361591                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.361591                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000147                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001778                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016313                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087053                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063579                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000147                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001778                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016313                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087053                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063579                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        62500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60908.410790                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62075.942679                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61707.087695                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10669.445878                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10669.445878                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55774.355806                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55774.355806                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60908.410790                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57026.766043                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57352.462103                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60908.410790                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57026.766043                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57352.462103                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------