path: root/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000022                       # Number of seconds simulated
sim_ticks                                    22074000                       # Number of ticks simulated
final_tick                                   22074000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  27311                       # Simulator instruction rate (inst/s)
host_op_rate                                    27309                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               94600483                       # Simulator tick rate (ticks/s)
host_mem_usage                                 225500                       # Number of bytes of host memory used
host_seconds                                     0.23                       # Real time elapsed on the host
sim_insts                                        6372                       # Number of instructions simulated
sim_ops                                          6372                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             20032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             11072                       # Number of bytes read from this memory
system.physmem.bytes_read::total                31104                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        20032                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           20032                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                173                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   486                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            907492978                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            501585576                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1409078554                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       907492978                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          907492978                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           907492978                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           501585576                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1409078554                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           486                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         486                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    31104                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     31104                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  69                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  33                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  32                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  47                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  42                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  20                       # Per bank write bursts
system.physmem.perBankRdBursts::6                   1                       # Per bank write bursts
system.physmem.perBankRdBursts::7                   3                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::9                   1                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 22                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 25                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 14                       # Per bank write bursts
system.physmem.perBankRdBursts::13                120                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 45                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 12                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        21941500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     486                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       272                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           81                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      332.641975                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     207.818416                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     321.662840                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             25     30.86%     30.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           18     22.22%     53.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383            9     11.11%     64.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            9     11.11%     75.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            6      7.41%     82.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            1      1.23%     83.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      3.70%     87.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           10     12.35%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             81                       # Bytes accessed per row activation
system.physmem.totQLat                        4363750                       # Total ticks spent queuing
system.physmem.totMemAccLat                  13476250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2430000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        8978.91                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27728.91                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        1409.08                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     1409.08                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                          11.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                      11.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.72                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        390                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.25                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        45147.12                       # Average gap between requests
system.physmem.pageHitRate                      80.25                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     219240                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     119625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   1653600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               10785825                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                  38250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 13833660                       # Total energy per rank (pJ)
system.physmem_0.averagePower              873.750829                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE         118250                       # Time in different power states
system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        15303750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     325080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     177375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   1255800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               10123200                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 619500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 13518075                       # Total energy per rank (pJ)
system.physmem_1.averagePower              853.818096                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE         963500                       # Time in different power states
system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        14362750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                    2808                       # Number of BP lookups
system.cpu.branchPred.condPredicted              1660                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               479                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 2112                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     676                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             32.007576                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     398                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 30                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                         2105                       # DTB read hits
system.cpu.dtb.read_misses                         56                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                     2161                       # DTB read accesses
system.cpu.dtb.write_hits                        1074                       # DTB write hits
system.cpu.dtb.write_misses                        30                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                    1104                       # DTB write accesses
system.cpu.dtb.data_hits                         3179                       # DTB hits
system.cpu.dtb.data_misses                         86                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                     3265                       # DTB accesses
system.cpu.itb.fetch_hits                        2195                       # ITB hits
system.cpu.itb.fetch_misses                        34                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                    2229                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   17                       # Number of system calls
system.cpu.numCycles                            44149                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles               8603                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          16272                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        2808                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches               1074                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          4302                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    1040                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           735                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                      2195                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   341                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              14185                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.147127                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.556854                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    11330     79.87%     79.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      287      2.02%     81.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      214      1.51%     83.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      204      1.44%     84.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      242      1.71%     86.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      209      1.47%     88.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      241      1.70%     89.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      178      1.25%     90.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     1280      9.02%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                14185                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.063603                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.368570                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                     8626                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  2504                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      2413                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   199                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                    443                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                  227                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                    83                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                  14877                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   224                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                    443                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                     8799                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    1077                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles            424                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      2422                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                  1020                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  14259                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                     15                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                     32                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                    922                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands               10782                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 17904                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            17895                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                 8                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                  4570                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                     6212                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             24                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                       534                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 2680                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1315                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      12936                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  28                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                     10742                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued                20                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined            6591                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined         3553                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             11                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         14185                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.757279                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.490412                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               10181     71.77%     71.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1265      8.92%     80.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                 910      6.42%     87.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 677      4.77%     91.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 530      3.74%     95.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 330      2.33%     97.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 213      1.50%     99.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                  54      0.38%     99.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  25      0.18%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           14185                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                      29     19.86%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                     74     50.68%     70.55% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    43     29.45%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                  7248     67.47%     67.49% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.52% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 2358     21.95%     89.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1131     10.53%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  10742                       # Type of FU issued
system.cpu.iq.rate                           0.243312                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                         146                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013592                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              35814                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             19563                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses         9787                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                  10875                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads               70                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1497                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           20                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          450                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            65                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                    443                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                    1035                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                    24                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               13050                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts               109                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  2680                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1315                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 28                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                    22                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             20                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect             81                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          391                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  472                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                 10248                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  2164                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               494                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                            86                       # number of nop insts executed
system.cpu.iew.exec_refs                         3270                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1599                       # Number of branches executed
system.cpu.iew.exec_stores                       1106                       # Number of stores executed
system.cpu.iew.exec_rate                     0.232123                       # Inst execution rate
system.cpu.iew.wb_sent                           9960                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                          9797                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                      5308                       # num instructions producing a value
system.cpu.iew.wb_consumers                      7306                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.221908                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.726526                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts            6660                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               402                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        12983                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.492105                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.404730                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        10525     81.07%     81.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         1166      8.98%     90.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          505      3.89%     93.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          209      1.61%     95.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          137      1.06%     96.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5           75      0.58%     97.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6           89      0.69%     97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           87      0.67%     98.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          190      1.46%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        12983                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 6389                       # Number of instructions committed
system.cpu.commit.committedOps                   6389                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           2048                       # Number of memory references committed
system.cpu.commit.loads                          1183                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                       1050                       # Number of branches committed
system.cpu.commit.fp_insts                         10                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      6307                       # Number of committed integer instructions.
system.cpu.commit.function_calls                  127                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass           19      0.30%      0.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu             4319     67.60%     67.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult               1      0.02%     67.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.91% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              2      0.03%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead            1183     18.52%     86.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite            865     13.54%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total              6389                       # Class of committed instruction
system.cpu.commit.bw_lim_events                   190                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                        25491                       # The number of ROB reads
system.cpu.rob.rob_writes                       27316                       # The number of ROB writes
system.cpu.timesIdled                             260                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           29964                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        6372                       # Number of Instructions Simulated
system.cpu.committedOps                          6372                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               6.928594                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         6.928594                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.144329                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.144329                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    13019                       # number of integer regfile reads
system.cpu.int_regfile_writes                    7461                       # number of integer regfile writes
system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse           107.596270                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                2347                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               173                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             13.566474                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   107.596270                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.026269                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.026269                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          173                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.042236                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              5893                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             5893                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         1838                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1838                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          509                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            509                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          2347                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             2347                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         2347                       # number of overall hits
system.cpu.dcache.overall_hits::total            2347                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          157                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           157                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          356                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          356                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          513                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            513                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          513                       # number of overall misses
system.cpu.dcache.overall_misses::total           513                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     12056250                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     12056250                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     24043225                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     24043225                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     36099475                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     36099475                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     36099475                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     36099475                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1995                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1995                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2860                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2860                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2860                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2860                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.078697                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.078697                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.411561                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.411561                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.179371                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.179371                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.179371                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.179371                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76791.401274                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 76791.401274                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67537.148876                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 67537.148876                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70369.346979                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 70369.346979                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70369.346979                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 70369.346979                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         2245                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                38                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    59.078947                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           56                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          284                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          284                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          340                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          340                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          340                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          340                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          101                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          101                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           72                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           72                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          173                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          173                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          173                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8557250                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      8557250                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5645250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      5645250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14202500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     14202500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14202500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     14202500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050627                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050627                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.060490                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.060490                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.060490                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.060490                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84725.247525                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84725.247525                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78406.250000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78406.250000                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82095.375723                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 82095.375723                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82095.375723                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 82095.375723                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           158.400693                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                1716                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               314                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              5.464968                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   158.400693                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.077344                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.077344                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.153320                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              4704                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             4704                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         1716                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1716                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          1716                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1716                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         1716                       # number of overall hits
system.cpu.icache.overall_hits::total            1716                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          479                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           479                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          479                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            479                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          479                       # number of overall misses
system.cpu.icache.overall_misses::total           479                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     34067500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     34067500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     34067500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     34067500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     34067500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     34067500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         2195                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         2195                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         2195                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         2195                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         2195                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         2195                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.218223                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.218223                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.218223                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.218223                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.218223                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.218223                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71122.129436                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 71122.129436                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71122.129436                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 71122.129436                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71122.129436                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 71122.129436                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          165                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          165                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          165                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          165                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          165                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          314                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          314                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          314                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          314                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          314                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          314                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24276250                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     24276250                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24276250                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     24276250                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24276250                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     24276250                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143052                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143052                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143052                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.143052                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143052                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.143052                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77312.898089                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77312.898089                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77312.898089                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 77312.898089                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77312.898089                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 77312.898089                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          219.195035                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              414                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   158.471795                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    60.723240                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004836                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.001853                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.006689                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          414                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012634                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             4382                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            4382                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          313                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          101                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          414                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           72                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           72                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          313                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          173                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           486                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          313                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          173                       # number of overall misses
system.cpu.l2cache.overall_misses::total          486                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     23950750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      8448250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     32399000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5570250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      5570250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     23950750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     14018500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     37969250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     23950750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     14018500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     37969250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          314                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          101                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          415                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           72                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           72                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          314                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          173                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          487                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          314                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          173                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          487                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996815                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.997590                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996815                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.997947                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996815                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.997947                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76519.968051                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83646.039604                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 78258.454106                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77364.583333                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77364.583333                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76519.968051                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81031.791908                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78126.028807                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76519.968051                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81031.791908                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78126.028807                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          313                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          101                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          414                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           72                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           72                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          313                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          173                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          486                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          313                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          173                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          486                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     20032750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      7188250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     27221000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4674250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4674250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     20032750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11862500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     31895250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     20032750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11862500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     31895250                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996815                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997590                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996815                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.997947                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996815                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.997947                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64002.396166                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71170.792079                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65751.207729                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64920.138889                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64920.138889                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64002.396166                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68569.364162                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65628.086420                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64002.396166                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68569.364162                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65628.086420                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq            415                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           415                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           72                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           72                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          628                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          346                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               974                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20096                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        11072                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              31168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples          487                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                487    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            487                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         243500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        535750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          2.4                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        285500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
system.membus.trans_dist::ReadReq                 414                       # Transaction distribution
system.membus.trans_dist::ReadResp                414                       # Transaction distribution
system.membus.trans_dist::ReadExReq                72                       # Transaction distribution
system.membus.trans_dist::ReadExResp               72                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          972                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    972                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31104                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   31104                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples               486                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     486    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 486                       # Request fanout histogram
system.membus.reqLayer0.occupancy              605500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2581250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             11.7                       # Layer utilization (%)

---------- End Simulation Statistics   ----------