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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 12394500 # Number of ticks simulated
final_tick 12394500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 52290 # Simulator instruction rate (inst/s)
host_op_rate 52282 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 101684511 # Simulator tick rate (ticks/s)
host_mem_usage 219660 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11328 # Number of bytes read from this memory
system.physmem.bytes_read::total 31296 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 177 # Number of read requests responded to by this memory
system.physmem.num_reads::total 489 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1611037154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 913953770 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2524990923 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1611037154 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1611037154 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1611037154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 913953770 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2524990923 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1990 # DTB read hits
system.cpu.dtb.read_misses 56 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 2046 # DTB read accesses
system.cpu.dtb.write_hits 1084 # DTB write hits
system.cpu.dtb.write_misses 30 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 1114 # DTB write accesses
system.cpu.dtb.data_hits 3074 # DTB hits
system.cpu.dtb.data_misses 86 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 3160 # DTB accesses
system.cpu.itb.fetch_hits 2336 # ITB hits
system.cpu.itb.fetch_misses 38 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2374 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 24790 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2873 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 545 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 2164 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8141 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 16442 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1200 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2939 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1838 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 885 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 739 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2336 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 367 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 13982 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.175940 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.562615 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 11043 78.98% 78.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 296 2.12% 81.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 231 1.65% 82.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 234 1.67% 84.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 276 1.97% 86.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 200 1.43% 87.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 274 1.96% 89.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 190 1.36% 91.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1238 8.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 13982 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.115894 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.663251 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 9096 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 904 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2739 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1171 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 257 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 89 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 15180 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1171 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 9315 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 364 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2589 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 284 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 14415 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 250 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 10802 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 18056 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 18039 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 6232 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 728 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2652 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 12813 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 10578 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 6130 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 13982 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.756544 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.394074 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9591 68.60% 68.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1568 11.21% 79.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1143 8.17% 87.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 728 5.21% 93.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 479 3.43% 96.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 273 1.95% 98.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 154 1.10% 99.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 33 0.24% 99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 13982 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 10 8.70% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 65 56.52% 65.22% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 40 34.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 7162 67.71% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2248 21.25% 89.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1163 10.99% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 10578 # Type of FU issued
system.cpu.iq.rate 0.426704 # Inst issue rate
system.cpu.iq.fu_busy_cnt 115 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010872 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 35279 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 18978 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 9581 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 10680 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1469 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1171 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 28 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 12931 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2652 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 151 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 403 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 554 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 9992 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2057 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 586 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 88 # number of nop insts executed
system.cpu.iew.exec_refs 3174 # number of memory reference insts executed
system.cpu.iew.exec_branches 1621 # Number of branches executed
system.cpu.iew.exec_stores 1117 # Number of stores executed
system.cpu.iew.exec_rate 0.403066 # Inst execution rate
system.cpu.iew.wb_sent 9749 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 9591 # cumulative count of insts written-back
system.cpu.iew.wb_producers 5054 # num instructions producing a value
system.cpu.iew.wb_consumers 6863 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.386890 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.736413 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 6541 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 12811 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.498712 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.314684 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 10031 78.30% 78.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1473 11.50% 89.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 525 4.10% 93.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 241 1.88% 95.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 164 1.28% 97.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 92 0.72% 97.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 108 0.84% 98.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 37 0.29% 98.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 140 1.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 12811 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2048 # Number of memory references committed
system.cpu.commit.loads 1183 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 1050 # Number of branches committed
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
system.cpu.commit.function_calls 127 # Number of function calls committed.
system.cpu.commit.bw_lim_events 140 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 25250 # The number of ROB reads
system.cpu.rob.rob_writes 27045 # The number of ROB writes
system.cpu.timesIdled 255 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 10808 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
system.cpu.cpi 3.890458 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.890458 # CPI: Total CPI of All Threads
system.cpu.ipc 0.257039 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.257039 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12699 # number of integer regfile reads
system.cpu.int_regfile_writes 7211 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 158.537993 # Cycle average of tags in use
system.cpu.icache.total_refs 1881 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 6.009585 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 158.537993 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.077411 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.077411 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1881 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1881 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1881 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1881 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1881 # number of overall hits
system.cpu.icache.overall_hits::total 1881 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses
system.cpu.icache.overall_misses::total 455 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15830500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15830500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15830500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15830500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15830500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15830500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2336 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2336 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2336 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2336 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2336 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2336 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194777 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.194777 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.194777 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.194777 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.194777 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.194777 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34792.307692 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34792.307692 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34792.307692 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34792.307692 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 142 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 142 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 142 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 142 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 142 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11526000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11526000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11526000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11526000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11526000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11526000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133990 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.133990 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.133990 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36824.281150 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36824.281150 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36824.281150 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36824.281150 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36824.281150 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36824.281150 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 107.969871 # Cycle average of tags in use
system.cpu.dcache.total_refs 2254 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 177 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.734463 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 107.969871 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.026360 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.026360 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1748 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1748 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2254 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2254 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2254 # number of overall hits
system.cpu.dcache.overall_hits::total 2254 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 527 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 527 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 527 # number of overall misses
system.cpu.dcache.overall_misses::total 527 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6365000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6365000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12897000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12897000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19262000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19262000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19262000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19262000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1916 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1916 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2781 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2781 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2781 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2781 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087683 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.087683 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.189500 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.189500 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.189500 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.189500 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37886.904762 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 37886.904762 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35924.791086 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35924.791086 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36550.284630 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36550.284630 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 177 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 177 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 177 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4341000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4341000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2884500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2884500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7225500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7225500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7225500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7225500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054280 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054280 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063646 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.063646 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063646 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.063646 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41740.384615 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41740.384615 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39513.698630 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39513.698630 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 219.433273 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002404 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 158.518751 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 60.914522 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004838 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001859 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006697 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 177 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 489 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 177 # number of overall misses
system.cpu.l2cache.overall_misses::total 489 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11209500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4227000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 15436500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2808500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2808500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 11209500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7035500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 18245000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 11209500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7035500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 18245000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 177 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 490 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 177 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 490 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997959 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997959 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35927.884615 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40644.230769 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 37106.971154 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38472.602740 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38472.602740 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35927.884615 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39748.587571 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 37310.838446 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35927.884615 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39748.587571 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 37310.838446 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 177 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 177 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10213000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3905000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14118000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2577000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2577000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10213000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6482000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16695000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10213000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6482000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16695000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32733.974359 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37548.076923 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33937.500000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35301.369863 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35301.369863 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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