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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 12146500 # Number of ticks simulated
final_tick 12146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 109785 # Simulator instruction rate (inst/s)
host_op_rate 109750 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 208686624 # Simulator tick rate (ticks/s)
host_mem_usage 218220 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 6386 # Number of instructions simulated
sim_ops 6386 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory
system.physmem.bytes_read::total 31232 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory
system.physmem.num_reads::total 488 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1643930350 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 927345326 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2571275676 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1643930350 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1643930350 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1643930350 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 927345326 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2571275676 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1978 # DTB read hits
system.cpu.dtb.read_misses 49 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 2027 # DTB read accesses
system.cpu.dtb.write_hits 1059 # DTB write hits
system.cpu.dtb.write_misses 31 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 1090 # DTB write accesses
system.cpu.dtb.data_hits 3037 # DTB hits
system.cpu.dtb.data_misses 80 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 3117 # DTB accesses
system.cpu.itb.fetch_hits 2279 # ITB hits
system.cpu.itb.fetch_misses 30 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2309 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 24294 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2808 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1620 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 530 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 2127 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 736 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 7536 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 16063 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1157 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2867 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1787 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 912 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2279 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 349 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 13192 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.217632 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.600569 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10325 78.27% 78.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 292 2.21% 80.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 224 1.70% 82.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 225 1.71% 83.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 268 2.03% 85.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 190 1.44% 87.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 268 2.03% 89.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 182 1.38% 90.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1218 9.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 13192 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.115584 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.661192 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8379 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 934 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2684 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1132 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 256 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 14824 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1132 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8584 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 335 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2519 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 14111 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 206 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 10590 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 17651 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 17634 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 6007 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 768 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2619 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1317 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 12558 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 10419 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 5861 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3437 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 13192 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.789797 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.411802 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 8893 67.41% 67.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1482 11.23% 78.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1143 8.66% 87.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 751 5.69% 93.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 453 3.43% 96.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 282 2.14% 98.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 149 1.13% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 30 0.23% 99.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 9 0.07% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 13192 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 8 7.41% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 64 59.26% 66.67% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 36 33.33% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 7046 67.63% 67.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2237 21.47% 89.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1131 10.86% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 10419 # Type of FU issued
system.cpu.iq.rate 0.428871 # Inst issue rate
system.cpu.iq.fu_busy_cnt 108 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010366 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 34161 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 18458 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 9433 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 10514 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1434 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 452 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1132 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2619 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1317 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 137 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 530 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 9845 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2040 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 574 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 83 # number of nop insts executed
system.cpu.iew.exec_refs 3133 # number of memory reference insts executed
system.cpu.iew.exec_branches 1595 # Number of branches executed
system.cpu.iew.exec_stores 1093 # Number of stores executed
system.cpu.iew.exec_rate 0.405244 # Inst execution rate
system.cpu.iew.wb_sent 9591 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 9443 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4951 # num instructions producing a value
system.cpu.iew.wb_consumers 6720 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.388697 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.736756 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 6261 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 447 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 12060 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.530929 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.361741 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9314 77.23% 77.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1447 12.00% 89.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 498 4.13% 93.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 252 2.09% 95.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 164 1.36% 96.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 93 0.77% 97.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 106 0.88% 98.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 41 0.34% 98.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 145 1.20% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 12060 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6403 # Number of instructions committed
system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2050 # Number of memory references committed
system.cpu.commit.loads 1185 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 1051 # Number of branches committed
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
system.cpu.commit.int_insts 6321 # Number of committed integer instructions.
system.cpu.commit.function_calls 127 # Number of function calls committed.
system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 24228 # The number of ROB reads
system.cpu.rob.rob_writes 26471 # The number of ROB writes
system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11102 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6386 # Number of Instructions Simulated
system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
system.cpu.cpi 3.804259 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.804259 # CPI: Total CPI of All Threads
system.cpu.ipc 0.262863 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.262863 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12506 # number of integer regfile reads
system.cpu.int_regfile_writes 7104 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 161.646618 # Cycle average of tags in use
system.cpu.icache.total_refs 1829 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.843450 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 161.646618 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.078929 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.078929 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1829 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1829 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1829 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1829 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1829 # number of overall hits
system.cpu.icache.overall_hits::total 1829 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 450 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 450 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 450 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 450 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 450 # number of overall misses
system.cpu.icache.overall_misses::total 450 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15742000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15742000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15742000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15742000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15742000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15742000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2279 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2279 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2279 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2279 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2279 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2279 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197455 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.197455 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.197455 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.197455 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.197455 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.197455 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34982.222222 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34982.222222 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34982.222222 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34982.222222 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 137 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 137 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 137 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 137 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11060000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11060000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11060000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137341 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.137341 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.137341 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35335.463259 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35335.463259 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 109.846299 # Cycle average of tags in use
system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 176 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.926136 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 109.846299 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1766 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1766 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits
system.cpu.dcache.overall_hits::total 2275 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 146 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 146 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses
system.cpu.dcache.overall_misses::total 502 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5337000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5337000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12518000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12518000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17855000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17855000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17855000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17855000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2777 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2777 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2777 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2777 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076360 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076360 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.180771 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.180771 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.180771 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.180771 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36554.794521 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 36554.794521 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35162.921348 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35162.921348 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 35567.729084 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35567.729084 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3764000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3764000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6339000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6339000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6339000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6339000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054393 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054393 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.063378 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.063378 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36192.307692 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36192.307692 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35763.888889 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35763.888889 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 224.380125 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002404 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 161.620273 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 62.759852 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004932 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001915 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006848 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses
system.cpu.l2cache.overall_misses::total 488 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10703000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3603500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 14306500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2489000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2489000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 10703000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6092500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 16795500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 10703000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6092500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 16795500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34304.487179 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34649.038462 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34390.625000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34569.444444 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34569.444444 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34417.008197 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34417.008197 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9702500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3275000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12977500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9702500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5539500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15242000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9702500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5539500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15242000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.756410 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.384615 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.913462 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31451.388889 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31451.388889 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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