path: root/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000020                       # Number of seconds simulated
sim_ticks                                    20329000                       # Number of ticks simulated
final_tick                                   20329000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 113549                       # Simulator instruction rate (inst/s)
host_op_rate                                   113428                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              891182571                       # Simulator tick rate (ticks/s)
host_mem_usage                                 248724                       # Number of bytes of host memory used
host_seconds                                     0.02                       # Real time elapsed on the host
sim_insts                                        2585                       # Number of instructions simulated
sim_ops                                          2585                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             14400                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              5440                       # Number of bytes read from this memory
system.physmem.bytes_read::total                19840                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        14400                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           14400                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                225                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   310                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            708347681                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            267598013                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               975945693                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       708347681                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          708347681                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           708347681                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           267598013                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              975945693                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           310                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         310                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    19840                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     19840                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::1                   1                       # Per bank write bursts
system.physmem.perBankRdBursts::2                   3                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  24                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  21                       # Per bank write bursts
system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  27                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  48                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  68                       # Per bank write bursts
system.physmem.perBankRdBursts::9                   2                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 15                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 15                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 18                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 52                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 15                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  1                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        20241500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     310                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       246                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                        61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           41                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      429.268293                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     281.421645                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     332.320856                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             10     24.39%     24.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255            6     14.63%     39.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383            4      9.76%     48.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            3      7.32%     56.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            6     14.63%     70.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            2      4.88%     75.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            4      9.76%     85.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            3      7.32%     92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            3      7.32%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             41                       # Bytes accessed per row activation
system.physmem.totQLat                        1774250                       # Total ticks spent queuing
system.physmem.totMemAccLat                   7586750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      1550000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        5723.39                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  24473.39                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         975.95                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      975.95                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           7.62                       # Data bus utilization in percentage
system.physmem.busUtilRead                       7.62                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.25                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        260                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.87                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        65295.16                       # Average gap between requests
system.physmem.pageHitRate                      83.87                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                      83160                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                      45375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                    787800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               10557540                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                 238500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 12729495                       # Total energy per rank (pJ)
system.physmem_0.averagePower              804.010422                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE         825750                       # Time in different power states
system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        14971750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     189000                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     103125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   1185600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               10490850                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 299250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 13284945                       # Total energy per rank (pJ)
system.physmem_1.averagePower              838.894625                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE         457000                       # Time in different power states
system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        14872250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                     794                       # Number of BP lookups
system.cpu.branchPred.condPredicted               394                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               170                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                  562                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                      54                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct              9.608541                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     144                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  2                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups              83                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits                  0                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses               83                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted           32                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                          506                       # DTB read hits
system.cpu.dtb.read_misses                          6                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                      512                       # DTB read accesses
system.cpu.dtb.write_hits                         307                       # DTB write hits
system.cpu.dtb.write_misses                         6                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                     313                       # DTB write accesses
system.cpu.dtb.data_hits                          813                       # DTB hits
system.cpu.dtb.data_misses                         12                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                      825                       # DTB accesses
system.cpu.itb.fetch_hits                         979                       # ITB hits
system.cpu.itb.fetch_misses                        13                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                     992                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                    4                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON        20329000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                            40658                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        2585                       # Number of instructions committed
system.cpu.committedOps                          2585                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                           573                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                              15.728433                       # CPI: cycles per instruction
system.cpu.ipc                               0.063579                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                 189      7.31%      7.31% # Class of committed instruction
system.cpu.op_class_0::IntAlu                    1678     64.91%     72.22% # Class of committed instruction
system.cpu.op_class_0::IntMult                      1      0.04%     72.26% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     72.26% # Class of committed instruction
system.cpu.op_class_0::MemRead                    419     16.21%     88.47% # Class of committed instruction
system.cpu.op_class_0::MemWrite                   298     11.53%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                     2585                       # Class of committed instruction
system.cpu.tickCycles                            5421                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                           35237                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            48.302993                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                 692                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              8.141176                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    48.302993                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.011793                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.011793                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              1673                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             1673                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data          441                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total             441                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          251                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            251                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data           692                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total              692                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data          692                       # number of overall hits
system.cpu.dcache.overall_hits::total             692                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           59                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            59                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           43                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          102                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            102                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          102                       # number of overall misses
system.cpu.dcache.overall_misses::total           102                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      4783500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      4783500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      3258000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      3258000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data      8041500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total      8041500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data      8041500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total      8041500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data          500                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total          500                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data          794                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total          794                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data          794                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total          794                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.118000                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.118000                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.146259                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.146259                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.128463                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.128463                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.128463                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.128463                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81076.271186                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 81076.271186                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75767.441860                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 75767.441860                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 78838.235294                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 78838.235294                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 78838.235294                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 78838.235294                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data           16                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total           16                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data           17                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total           17                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data           17                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total           17                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           58                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           58                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           27                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           27                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4654000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      4654000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2017500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      2017500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6671500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      6671500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6671500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      6671500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.116000                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.116000                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.107053                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.107053                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.107053                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.107053                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80241.379310                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80241.379310                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78488.235294                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78488.235294                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78488.235294                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78488.235294                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           119.197826                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                 754                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               225                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              3.351111                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   119.197826                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.058202                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.058202                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          225                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.109863                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              2183                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             2183                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst          754                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total             754                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst           754                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total              754                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst          754                       # number of overall hits
system.cpu.icache.overall_hits::total             754                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          225                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           225                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          225                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            225                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          225                       # number of overall misses
system.cpu.icache.overall_misses::total           225                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     17116000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     17116000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     17116000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     17116000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     17116000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     17116000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst          979                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total          979                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst          979                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total          979                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst          979                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total          979                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.229826                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.229826                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.229826                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.229826                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.229826                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.229826                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76071.111111                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76071.111111                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76071.111111                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76071.111111                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76071.111111                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76071.111111                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          225                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          225                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          225                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          225                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          225                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          225                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16891000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     16891000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16891000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     16891000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16891000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     16891000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.229826                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.229826                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.229826                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.229826                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.229826                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.229826                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75071.111111                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75071.111111                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75071.111111                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75071.111111                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75071.111111                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75071.111111                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          147.090026                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              283                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   119.314039                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    27.775987                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003641                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.000848                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.004489                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          283                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008636                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             2790                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            2790                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadExReq_misses::cpu.data           27                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           27                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          225                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          225                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data           58                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total           58                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          225                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data           85                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           310                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          225                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
system.cpu.l2cache.overall_misses::total          310                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1977000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      1977000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     16553500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     16553500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4566000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total      4566000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     16553500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      6543000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     23096500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     16553500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      6543000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     23096500                       # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data           27                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          225                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          225                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           58                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total           58                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          225                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data           85                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          310                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          225                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data           85                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          310                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73571.111111                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73571.111111                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78724.137931                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78724.137931                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73571.111111                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76976.470588                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74504.838710                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73571.111111                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76976.470588                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74504.838710                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           27                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          225                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          225                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           58                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total           58                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          225                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          310                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          225                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          310                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1707000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1707000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     14303500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     14303500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      3986000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      3986000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14303500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5693000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     19996500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14303500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5693000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     19996500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63571.111111                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63571.111111                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68724.137931                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68724.137931                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.111111                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66976.470588                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64504.838710                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.111111                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66976.470588                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64504.838710                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests          310                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp           283                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           27                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          225                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq           58                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          450                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               620                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        14400                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              19840                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples          310                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                310    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            310                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         155000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        337500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.7                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        127500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
system.membus.pwrStateResidencyTicks::UNDEFINED     20329000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                283                       # Transaction distribution
system.membus.trans_dist::ReadExReq                27                       # Transaction distribution
system.membus.trans_dist::ReadExResp               27                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           283                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          620                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    620                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        19840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   19840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               310                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     310    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 310                       # Request fanout histogram
system.membus.reqLayer0.occupancy              363000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy            1648250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              8.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------