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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000009 # Number of seconds simulated
sim_ticks 9061000 # Number of ticks simulated
final_tick 9061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 62320 # Simulator instruction rate (inst/s)
host_op_rate 62299 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 236406021 # Simulator tick rate (ticks/s)
host_mem_usage 216020 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
system.physmem.bytes_read::total 17408 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1320825516 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 600375235 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1921200750 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1320825516 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1320825516 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1320825516 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 600375235 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1921200750 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 272 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 17408 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 17408 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 8992500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 272 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1105772 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 6813772 # Sum of mem lat for all requests
system.physmem.totBusLat 1088000 # Total cycles spent in databus access
system.physmem.totBankLat 4620000 # Total cycles spent in bank access
system.physmem.avgQLat 4065.34 # Average queueing delay per request
system.physmem.avgBankLat 16985.29 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 25050.63 # Average memory access latency
system.physmem.avgRdBW 1921.20 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1921.20 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 12.01 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.75 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 228 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33060.66 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 743 # DTB read hits
system.cpu.dtb.read_misses 38 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
system.cpu.dtb.read_accesses 781 # DTB read accesses
system.cpu.dtb.write_hits 387 # DTB write hits
system.cpu.dtb.write_misses 24 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 411 # DTB write accesses
system.cpu.dtb.data_hits 1130 # DTB hits
system.cpu.dtb.data_misses 62 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
system.cpu.dtb.data_accesses 1192 # DTB accesses
system.cpu.itb.fetch_hits 1097 # ITB hits
system.cpu.itb.fetch_misses 30 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1127 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 18123 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 1200 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 612 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 260 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 849 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 266 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 229 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 4258 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 7288 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1200 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 495 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1268 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 917 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 438 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 961 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 1097 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 7579 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.961604 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.365122 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 6311 83.27% 83.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 53 0.70% 83.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 134 1.77% 85.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 102 1.35% 87.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 181 2.39% 89.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 82 1.08% 90.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 68 0.90% 91.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 65 0.86% 92.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 583 7.69% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 7579 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.066214 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.402141 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 5340 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 471 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1207 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 14 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 547 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 173 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 6471 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 547 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 5441 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 165 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1119 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 57 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 6174 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 4474 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 6979 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 6967 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 2706 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1006 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 508 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 5283 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 4254 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 2663 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1563 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 7579 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.561288 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.273203 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 5858 77.29% 77.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 621 8.19% 85.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 415 5.48% 90.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 261 3.44% 94.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 216 2.85% 97.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 132 1.74% 99.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 51 0.67% 99.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10 0.13% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 15 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 7579 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1 2.13% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.13% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 22 46.81% 48.94% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 24 51.06% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 2999 70.50% 70.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.52% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 829 19.49% 90.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 425 9.99% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 4254 # Type of FU issued
system.cpu.iq.rate 0.234729 # Inst issue rate
system.cpu.iq.fu_busy_cnt 47 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011048 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 16186 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 7949 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 3830 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 4294 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 591 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 214 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 547 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 5652 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 1006 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 508 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 155 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 217 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 4043 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 782 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 211 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 363 # number of nop insts executed
system.cpu.iew.exec_refs 1193 # number of memory reference insts executed
system.cpu.iew.exec_branches 672 # Number of branches executed
system.cpu.iew.exec_stores 411 # Number of stores executed
system.cpu.iew.exec_rate 0.223087 # Inst execution rate
system.cpu.iew.wb_sent 3934 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 3836 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1789 # num instructions producing a value
system.cpu.iew.wb_consumers 2358 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.211665 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.758694 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 3067 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 182 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 7032 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.366325 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.202351 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 6145 87.39% 87.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 219 3.11% 90.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 312 4.44% 94.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 120 1.71% 96.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 65 0.92% 97.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 56 0.80% 98.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 33 0.47% 98.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 21 0.30% 99.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 61 0.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 7032 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 709 # Number of memory references committed
system.cpu.commit.loads 415 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 396 # Number of branches committed
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.function_calls 71 # Number of function calls committed.
system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 12367 # The number of ROB reads
system.cpu.rob.rob_writes 11843 # The number of ROB writes
system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 10544 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
system.cpu.cpi 7.592375 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.592375 # CPI: Total CPI of All Threads
system.cpu.ipc 0.131711 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.131711 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 4904 # number of integer regfile reads
system.cpu.int_regfile_writes 2974 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 92.415859 # Cycle average of tags in use
system.cpu.icache.total_refs 849 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.540107 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 92.415859 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.045125 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.045125 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 849 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 849 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 849 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 849 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 849 # number of overall hits
system.cpu.icache.overall_hits::total 849 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses
system.cpu.icache.overall_misses::total 248 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11771499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11771499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11771499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11771499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11771499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11771499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1097 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1097 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1097 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1097 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1097 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1097 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.226071 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.226071 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.226071 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.226071 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.226071 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.226071 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47465.721774 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 47465.721774 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 47465.721774 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 47465.721774 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9118999 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9118999 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9118999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9118999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9118999 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9118999 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170465 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.170465 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.170465 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48764.700535 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48764.700535 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48764.700535 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 48764.700535 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48764.700535 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48764.700535 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 45.370052 # Cycle average of tags in use
system.cpu.dcache.total_refs 789 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 9.282353 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 45.370052 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.011077 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.011077 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 576 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 576 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 789 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 789 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 789 # number of overall hits
system.cpu.dcache.overall_hits::total 789 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 204 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 204 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 204 # number of overall misses
system.cpu.dcache.overall_misses::total 204 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5446500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5446500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4115000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 9561500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 9561500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 9561500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 9561500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 699 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 699 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 993 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 993 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 993 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 993 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175966 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.175966 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.205438 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.205438 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.205438 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.205438 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44280.487805 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 44280.487805 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50802.469136 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 50802.469136 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 46870.098039 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 46870.098039 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.333333 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 119 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 119 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 119 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3349500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3349500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4698500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4698500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4698500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4698500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.087268 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.087268 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.085599 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.085599 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.085599 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.085599 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54909.836066 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54909.836066 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56208.333333 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56208.333333 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55276.470588 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55276.470588 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55276.470588 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55276.470588 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 121.264296 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 92.675015 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 28.589281 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.002828 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000872 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.003701 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 187 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
system.cpu.l2cache.overall_misses::total 272 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8931000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3288500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 12219500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1323500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1323500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 8931000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4612000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13543000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 8931000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4612000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13543000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47759.358289 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53909.836066 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49272.177419 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55145.833333 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55145.833333 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47759.358289 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54258.823529 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 49790.441176 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47759.358289 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54258.823529 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 49790.441176 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 248 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6582780 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2536058 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9118838 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1027024 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1027024 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6582780 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3563082 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 10145862 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6582780 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3563082 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 10145862 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35202.032086 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41574.721311 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36769.508065 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42792.666667 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42792.666667 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|