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---------- Begin Simulation Statistics ----------
sim_seconds 0.000053 # Number of seconds simulated
sim_ticks 52575 # Number of ticks simulated
final_tick 52575 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 18867 # Simulator instruction rate (inst/s)
host_op_rate 18864 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 384805 # Simulator tick rate (ticks/s)
host_mem_usage 145340 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 2285 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 300 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests
system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads
system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes
system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 117 # Delay stalled at the head of the bank queue
system.ruby.dir_cntrl0.memBuffer.totalStalls 117 # Total number of stall cycles
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.180000 # Expected number of stall cycles per request
system.ruby.dir_cntrl0.memBuffer.memBankBusy 63 # memory stalls due to busy bank
system.ruby.dir_cntrl0.memBuffer.memBusBusy 46 # memory stalls due to busy bus
system.ruby.dir_cntrl0.memBuffer.memArbWait 8 # memory stalls due to arbitration
system.ruby.dir_cntrl0.memBuffer.memBankCount | 26 4.00% 4.00% | 14 2.15% 6.15% | 0 0.00% 6.15% | 49 7.54% 13.69% | 21 3.23% 16.92% | 21 3.23% 20.15% | 42 6.46% 26.62% | 25 3.85% 30.46% | 6 0.92% 31.38% | 4 0.62% 32.00% | 7 1.08% 33.08% | 4 0.62% 33.69% | 24 3.69% 37.38% | 42 6.46% 43.85% | 26 4.00% 47.85% | 3 0.46% 48.31% | 5 0.77% 49.08% | 7 1.08% 50.15% | 7 1.08% 51.23% | 18 2.77% 54.00% | 10 1.54% 55.54% | 29 4.46% 60.00% | 15 2.31% 62.31% | 50 7.69% 70.00% | 19 2.92% 72.92% | 5 0.77% 73.69% | 6 0.92% 74.62% | 16 2.46% 77.08% | 14 2.15% 79.23% | 24 3.69% 82.92% | 19 2.92% 85.85% | 92 14.15% 100.00% # Number of accesses per bank
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 650 # Number of accesses per bank
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 52575 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 52575 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.ruby.l2_cntrl0.L1_GET_INSTR 300 0.00% 0.00%
system.ruby.l2_cntrl0.L1_GETS 204 0.00% 0.00%
system.ruby.l2_cntrl0.L1_GETX 68 0.00% 0.00%
system.ruby.l2_cntrl0.L1_PUTX 124 0.00% 0.00%
system.ruby.l2_cntrl0.L2_Replacement 43 0.00% 0.00%
system.ruby.l2_cntrl0.L2_Replacement_clean 496 0.00% 0.00%
system.ruby.l2_cntrl0.Mem_Data 547 0.00% 0.00%
system.ruby.l2_cntrl0.Mem_Ack 539 0.00% 0.00%
system.ruby.l2_cntrl0.WB_Data 62 0.00% 0.00%
system.ruby.l2_cntrl0.Ack_all 369 0.00% 0.00%
system.ruby.l2_cntrl0.Exclusive_Unblock 272 0.00% 0.00%
system.ruby.l2_cntrl0.NP.L1_GET_INSTR 291 0.00% 0.00%
system.ruby.l2_cntrl0.NP.L1_GETS 192 0.00% 0.00%
system.ruby.l2_cntrl0.NP.L1_GETX 64 0.00% 0.00%
system.ruby.l2_cntrl0.SS.L1_GET_INSTR 9 0.00% 0.00%
system.ruby.l2_cntrl0.SS.L2_Replacement_clean 286 0.00% 0.00%
system.ruby.l2_cntrl0.M.L1_GETS 12 0.00% 0.00%
system.ruby.l2_cntrl0.M.L1_GETX 4 0.00% 0.00%
system.ruby.l2_cntrl0.M.L2_Replacement 39 0.00% 0.00%
system.ruby.l2_cntrl0.M.L2_Replacement_clean 69 0.00% 0.00%
system.ruby.l2_cntrl0.MT.L1_PUTX 124 0.00% 0.00%
system.ruby.l2_cntrl0.MT.L2_Replacement 4 0.00% 0.00%
system.ruby.l2_cntrl0.MT.L2_Replacement_clean 141 0.00% 0.00%
system.ruby.l2_cntrl0.M_I.Mem_Ack 539 0.00% 0.00%
system.ruby.l2_cntrl0.MT_I.WB_Data 2 0.00% 0.00%
system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
system.ruby.l2_cntrl0.MCT_I.WB_Data 60 0.00% 0.00%
system.ruby.l2_cntrl0.MCT_I.Ack_all 81 0.00% 0.00%
system.ruby.l2_cntrl0.I_I.Ack_all 286 0.00% 0.00%
system.ruby.l2_cntrl0.ISS.Mem_Data 192 0.00% 0.00%
system.ruby.l2_cntrl0.IS.Mem_Data 291 0.00% 0.00%
system.ruby.l2_cntrl0.IM.Mem_Data 64 0.00% 0.00%
system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 272 0.00% 0.00%
system.ruby.l1_cntrl0.Load 415 0.00% 0.00%
system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00%
system.ruby.l1_cntrl0.Store 294 0.00% 0.00%
system.ruby.l1_cntrl0.Inv 431 0.00% 0.00%
system.ruby.l1_cntrl0.L1_Replacement 502 0.00% 0.00%
system.ruby.l1_cntrl0.Data_Exclusive 204 0.00% 0.00%
system.ruby.l1_cntrl0.Data_all_Acks 368 0.00% 0.00%
system.ruby.l1_cntrl0.WB_Ack 124 0.00% 0.00%
system.ruby.l1_cntrl0.NP.Load 182 0.00% 0.00%
system.ruby.l1_cntrl0.NP.Ifetch 270 0.00% 0.00%
system.ruby.l1_cntrl0.NP.Store 58 0.00% 0.00%
system.ruby.l1_cntrl0.NP.Inv 162 0.00% 0.00%
system.ruby.l1_cntrl0.I.Load 22 0.00% 0.00%
system.ruby.l1_cntrl0.I.Ifetch 30 0.00% 0.00%
system.ruby.l1_cntrl0.I.Store 10 0.00% 0.00%
system.ruby.l1_cntrl0.I.L1_Replacement 206 0.00% 0.00%
system.ruby.l1_cntrl0.S.Ifetch 2285 0.00% 0.00%
system.ruby.l1_cntrl0.S.Inv 124 0.00% 0.00%
system.ruby.l1_cntrl0.S.L1_Replacement 172 0.00% 0.00%
system.ruby.l1_cntrl0.E.Load 140 0.00% 0.00%
system.ruby.l1_cntrl0.E.Store 41 0.00% 0.00%
system.ruby.l1_cntrl0.E.Inv 83 0.00% 0.00%
system.ruby.l1_cntrl0.E.L1_Replacement 79 0.00% 0.00%
system.ruby.l1_cntrl0.M.Load 71 0.00% 0.00%
system.ruby.l1_cntrl0.M.Store 185 0.00% 0.00%
system.ruby.l1_cntrl0.M.Inv 62 0.00% 0.00%
system.ruby.l1_cntrl0.M.L1_Replacement 45 0.00% 0.00%
system.ruby.l1_cntrl0.IS.Data_Exclusive 204 0.00% 0.00%
system.ruby.l1_cntrl0.IS.Data_all_Acks 300 0.00% 0.00%
system.ruby.l1_cntrl0.IM.Data_all_Acks 68 0.00% 0.00%
system.ruby.l1_cntrl0.M_I.WB_Ack 124 0.00% 0.00%
system.ruby.dir_cntrl0.Fetch 547 0.00% 0.00%
system.ruby.dir_cntrl0.Data 103 0.00% 0.00%
system.ruby.dir_cntrl0.Memory_Data 547 0.00% 0.00%
system.ruby.dir_cntrl0.Memory_Ack 103 0.00% 0.00%
system.ruby.dir_cntrl0.CleanReplacement 436 0.00% 0.00%
system.ruby.dir_cntrl0.I.Fetch 547 0.00% 0.00%
system.ruby.dir_cntrl0.M.Data 103 0.00% 0.00%
system.ruby.dir_cntrl0.M.CleanReplacement 436 0.00% 0.00%
system.ruby.dir_cntrl0.IM.Memory_Data 547 0.00% 0.00%
system.ruby.dir_cntrl0.MI.Memory_Ack 103 0.00% 0.00%
---------- End Simulation Statistics ----------
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