blob: f1ed0212f697082a0d2553c7b54a3a8c276a2cfc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000035 # Number of seconds simulated
sim_ticks 35432 # Number of ticks simulated
final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 14099 # Simulator instruction rate (inst/s)
host_op_rate 14097 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 193809 # Simulator tick rate (ticks/s)
host_mem_usage 145312 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses
system.ruby.dir_cntrl0.memBuffer.memReq 522 # Total number of memory requests
system.ruby.dir_cntrl0.memBuffer.memRead 441 # Number of memory reads
system.ruby.dir_cntrl0.memBuffer.memWrite 81 # Number of memory writes
system.ruby.dir_cntrl0.memBuffer.memRefresh 246 # Number of memory refreshes
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 39 # Delay stalled at the head of the bank queue
system.ruby.dir_cntrl0.memBuffer.totalStalls 39 # Total number of stall cycles
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.074713 # Expected number of stall cycles per request
system.ruby.dir_cntrl0.memBuffer.memBankBusy 15 # memory stalls due to busy bank
system.ruby.dir_cntrl0.memBuffer.memBusBusy 15 # memory stalls due to busy bus
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround
system.ruby.dir_cntrl0.memBuffer.memArbWait 5 # memory stalls due to arbitration
system.ruby.dir_cntrl0.memBuffer.memBankCount | 18 3.45% 3.45% | 10 1.92% 5.36% | 0 0.00% 5.36% | 36 6.90% 12.26% | 20 3.83% 16.09% | 19 3.64% 19.73% | 31 5.94% 25.67% | 22 4.21% 29.89% | 5 0.96% 30.84% | 4 0.77% 31.61% | 7 1.34% 32.95% | 4 0.77% 33.72% | 22 4.21% 37.93% | 41 7.85% 45.79% | 22 4.21% 50.00% | 3 0.57% 50.57% | 4 0.77% 51.34% | 6 1.15% 52.49% | 7 1.34% 53.83% | 13 2.49% 56.32% | 10 1.92% 58.24% | 18 3.45% 61.69% | 14 2.68% 64.37% | 41 7.85% 72.22% | 16 3.07% 75.29% | 5 0.96% 76.25% | 5 0.96% 77.20% | 12 2.30% 79.50% | 13 2.49% 81.99% | 18 3.45% 85.44% | 14 2.68% 88.12% | 62 11.88% 100.00% # Number of accesses per bank
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 522 # Number of accesses per bank
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 35432 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 35432 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.ruby.l1_cntrl0.Load 422 0.00% 0.00%
system.ruby.l1_cntrl0.Ifetch 2591 0.00% 0.00%
system.ruby.l1_cntrl0.Store 298 0.00% 0.00%
system.ruby.l1_cntrl0.L2_Replacement 425 0.00% 0.00%
system.ruby.l1_cntrl0.L1_to_L2 502 0.00% 0.00%
system.ruby.l1_cntrl0.Trigger_L2_to_L1D 47 0.00% 0.00%
system.ruby.l1_cntrl0.Trigger_L2_to_L1I 22 0.00% 0.00%
system.ruby.l1_cntrl0.Complete_L2_to_L1 69 0.00% 0.00%
system.ruby.l1_cntrl0.Exclusive_Data 441 0.00% 0.00%
system.ruby.l1_cntrl0.Writeback_Ack 425 0.00% 0.00%
system.ruby.l1_cntrl0.All_acks_no_sharers 441 0.00% 0.00%
system.ruby.l1_cntrl0.I.Load 146 0.00% 0.00%
system.ruby.l1_cntrl0.I.Ifetch 248 0.00% 0.00%
system.ruby.l1_cntrl0.I.Store 47 0.00% 0.00%
system.ruby.l1_cntrl0.M.Load 109 0.00% 0.00%
system.ruby.l1_cntrl0.M.Ifetch 2315 0.00% 0.00%
system.ruby.l1_cntrl0.M.Store 35 0.00% 0.00%
system.ruby.l1_cntrl0.M.L2_Replacement 344 0.00% 0.00%
system.ruby.l1_cntrl0.M.L1_to_L2 397 0.00% 0.00%
system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D 23 0.00% 0.00%
system.ruby.l1_cntrl0.M.Trigger_L2_to_L1I 22 0.00% 0.00%
system.ruby.l1_cntrl0.MM.Load 124 0.00% 0.00%
system.ruby.l1_cntrl0.MM.Store 201 0.00% 0.00%
system.ruby.l1_cntrl0.MM.L2_Replacement 81 0.00% 0.00%
system.ruby.l1_cntrl0.MM.L1_to_L2 105 0.00% 0.00%
system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D 24 0.00% 0.00%
system.ruby.l1_cntrl0.MR.Load 22 0.00% 0.00%
system.ruby.l1_cntrl0.MR.Ifetch 22 0.00% 0.00%
system.ruby.l1_cntrl0.MR.Store 1 0.00% 0.00%
system.ruby.l1_cntrl0.MMR.Load 14 0.00% 0.00%
system.ruby.l1_cntrl0.MMR.Store 10 0.00% 0.00%
system.ruby.l1_cntrl0.IM.Exclusive_Data 47 0.00% 0.00%
system.ruby.l1_cntrl0.M_W.All_acks_no_sharers 394 0.00% 0.00%
system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers 47 0.00% 0.00%
system.ruby.l1_cntrl0.IS.Exclusive_Data 394 0.00% 0.00%
system.ruby.l1_cntrl0.MI.Load 7 0.00% 0.00%
system.ruby.l1_cntrl0.MI.Ifetch 6 0.00% 0.00%
system.ruby.l1_cntrl0.MI.Store 4 0.00% 0.00%
system.ruby.l1_cntrl0.MI.Writeback_Ack 425 0.00% 0.00%
system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 45 0.00% 0.00%
system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 24 0.00% 0.00%
system.ruby.dir_cntrl0.GETX 51 0.00% 0.00%
system.ruby.dir_cntrl0.GETS 410 0.00% 0.00%
system.ruby.dir_cntrl0.PUT 425 0.00% 0.00%
system.ruby.dir_cntrl0.UnblockM 440 0.00% 0.00%
system.ruby.dir_cntrl0.Writeback_Exclusive_Clean 344 0.00% 0.00%
system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty 81 0.00% 0.00%
system.ruby.dir_cntrl0.Memory_Data 441 0.00% 0.00%
system.ruby.dir_cntrl0.Memory_Ack 81 0.00% 0.00%
system.ruby.dir_cntrl0.NO.PUT 425 0.00% 0.00%
system.ruby.dir_cntrl0.E.GETX 47 0.00% 0.00%
system.ruby.dir_cntrl0.E.GETS 394 0.00% 0.00%
system.ruby.dir_cntrl0.NO_B.UnblockM 440 0.00% 0.00%
system.ruby.dir_cntrl0.NO_B_W.Memory_Data 441 0.00% 0.00%
system.ruby.dir_cntrl0.WB.GETX 4 0.00% 0.00%
system.ruby.dir_cntrl0.WB.GETS 14 0.00% 0.00%
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean 344 0.00% 0.00%
system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00%
system.ruby.dir_cntrl0.WB_E_W.GETS 2 0.00% 0.00%
system.ruby.dir_cntrl0.WB_E_W.Memory_Ack 81 0.00% 0.00%
---------- End Simulation Statistics ----------
|
