blob: fab61398172762cc4a68ce86cbbda9c319b51d14 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000017 # Number of seconds simulated
sim_ticks 16769000 # Number of ticks simulated
final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 308591 # Simulator instruction rate (inst/s)
host_op_rate 307918 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1999557615 # Simulator tick rate (ticks/s)
host_mem_usage 213304 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory
system.physmem.bytes_read::total 15680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 622100304 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 312958435 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 935058739 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 622100304 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 622100304 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 622100304 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 312958435 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 935058739 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 33538 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 33538 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use
system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 80.003762 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.039064 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.039064 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits
system.cpu.icache.overall_hits::total 2423 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
system.cpu.icache.overall_misses::total 163 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 9128000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 9128000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 9128000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 9128000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 9128000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 47.418751 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.011577 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.011577 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
system.cpu.dcache.overall_hits::total 627 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
system.cpu.dcache.overall_misses::total 82 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1512000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1512000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 4592000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 4592000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 4592000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 4592000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 80.120406 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 26.980800 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.002445 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.003268 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
system.cpu.l2cache.overall_misses::total 245 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
