path: root/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
final_tick                                   27963000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate                                  75358                       # Simulator instruction rate (inst/s)
host_mem_usage                                 292860                       # Number of bytes of host memory used
host_op_rate                                    93985                       # Simulator op (including micro ops) rate (op/s)
host_seconds                                     0.06                       # Real time elapsed on the host
host_tick_rate                              457698243                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        4604                       # Number of instructions simulated
sim_ops                                          5742                       # Number of ops (including micro ops) simulated
sim_seconds                                  0.000028                       # Number of seconds simulated
sim_ticks                                    27963000                       # Number of ticks simulated
system.clk_domain.clock                          1000                       # Clock period in ticks
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             21.219512                       # BTB Hit Percentage
system.cpu.branchPred.BTBHits                     348                       # Number of BTB hits
system.cpu.branchPred.BTBLookups                 1640                       # Number of BTB lookups
system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
system.cpu.branchPred.condIncorrect               349                       # Number of conditional branches incorrect
system.cpu.branchPred.condPredicted              1370                       # Number of conditional branches predicted
system.cpu.branchPred.lookups                    2005                       # Number of BP lookups
system.cpu.branchPred.usedRAS                     202                       # Number of times the RAS was used to get a target.
system.cpu.committedInsts                        4604                       # Number of instructions committed
system.cpu.committedOps                          5742                       # Number of ops (including micro ops) committed
system.cpu.cpi                              12.147263                       # CPI: cycles per instruction
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           11                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::cpu.inst           11                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses::cpu.inst         1318                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1318                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60367.304348                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60367.304348                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60667.563107                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60667.563107                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits::cpu.inst         1203                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1203                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency::cpu.inst      6942240                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      6942240                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.087253                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.087253                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::cpu.inst          115                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      6248759                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      6248759                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.078149                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.078149                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          103                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          103                       # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses::cpu.inst           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::cpu.inst           11                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::cpu.inst          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.179104                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.179104                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66843.023256                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66843.023256                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits::cpu.inst          846                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            846                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency::cpu.inst      4600500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      4600500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.073384                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.073384                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::cpu.inst           67                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           67                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           24                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total           24                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2874250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      2874250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.047097                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           43                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           43                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses::cpu.inst         2231                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2231                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63421.648352                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 63421.648352                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62486.363014                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62486.363014                       # average overall mshr miss latency
system.cpu.dcache.demand_hits::cpu.inst          2049                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             2049                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency::cpu.inst     11542740                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     11542740                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::cpu.inst     0.081578                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.081578                       # miss rate for demand accesses
system.cpu.dcache.demand_misses::cpu.inst          182                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits::cpu.inst           36                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total           36                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      9123009                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      9123009                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.065442                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.065442                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses::cpu.inst          146                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses::cpu.inst         2231                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2231                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63421.648352                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 63421.648352                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62486.363014                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62486.363014                       # average overall mshr miss latency
system.cpu.dcache.overall_hits::cpu.inst         2049                       # number of overall hits
system.cpu.dcache.overall_hits::total            2049                       # number of overall hits
system.cpu.dcache.overall_miss_latency::cpu.inst     11542740                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     11542740                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::cpu.inst     0.081578                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.081578                       # miss rate for overall accesses
system.cpu.dcache.overall_misses::cpu.inst          182                       # number of overall misses
system.cpu.dcache.overall_misses::total           182                       # number of overall misses
system.cpu.dcache.overall_mshr_hits::cpu.inst           36                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total           36                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      9123009                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      9123009                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.065442                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.065442                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses::cpu.inst          146                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
system.cpu.dcache.tags.avg_refs             14.184932                       # Average number of references to valid blocks.
system.cpu.dcache.tags.data_accesses             4652                       # Number of data accesses
system.cpu.dcache.tags.occ_blocks::cpu.inst    86.831207                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.021199                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.021199                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.tag_accesses              4652                       # Number of tag accesses
system.cpu.dcache.tags.tagsinuse            86.831207                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                2071                       # Total number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.discardedOps                          1297                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.icache.ReadReq_accesses::cpu.inst         2307                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         2307                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66806.250000                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 66806.250000                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64396.875000                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64396.875000                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits::cpu.inst         1987                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1987                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency::cpu.inst     21378000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     21378000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138708                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.138708                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::cpu.inst          320                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           320                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20607000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     20607000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138708                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138708                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          320                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          320                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses::cpu.inst         2307                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         2307                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66806.250000                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 66806.250000                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64396.875000                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 64396.875000                       # average overall mshr miss latency
system.cpu.icache.demand_hits::cpu.inst          1987                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1987                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency::cpu.inst     21378000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     21378000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::cpu.inst     0.138708                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.138708                       # miss rate for demand accesses
system.cpu.icache.demand_misses::cpu.inst          320                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            320                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20607000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     20607000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138708                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.138708                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses::cpu.inst          320                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          320                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses::cpu.inst         2307                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         2307                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::cpu.inst 66806.250000                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 66806.250000                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64396.875000                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 64396.875000                       # average overall mshr miss latency
system.cpu.icache.overall_hits::cpu.inst         1987                       # number of overall hits
system.cpu.icache.overall_hits::total            1987                       # number of overall hits
system.cpu.icache.overall_miss_latency::cpu.inst     21378000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     21378000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate::cpu.inst     0.138708                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.138708                       # miss rate for overall accesses
system.cpu.icache.overall_misses::cpu.inst          320                       # number of overall misses
system.cpu.icache.overall_misses::total           320                       # number of overall misses
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20607000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     20607000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138708                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.138708                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses::cpu.inst          320                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          320                       # number of overall MSHR misses
system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
system.cpu.icache.tags.avg_refs              6.209375                       # Average number of references to valid blocks.
system.cpu.icache.tags.data_accesses             4934                       # Number of data accesses
system.cpu.icache.tags.occ_blocks::cpu.inst   161.718196                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.078964                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.078964                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          317                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.154785                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.replacements                 3                       # number of replacements
system.cpu.icache.tags.sampled_refs               320                       # Sample count of references to valid blocks.
system.cpu.icache.tags.tag_accesses              4934                       # Number of tag accesses
system.cpu.icache.tags.tagsinuse           161.718196                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                1987                       # Total number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.idleCycles                           44980                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.ipc                               0.082323                       # IPC: instructions per cycle
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses::cpu.inst           43                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65831.395349                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65831.395349                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53308.139535                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53308.139535                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2830750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      2830750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses::cpu.inst           43                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      2292250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2292250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           43                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses::cpu.inst          423                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          423                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67507.124352                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67507.124352                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55150.530504                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55150.530504                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits::cpu.inst           37                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total             37                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     26057750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     26057750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.912530                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.912530                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses::cpu.inst          386                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          386                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            9                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            9                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     20791750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20791750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.891253                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.891253                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          377                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          377                       # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses::cpu.inst          466                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          466                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67339.160839                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 67339.160839                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54961.904762                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54961.904762                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits::cpu.inst           37                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total              37                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency::cpu.inst     28888500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     28888500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.920601                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.920601                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses::cpu.inst          429                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           429                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits::cpu.inst            9                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            9                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23084000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     23084000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.901288                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.901288                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          420                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          420                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses::cpu.inst          466                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          466                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67339.160839                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 67339.160839                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54961.904762                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54961.904762                       # average overall mshr miss latency
system.cpu.l2cache.overall_hits::cpu.inst           37                       # number of overall hits
system.cpu.l2cache.overall_hits::total             37                       # number of overall hits
system.cpu.l2cache.overall_miss_latency::cpu.inst     28888500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     28888500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.920601                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.920601                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses::cpu.inst          429                       # number of overall misses
system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits::cpu.inst            9                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            9                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23084000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     23084000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.901288                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.901288                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          420                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          420                       # number of overall MSHR misses
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
system.cpu.l2cache.tags.avg_refs             0.098143                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.data_accesses            4148                       # Number of data accesses
system.cpu.l2cache.tags.occ_blocks::cpu.inst   195.926239                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005979                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.005979                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          377                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011505                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.sampled_refs              377                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.tag_accesses             4148                       # Number of tag accesses
system.cpu.l2cache.tags.tagsinuse          195.926239                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                 37                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.numCycles                            55926                       # number of cpu cycles simulated
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.tickCycles                           10946                       # Number of cycles that the CPU actually ticked
system.cpu.toL2Bus.data_through_bus             29824                       # Total data (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          640                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          292                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               932                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy         233000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        545500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        234491                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.throughput              1066552230                       # Throughput (bytes/s)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20480                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total          29824                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.trans_dist::ReadReq            423                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           423                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
system.cpu.workload.num_syscalls                   13                       # Number of system calls
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.membus.data_through_bus                  26880                       # Total data (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          840                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    840                       # Packet count per connected master and slave (bytes)
system.membus.reqLayer0.occupancy              485500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3923500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             14.0                       # Layer utilization (%)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.throughput                    961270250                       # Throughput (bytes/s)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               26880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadReq                 377                       # Transaction distribution
system.membus.trans_dist::ReadResp                377                       # Transaction distribution
system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgGap                        66375.00                       # Average gap between requests
system.physmem.avgMemAccLat                  24369.64                       # Average memory access latency per DRAM burst
system.physmem.avgQLat                        5619.64                       # Average queueing delay per DRAM burst
system.physmem.avgRdBW                         961.27                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgRdBWSys                      961.27                       # Average system read bandwidth in MiByte/s
system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.busUtil                           7.51                       # Data bus utilization in percentage
system.physmem.busUtilRead                       7.51                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.bw_inst_read::cpu.inst       695776562                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          695776562                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst            961270250                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               961270250                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           961270250                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              961270250                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytesPerActivate::samples           65                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      389.907692                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     267.054058                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     328.238562                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             11     16.92%     16.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           17     26.15%     43.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           12     18.46%     61.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            7     10.77%     72.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            3      4.62%     76.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            2      3.08%     80.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      4.62%     84.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           10     15.38%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             65                       # Bytes accessed per row activation
system.physmem.bytesReadDRAM                    26880                       # Total number of bytes read from DRAM
system.physmem.bytesReadSys                     26880                       # Total read bytes from the system interface side
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.bytes_inst_read::cpu.inst        19456                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           19456                       # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.inst             26880                       # Number of bytes read from this memory
system.physmem.bytes_read::total                26880                       # Number of bytes read from this memory
system.physmem.memoryStateTime::IDLE            12000                       # Time in different power states
system.physmem.memoryStateTime::REF            780000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT          22869500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.num_reads::cpu.inst                420                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   420                       # Number of read requests responded to by this memory
system.physmem.pageHitRate                      82.62                       # Row buffer hit rate, read and write combined
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.perBankRdBursts::0                  91                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  51                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  20                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  42                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  22                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  41                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  36                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  12                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   6                       # Per bank write bursts
system.physmem.perBankRdBursts::9                   6                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 27                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 42                       # Per bank write bursts
system.physmem.perBankRdBursts::12                  9                       # Per bank write bursts
system.physmem.perBankRdBursts::13                  8                       # Per bank write bursts
system.physmem.perBankRdBursts::14                  0                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  7                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.rdQLenPdf::0                       347                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                        65                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.readBursts                         420                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     420                       # Read request sizes (log2)
system.physmem.readReqs                           420                       # Number of read requests accepted
system.physmem.readRowHitRate                   82.62                       # Row buffer hit rate for reads
system.physmem.readRowHits                        347                       # Number of row buffer hits during reads
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.totBusLat                      2100000                       # Total ticks spent in databus transfers
system.physmem.totGap                        27877500                       # Total gap between requests
system.physmem.totMemAccLat                  10235250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat                        2360250                       # Total ticks spent queuing
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.voltage_domain.voltage                       1                       # Voltage in Volts

---------- End Simulation Statistics   ----------