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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000028 # Number of seconds simulated
sim_ticks 27981000 # Number of ticks simulated
final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 65720 # Simulator instruction rate (inst/s)
host_op_rate 76928 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 399296424 # Simulator tick rate (ticks/s)
host_mem_usage 250660 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 4604 # Number of instructions simulated
sim_ops 5390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 26944 # Number of bytes read from this memory
system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 421 # Number of read requests responded to by this memory
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 962939137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 962939137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 421 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 91 # Per bank write bursts
system.physmem.perBankRdBursts::1 52 # Per bank write bursts
system.physmem.perBankRdBursts::2 20 # Per bank write bursts
system.physmem.perBankRdBursts::3 43 # Per bank write bursts
system.physmem.perBankRdBursts::4 22 # Per bank write bursts
system.physmem.perBankRdBursts::5 41 # Per bank write bursts
system.physmem.perBankRdBursts::6 36 # Per bank write bursts
system.physmem.perBankRdBursts::7 12 # Per bank write bursts
system.physmem.perBankRdBursts::8 5 # Per bank write bursts
system.physmem.perBankRdBursts::9 6 # Per bank write bursts
system.physmem.perBankRdBursts::10 27 # Per bank write bursts
system.physmem.perBankRdBursts::11 42 # Per bank write bursts
system.physmem.perBankRdBursts::12 9 # Per bank write bursts
system.physmem.perBankRdBursts::13 8 # Per bank write bursts
system.physmem.perBankRdBursts::14 0 # Per bank write bursts
system.physmem.perBankRdBursts::15 7 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 27895500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 421 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
system.physmem.totQLat 2478000 # Total ticks spent queuing
system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.52 # Data bus utilization in percentage
system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 350 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 66260.10 # Average gap between requests
system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 12000 # Time in different power states
system.physmem.memoryStateTime::REF 780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22840500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ)
system.physmem.averagePower::0 856.107753 # Core power per rank (mW)
system.physmem.averagePower::1 786.272135 # Core power per rank (mW)
system.cpu.branchPred.lookups 1926 # Number of BP lookups
system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups
system.cpu.branchPred.BTBHits 326 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 55962 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4604 # Number of instructions committed
system.cpu.committedOps 5390 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 12.155083 # CPI: cycles per instruction
system.cpu.ipc 0.082270 # IPC: instructions per cycle
system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked
system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst 86.669090 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst 1054 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst 1900 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst 1900 # number of overall hits
system.cpu.dcache.overall_hits::total 1900 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses
system.cpu.dcache.overall_misses::total 182 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6708741 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4576500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 11285241 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 11285241 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 1169 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst 2082 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst 2082 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098375 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst 0.087416 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.087416 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 58336.878261 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68305.970149 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 24 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6015258 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2857500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 8872758 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 8872758 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088109 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 58400.563107 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66453.488372 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 3 # number of replacements
system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4804 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
system.cpu.icache.overall_hits::total 1919 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
system.cpu.icache.overall_misses::total 322 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.981905 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005981 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
system.cpu.l2cache.overall_hits::total 39 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses
system.cpu.l2cache.overall_misses::total 429 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26149000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2814500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 28963500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 28963500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 425 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 468 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 468 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908235 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.908235 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916667 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916667 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67743.523316 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65453.488372 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 378 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 378 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 421 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 421 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20940500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2273500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23214000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23214000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889412 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55398.148148 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52872.093023 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.membus.trans_dist::ReadReq 378 # Transaction distribution
system.membus.trans_dist::ReadResp 378 # Transaction distribution
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 421 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 421 # Request fanout histogram
system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
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