path: root/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000030                       # Number of seconds simulated
sim_ticks                                    29977500                       # Number of ticks simulated
final_tick                                   29977500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  89930                       # Simulator instruction rate (inst/s)
host_op_rate                                   105235                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              584953104                       # Simulator tick rate (ticks/s)
host_mem_usage                                 268772                       # Number of bytes of host memory used
host_seconds                                     0.05                       # Real time elapsed on the host
sim_insts                                        4605                       # Number of instructions simulated
sim_ops                                          5391                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             19520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              7424                       # Number of bytes read from this memory
system.physmem.bytes_read::total                26944                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        19520                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           19520                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                305                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                116                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   421                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            651155033                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            247652406                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               898807439                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       651155033                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          651155033                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           651155033                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           247652406                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              898807439                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           421                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         421                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    26944                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     26944                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  91                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  52                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  20                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  43                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  22                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  41                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  36                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  12                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   5                       # Per bank write bursts
system.physmem.perBankRdBursts::9                   6                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 27                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 42                       # Per bank write bursts
system.physmem.perBankRdBursts::12                  9                       # Per bank write bursts
system.physmem.perBankRdBursts::13                  8                       # Per bank write bursts
system.physmem.perBankRdBursts::14                  0                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  7                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        29886000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     421                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       347                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                        66                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           62                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      408.774194                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     287.393665                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     328.869570                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127              8     12.90%     12.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           17     27.42%     40.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           12     19.35%     59.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            5      8.06%     67.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            4      6.45%     74.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            3      4.84%     79.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      4.84%     83.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            1      1.61%     85.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            9     14.52%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             62                       # Bytes accessed per row activation
system.physmem.totQLat                        2113500                       # Total ticks spent queuing
system.physmem.totMemAccLat                  10007250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2105000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        5020.19                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  23770.19                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         898.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      898.81                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           7.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       7.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        350                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.14                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        70988.12                       # Average gap between requests
system.physmem.pageHitRate                      83.14                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     272160                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     148500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   1973400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               16099650                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                  48750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 20068140                       # Total energy per rank (pJ)
system.physmem_0.averagePower              849.669860                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE          12500                       # Time in different power states
system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        22840000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     128520                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                      70125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                    694200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               15745680                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 359250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 18523455                       # Total energy per rank (pJ)
system.physmem_1.averagePower              784.269066                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE        1654750                       # Time in different power states
system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        22324250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                    1949                       # Number of BP lookups
system.cpu.branchPred.condPredicted              1165                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               351                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 1641                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     316                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             19.256551                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     222                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups             133                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits                  8                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses              125                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted           62                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   13                       # Number of system calls
system.cpu.numCycles                            59955                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        4605                       # Number of instructions committed
system.cpu.committedOps                          5391                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                          1202                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                              13.019544                       # CPI: cycles per instruction
system.cpu.ipc                               0.076808                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu                    3419     63.42%     63.42% # Class of committed instruction
system.cpu.op_class_0::IntMult                      4      0.07%     63.49% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                3      0.06%     63.55% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     63.55% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     63.55% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     63.55% # Class of committed instruction
system.cpu.op_class_0::MemRead                   1027     19.05%     82.60% # Class of committed instruction
system.cpu.op_class_0::MemWrite                   938     17.40%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                     5391                       # Class of committed instruction
system.cpu.tickCycles                           10654                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                           49301                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            86.495507                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1916                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             13.123288                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    86.495507                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.021117                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.021117                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4342                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4342                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          846                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            846                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data          1894                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1894                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1894                       # number of overall hits
system.cpu.dcache.overall_hits::total            1894                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          115                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           67                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           67                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          182                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          182                       # number of overall misses
system.cpu.dcache.overall_misses::total           182                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      6977500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      6977500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      5011500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      5011500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     11989000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     11989000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     11989000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     11989000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2076                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2076                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2076                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2076                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098882                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.098882                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.073384                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.073384                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.087669                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.087669                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.087669                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.087669                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 65873.626374                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 65873.626374                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           12                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data           24                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total           24                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data           36                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total           36                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data           36                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total           36                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          103                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          103                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           43                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           43                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6370500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      6370500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3194000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      3194000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9564500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      9564500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9564500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      9564500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088564                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088564                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070328                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.070328                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070328                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.070328                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973                       # average overall mshr miss latency
system.cpu.icache.tags.replacements                 4                       # number of replacements
system.cpu.icache.tags.tagsinuse           162.122030                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                1926                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               323                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              5.962848                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   162.122030                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.079161                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.079161                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          319                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.155762                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              4821                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             4821                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         1926                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1926                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          1926                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1926                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         1926                       # number of overall hits
system.cpu.icache.overall_hits::total            1926                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          323                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           323                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          323                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            323                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          323                       # number of overall misses
system.cpu.icache.overall_misses::total           323                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     23530000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     23530000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     23530000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     23530000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     23530000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     23530000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         2249                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         2249                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         2249                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         2249                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         2249                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         2249                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.143619                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.143619                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.143619                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.143619                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.143619                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.143619                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72848.297214                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 72848.297214                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72848.297214                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 72848.297214                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 72848.297214                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks            4                       # number of writebacks
system.cpu.icache.writebacks::total                 4                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          323                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          323                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          323                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          323                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          323                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          323                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23207000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     23207000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23207000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     23207000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23207000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     23207000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.143619                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.143619                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.143619                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.143619                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.143619                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.143619                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214                       # average overall mshr miss latency
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          195.781809                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                 43                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              378                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.113757                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   154.633330                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    41.148479                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004719                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.001256                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.005975                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          378                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011536                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             4197                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            4197                       # Number of data accesses
system.cpu.l2cache.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total            3                       # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           18                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total           18                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data           22                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total           22                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst           18                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           22                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total              40                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           18                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           22                       # number of overall hits
system.cpu.l2cache.overall_hits::total             40                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data           43                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          305                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          305                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data           81                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total           81                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          305                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          124                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           429                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          305                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          124                       # number of overall misses
system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3129500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      3129500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     22515500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     22515500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5956000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total      5956000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     22515500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      9085500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     31601000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     22515500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      9085500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     31601000                       # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          323                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          323                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          103                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total          103                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          323                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          146                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          469                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          323                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          146                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          469                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.944272                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.944272                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.786408                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.786408                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.944272                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.849315                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.914712                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.944272                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.849315                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.914712                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            8                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            8                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           43                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          305                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          305                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           73                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total           73                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          305                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          116                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          421                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          305                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          116                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          421                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2699500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2699500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     19465500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     19465500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4696000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4696000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19465500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7395500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     26861000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19465500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7395500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     26861000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.944272                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.944272                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.708738                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.708738                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.944272                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.794521                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.897655                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.944272                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.794521                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.897655                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests          473                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests           51                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp           426                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean            4                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          323                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq          103                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          650                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          292                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               942                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              30272                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples          469                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.102345                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.303426                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                421     89.77%     89.77% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                 48     10.23%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            469                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         240500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        484500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        222992                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
system.membus.trans_dist::ReadResp                378                       # Transaction distribution
system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           378                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          842                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    842                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26944                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   26944                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples               421                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     421    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 421                       # Request fanout histogram
system.membus.reqLayer0.occupancy              489000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2236750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              7.5                       # Layer utilization (%)

---------- End Simulation Statistics   ----------