path: root/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000016                       # Number of seconds simulated
sim_ticks                                    16487000                       # Number of ticks simulated
final_tick                                   16487000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  33036                       # Simulator instruction rate (inst/s)
host_op_rate                                    38686                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              118603969                       # Simulator tick rate (ticks/s)
host_mem_usage                                 248576                       # Number of bytes of host memory used
host_seconds                                     0.14                       # Real time elapsed on the host
sim_insts                                        4591                       # Number of instructions simulated
sim_ops                                          5377                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             17408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              6912                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher         1728                       # Number of bytes read from this memory
system.physmem.bytes_read::total                26048                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        17408                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           17408                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                272                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                108                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher           27                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   407                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst           1055862194                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            419239401                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher    104809850                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1579911445                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      1055862194                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         1055862194                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          1055862194                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           419239401                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher    104809850                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1579911445                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           408                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         408                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    26112                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     26112                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  88                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  45                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  19                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  45                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  18                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  32                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  37                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  10                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   4                       # Per bank write bursts
system.physmem.perBankRdBursts::9                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 26                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 47                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 17                       # Per bank write bursts
system.physmem.perBankRdBursts::13                  7                       # Per bank write bursts
system.physmem.perBankRdBursts::14                  0                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  6                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        16473500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     408                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       226                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       123                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           63                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      406.349206                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     267.472109                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     352.639181                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             10     15.87%     15.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           20     31.75%     47.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383            9     14.29%     61.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            4      6.35%     68.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            2      3.17%     71.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            3      4.76%     76.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      4.76%     80.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            2      3.17%     84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           10     15.87%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             63                       # Bytes accessed per row activation
system.physmem.totQLat                        3192729                       # Total ticks spent queuing
system.physmem.totMemAccLat                  10842729                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2040000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        7825.32                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  26575.32                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        1583.79                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     1583.79                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                          12.37                       # Data bus utilization in percentage
system.physmem.busUtilRead                      12.37                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.77                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        342                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.82                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        40376.23                       # Average gap between requests
system.physmem.pageHitRate                      83.82                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     317520                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     173250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   2207400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               10796085                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                  29250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 14540625                       # Total energy per rank (pJ)
system.physmem_0.averagePower              918.403600                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE           6500                       # Time in different power states
system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        15319750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     151200                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                      82500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                    881400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               10626795                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 177750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 12936765                       # Total energy per rank (pJ)
system.physmem_1.averagePower              817.101847                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE         860250                       # Time in different power states
system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        15071750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                    2361                       # Number of BP lookups
system.cpu.branchPred.condPredicted              1411                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               506                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                  871                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     473                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             54.305396                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     287                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 56                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   13                       # Number of system calls
system.cpu.numCycles                            32975                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles               6157                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          11322                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        2361                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches                760                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          7387                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    1055                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  111                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           277                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          339                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                      3848                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   178                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              14798                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.892688                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.216053                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                     8580     57.98%     57.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                     2466     16.66%     74.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      512      3.46%     78.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                     3240     21.89%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                14798                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.071600                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.343351                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                     5946                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  3315                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      5035                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   135                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                    367                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                  329                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   163                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                   9887                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  1624                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                    367                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                     7027                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                     950                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           1833                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      4080                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                   541                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                   8892                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                   410                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents                    16                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                     16                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                    453                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands                9276                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 40303                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups             9770                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                18                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                     3782                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 31                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             28                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                       320                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 1789                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1266                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                       8351                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  39                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                      7157                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued               186                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined            2800                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined         7772                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         14798                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.483646                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.864768                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               10589     71.56%     71.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1954     13.20%     84.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                1606     10.85%     95.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 605      4.09%     99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                  44      0.30%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            4                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           14798                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     414     28.91%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.91% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                    469     32.75%     61.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                   549     38.34%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                  4493     62.78%     62.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    5      0.07%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     62.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.89% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 1580     22.08%     84.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1076     15.03%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                   7157                       # Type of FU issued
system.cpu.iq.rate                           0.217043                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                        1432                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.200084                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              30686                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             11179                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses         6571                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                  44                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                 18                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                   8561                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      28                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads               10                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads          762                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          328                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            6                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            21                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                    367                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                     446                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                    24                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts                8404                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  1789                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1266                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 27                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                    19                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect             69                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          290                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  359                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                  6761                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  1400                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               396                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                            14                       # number of nop insts executed
system.cpu.iew.exec_refs                         2417                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1277                       # Number of branches executed
system.cpu.iew.exec_stores                       1017                       # Number of stores executed
system.cpu.iew.exec_rate                     0.205034                       # Inst execution rate
system.cpu.iew.wb_sent                           6630                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                          6587                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                      2990                       # num instructions producing a value
system.cpu.iew.wb_consumers                      5391                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.199757                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.554628                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts            2570                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               346                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        14256                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.377175                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.026651                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        11607     81.42%     81.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         1384      9.71%     91.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          607      4.26%     95.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          292      2.05%     97.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          168      1.18%     98.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5           76      0.53%     99.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6           46      0.32%     99.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           33      0.23%     99.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8           43      0.30%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        14256                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
system.cpu.commit.committedOps                   5377                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           1965                       # Number of memory references committed
system.cpu.commit.loads                          1027                       # Number of loads committed
system.cpu.commit.membars                          12                       # Number of memory barriers committed
system.cpu.commit.branches                       1007                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      4624                       # Number of committed integer instructions.
system.cpu.commit.function_calls                   82                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu             3405     63.33%     63.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult               4      0.07%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     63.40% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.06%     63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead            1027     19.10%     82.56% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite            938     17.44%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total              5377                       # Class of committed instruction
system.cpu.commit.bw_lim_events                    43                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                        22003                       # The number of ROB reads
system.cpu.rob.rob_writes                       16441                       # The number of ROB writes
system.cpu.timesIdled                             222                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           18177                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
system.cpu.committedOps                          5377                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               7.182531                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.182531                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.139227                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.139227                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                     6737                       # number of integer regfile reads
system.cpu.int_regfile_writes                    3765                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.cc_regfile_reads                     24010                       # number of cc regfile reads
system.cpu.cc_regfile_writes                     2910                       # number of cc regfile writes
system.cpu.misc_regfile_reads                    2599                       # number of misc regfile reads
system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
system.cpu.dcache.tags.replacements                 1                       # number of replacements
system.cpu.dcache.tags.tagsinuse            84.720980                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1896                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             13.352113                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    84.720980                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.165471                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.165471                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.275391                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4676                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4676                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         1154                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1154                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          722                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            722                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data            9                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total            9                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data          1876                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1876                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1876                       # number of overall hits
system.cpu.dcache.overall_hits::total            1876                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          178                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           178                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          191                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          191                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data          369                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            369                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          369                       # number of overall misses
system.cpu.dcache.overall_misses::total           369                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      8985992                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      8985992                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      6715000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      6715000                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       112000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       112000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     15700992                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     15700992                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     15700992                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     15700992                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1332                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1332                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2245                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2245                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2245                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2245                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133634                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.133634                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.209200                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.209200                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.181818                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.164365                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.164365                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.164365                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.164365                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        56000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        56000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 42550.113821                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 42550.113821                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          646                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              18                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    35.888889                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           76                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           76                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          150                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          150                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          226                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          226                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          226                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          226                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          102                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           41                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           41                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          143                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          143                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          143                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5294755                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      5294755                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2189500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      2189500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7484255                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      7484255                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7484255                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      7484255                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076577                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076577                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044907                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063697                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.063697                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063697                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.063697                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51909.362745                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51909.362745                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53402.439024                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53402.439024                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52337.447552                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52337.447552                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52337.447552                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52337.447552                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements                42                       # number of replacements
system.cpu.icache.tags.tagsinuse           138.060100                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                3485                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               296                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             11.773649                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   138.060100                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.269649                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.269649                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          254                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.496094                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              7990                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             7990                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         3485                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            3485                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          3485                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             3485                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         3485                       # number of overall hits
system.cpu.icache.overall_hits::total            3485                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          362                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           362                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          362                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            362                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          362                       # number of overall misses
system.cpu.icache.overall_misses::total           362                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     19725741                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     19725741                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     19725741                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     19725741                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     19725741                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     19725741                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         3847                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         3847                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         3847                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         3847                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         3847                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         3847                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.094099                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.094099                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.094099                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.094099                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.094099                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.094099                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54490.997238                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54490.997238                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54490.997238                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54490.997238                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54490.997238                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54490.997238                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         7642                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           18                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                94                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    81.297872                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           18                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           65                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           65                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           65                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           65                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           65                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           65                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          297                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          297                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          297                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          297                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          297                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          297                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16894743                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     16894743                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16894743                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     16894743                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16894743                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     16894743                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.077203                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.077203                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.077203                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.077203                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.077203                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.077203                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56884.656566                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56884.656566                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56884.656566                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 56884.656566                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56884.656566                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 56884.656566                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued          112                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified          112                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          195.136661                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                 42                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              365                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.115068                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   140.591914                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    45.333856                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher     9.210892                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008581                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.002767                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.000562                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.011910                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022           16                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024          349                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0           13                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            3                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.000977                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.021301                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             7446                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            7446                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst           23                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           19                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total             42                       # number of ReadReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           11                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           11                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           23                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           30                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total              53                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           23                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           30                       # number of overall hits
system.cpu.l2cache.overall_hits::total             53                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          274                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           83                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          357                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           30                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           30                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          274                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          113                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           387                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          274                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          113                       # number of overall misses
system.cpu.l2cache.overall_misses::total          387                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     16599750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5077250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     21677000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2079500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      2079500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     16599750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      7156750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     23756500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     16599750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      7156750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     23756500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          297                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          102                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          399                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           41                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           41                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          297                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          143                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          440                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          297                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          143                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          440                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.922559                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.813725                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.894737                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.731707                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.731707                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.922559                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.790210                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.879545                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.922559                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.790210                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.879545                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60583.029197                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61171.686747                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 60719.887955                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69316.666667                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69316.666667                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60583.029197                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63334.070796                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 61386.304910                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60583.029197                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63334.070796                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 61386.304910                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          273                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           78                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          351                       # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher           48                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total           48                       # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           30                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           30                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          273                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          108                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          381                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          273                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          108                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher           48                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          429                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     14211250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4185750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     18397000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher      1810701                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total      1810701                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1833500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1833500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14211250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6019250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     20230500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14211250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6019250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher      1810701                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     22041201                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.919192                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.879699                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.731707                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.731707                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.919192                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.755245                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.865909                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.919192                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.755245                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.975000                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413                       # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500                       # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq            399                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           397                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq           67                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           41                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           41                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          593                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          285                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               878                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18944                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9088                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              28032                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                          67                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples          507                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        5.132150                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.338988                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5                440     86.79%     86.79% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6                 67     13.21%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            507                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         220000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        493249                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          3.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        222745                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
system.membus.trans_dist::ReadReq                 378                       # Transaction distribution
system.membus.trans_dist::ReadResp                376                       # Transaction distribution
system.membus.trans_dist::ReadExReq                30                       # Transaction distribution
system.membus.trans_dist::ReadExResp               30                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          814                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    814                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25984                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   25984                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples               408                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     408    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 408                       # Request fanout histogram
system.membus.reqLayer0.occupancy              506687                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3785965                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             23.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------