blob: 3c2a96518c9029569da8aaecd69573498531bf37 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated
sim_ticks 24975000 # Number of ticks simulated
final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 84511 # Simulator instruction rate (inst/s)
host_op_rate 84494 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 362882134 # Simulator tick rate (ticks/s)
host_mem_usage 254488 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
system.physmem.bytes_read::total 29120 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 20288 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 20288 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 455 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 29120 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 29120 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 28 # Per bank write bursts
system.physmem.perBankRdBursts::1 0 # Per bank write bursts
system.physmem.perBankRdBursts::2 0 # Per bank write bursts
system.physmem.perBankRdBursts::3 0 # Per bank write bursts
system.physmem.perBankRdBursts::4 8 # Per bank write bursts
system.physmem.perBankRdBursts::5 3 # Per bank write bursts
system.physmem.perBankRdBursts::6 12 # Per bank write bursts
system.physmem.perBankRdBursts::7 51 # Per bank write bursts
system.physmem.perBankRdBursts::8 59 # Per bank write bursts
system.physmem.perBankRdBursts::9 75 # Per bank write bursts
system.physmem.perBankRdBursts::10 36 # Per bank write bursts
system.physmem.perBankRdBursts::11 19 # Per bank write bursts
system.physmem.perBankRdBursts::12 52 # Per bank write bursts
system.physmem.perBankRdBursts::13 28 # Per bank write bursts
system.physmem.perBankRdBursts::14 77 # Per bank write bursts
system.physmem.perBankRdBursts::15 7 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 24894000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 455 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 107 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 245.831776 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 162.727359 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 292.380874 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 36 33.64% 33.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 20 18.69% 52.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 15 14.02% 66.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 9 8.41% 74.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 4 3.74% 78.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 8 7.48% 85.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 1 0.93% 86.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 4 3.74% 90.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 2 1.87% 92.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 2 1.87% 94.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768 2 1.87% 96.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832 1 0.93% 97.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024 1 0.93% 98.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216 1 0.93% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240 1 0.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 107 # Bytes accessed per row activation
system.physmem.totQLat 3167500 # Total ticks spent queuing
system.physmem.totMemAccLat 13555000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers
system.physmem.totBankLat 8112500 # Total ticks spent accessing banks
system.physmem.avgQLat 6961.54 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 17829.67 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29791.21 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 9.11 # Data bus utilization in percentage
system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.54 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 348 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 54712.09 # Average gap between requests
system.physmem.pageHitRate 76.48 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 1165965966 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 404 # Transaction distribution
system.membus.trans_dist::ReadResp 404 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 29120 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 4260750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 17.1 # Layer utilization (%)
system.cpu.branchPred.lookups 1156 # Number of BP lookups
system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 879 # Number of BTB lookups
system.cpu.branchPred.BTBHits 339 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 38.566553 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 49951 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 724 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5088 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 8484 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 1328 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2229 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 274 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 594 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 321 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 64.918033 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 3133 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5383 # Number of cycles cpu stages are processed.
system.cpu.activity 10.776561 # Percentage of cycles cpu is active
system.cpu.comLoads 1163 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 915 # Number of Branches instructions committed
system.cpu.comNops 657 # Number of Nop instructions committed
system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed
system.cpu.comInts 2144 # Number of Integer instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
system.cpu.committedInsts 5814 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads
system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 47185 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 5.537427 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 47060 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2891 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 5.787672 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 13 # number of replacements
system.cpu.icache.tags.tagsinuse 150.636983 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 150.636983 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.073553 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.073553 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits
system.cpu.icache.overall_hits::total 428 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
system.cpu.icache.overall_misses::total 350 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 25425500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 25425500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 25425500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 25425500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 25425500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 778 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 778 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.449871 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.449871 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72644.285714 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 72644.285714 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 72644.285714 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 72644.285714 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 31 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 31 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 31 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23091000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 23091000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23091000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 23091000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23091000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 23091000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72385.579937 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72385.579937 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 538500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 225750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 208.420638 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.318425 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.102213 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004648 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001712 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006360 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 317 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 404 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 317 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 455 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 455 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22745500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6874750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 29620250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3847000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3847000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 22745500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10721750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 33467250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 22745500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10721750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 33467250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 319 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 319 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.995074 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.995624 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71752.365931 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79020.114943 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73317.450495 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75431.372549 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75431.372549 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73554.395604 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73554.395604 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 317 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 404 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 317 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 455 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18763000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5795250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24558250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18763000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8999750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 27762750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18763000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8999750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 27762750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59189.274448 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66612.068966 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60787.747525 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 90.339752 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 90.339752 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.022056 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.022056 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1638 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1638 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1638 # number of overall hits
system.cpu.dcache.overall_hits::total 1638 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 450 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses
system.cpu.dcache.overall_misses::total 450 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7659250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7659250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21762250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21762250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 29421500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 29421500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 29421500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 29421500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083405 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.083405 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78961.340206 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 78961.340206 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61649.433428 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61649.433428 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 65381.111111 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 65381.111111 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 312 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 312 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6968250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6968250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3901000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3901000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10869250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10869250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10869250 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10869250 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80094.827586 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80094.827586 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76490.196078 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76490.196078 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|