path: root/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000024                       # Number of seconds simulated
sim_ticks                                    24417000                       # Number of ticks simulated
final_tick                                   24417000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  26948                       # Simulator instruction rate (inst/s)
host_op_rate                                    26945                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              116974890                       # Simulator tick rate (ticks/s)
host_mem_usage                                 277212                       # Number of bytes of host memory used
host_seconds                                     0.21                       # Real time elapsed on the host
sim_insts                                        5624                       # Number of instructions simulated
sim_ops                                          5624                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             20032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              8768                       # Number of bytes read from this memory
system.physmem.bytes_read::total                28800                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        20032                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           20032                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                137                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   450                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            820412008                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            359094074                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1179506082                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       820412008                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          820412008                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           820412008                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           359094074                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1179506082                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           450                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         450                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    28800                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     28800                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  27                       # Per bank write bursts
system.physmem.perBankRdBursts::1                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::2                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::3                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::4                   8                       # Per bank write bursts
system.physmem.perBankRdBursts::5                   3                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  12                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  50                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  56                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  75                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 36                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 19                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 52                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 28                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 77                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  7                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        24336000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     450                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       299                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        23                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          103                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      276.504854                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     191.986288                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     256.190297                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             25     24.27%     24.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           37     35.92%     60.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           14     13.59%     73.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            8      7.77%     81.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            8      7.77%     89.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            2      1.94%     91.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      2.91%     94.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            1      0.97%     95.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            5      4.85%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            103                       # Bytes accessed per row activation
system.physmem.totQLat                        4914500                       # Total ticks spent queuing
system.physmem.totMemAccLat                  13352000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2250000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10921.11                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29671.11                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        1179.51                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     1179.51                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           9.21                       # Data bus utilization in percentage
system.physmem.busUtilRead                       9.21                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.52                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        344                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.44                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        54080.00                       # Average gap between requests
system.physmem.pageHitRate                      76.44                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
system.physmem.memoryStateTime::REF            780000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT          22851000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                    181440                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                    582120                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                     99000                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                    317625                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                   772200                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                  2652000                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0               1525680                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1               1525680                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0              14753880                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1              16048350                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0               1235250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1                 99750                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0                18567450                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1                21225525                       # Total energy per rank (pJ)
system.physmem.averagePower::0             785.799080                       # Core power per rank (mW)
system.physmem.averagePower::1             898.292335                       # Core power per rank (mW)
system.membus.trans_dist::ReadReq                 400                       # Transaction distribution
system.membus.trans_dist::ReadResp                400                       # Transaction distribution
system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28800                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   28800                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples               450                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     450    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 450                       # Request fanout histogram
system.membus.reqLayer0.occupancy              545500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy            4210750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             17.2                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                    1124                       # Number of BP lookups
system.cpu.branchPred.condPredicted               833                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               586                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                  850                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     329                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             38.705882                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                      84                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 31                       # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                    7                       # Number of system calls
system.cpu.numCycles                            48835                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken          421                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken          703                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads         4929                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites         3280                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses         8209                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads            3                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites            1                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses            4                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards           1292                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                       2173                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect          263                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect          315                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted            578                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted               305                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     65.458664                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions             3019                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies                 2                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.threadCycles                          9295                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                             454                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           43587                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                             5248                       # Number of cycles cpu stages are processed.
system.cpu.activity                         10.746391                       # Percentage of cycles cpu is active
system.cpu.comLoads                              1132                       # Number of Load instructions committed
system.cpu.comStores                              901                       # Number of Store instructions committed
system.cpu.comBranches                            883                       # Number of Branches instructions committed
system.cpu.comNops                                637                       # Number of Nop instructions committed
system.cpu.comNonSpec                               9                       # Number of Non-Speculative instructions committed
system.cpu.comInts                               2062                       # Number of Integer instructions committed
system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
system.cpu.committedInsts                        5624                       # Number of Instructions committed (Per-Thread)
system.cpu.committedOps                          5624                       # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total                  5624                       # Number of Instructions committed (Total)
system.cpu.cpi                               8.683321                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
system.cpu.cpi_total                         8.683321                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.115163                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         0.115163                       # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles                    45291                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                      3544                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization                7.257090                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles                    46099                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                      2736                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization                5.602539                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles                    46145                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                      2690                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization                5.508344                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles                    47641                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                      1194                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization                2.444968                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                    46041                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                      2794                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization                5.721306                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements                13                       # number of replacements
system.cpu.icache.tags.tagsinuse           147.900639                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                 418                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               315                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              1.326984                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   147.900639                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.072217                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.072217                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          302                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.147461                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              1839                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             1839                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst          418                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total             418                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst           418                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total              418                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst          418                       # number of overall hits
system.cpu.icache.overall_hits::total             418                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          344                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           344                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          344                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            344                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          344                       # number of overall misses
system.cpu.icache.overall_misses::total           344                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     25151000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     25151000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     25151000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     25151000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     25151000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     25151000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst          762                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total          762                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst          762                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total          762                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst          762                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total          762                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.451444                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.451444                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.451444                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.451444                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.451444                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.451444                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73113.372093                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 73113.372093                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 73113.372093                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 73113.372093                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 73113.372093                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 73113.372093                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           29                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           29                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           29                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           29                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           29                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           29                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          315                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          315                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          315                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          315                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          315                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          315                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22975000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     22975000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22975000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     22975000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22975000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     22975000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.413386                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.413386                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.413386                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.413386                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.413386                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.413386                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72936.507937                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72936.507937                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72936.507937                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 72936.507937                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72936.507937                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 72936.507937                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq            402                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           402                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          630                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          274                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               904                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20160                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8768                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              28928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples          452                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                452    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            452                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         226000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        532000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        224750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          204.797884                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              400                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.005000                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   149.365797                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    55.432088                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004558                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.001692                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.006250                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012207                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             4066                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            4066                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          313                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          400                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           50                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          313                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          137                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           450                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          313                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          137                       # number of overall misses
system.cpu.l2cache.overall_misses::total          450                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22634000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6609750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     29243750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3723500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      3723500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     22634000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     10333250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     32967250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     22634000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     10333250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     32967250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          315                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          402                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           50                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          315                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          137                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          452                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          315                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          137                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          452                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993651                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.995025                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993651                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.995575                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993651                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.995575                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72313.099042                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75974.137931                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73109.375000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        74470                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        74470                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72313.099042                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75425.182482                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73260.555556                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72313.099042                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75425.182482                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73260.555556                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          313                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          400                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          313                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          450                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          313                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          450                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18704000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5530750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24234750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3093000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3093000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18704000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8623750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     27327750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18704000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8623750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     27327750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995025                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.995575                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.995575                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59757.188498                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63571.839080                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60586.875000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        61860                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        61860                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59757.188498                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62947.080292                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60728.333333                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59757.188498                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62947.080292                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60728.333333                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            89.129655                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1596                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               137                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.649635                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    89.129655                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.021760                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.021760                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          137                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          107                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.033447                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4203                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4203                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         1035                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1035                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          561                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            561                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          1596                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1596                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1596                       # number of overall hits
system.cpu.dcache.overall_hits::total            1596                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           97                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            97                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          340                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          340                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          437                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            437                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          437                       # number of overall misses
system.cpu.dcache.overall_misses::total           437                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      7368000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      7368000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     20584000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     20584000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     27952000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     27952000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     27952000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     27952000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1132                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1132                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2033                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2033                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2033                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2033                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085689                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.085689                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.377358                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.377358                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.214953                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.214953                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.214953                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.214953                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60541.176471                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60541.176471                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63963.386728                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 63963.386728                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63963.386728                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 63963.386728                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          265                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.384615                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           10                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          290                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          290                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          300                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          300                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          300                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          300                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          137                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          137                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6703250                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      6703250                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3776500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      3776500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10479750                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     10479750                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10479750                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     10479750                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076855                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076855                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.067388                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.067388                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        75530                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        75530                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.525547                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.525547                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.525547                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.525547                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------