blob: 66a92381f64099bcfe0214e0f805d24a4f923195 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000019 # Number of seconds simulated
sim_ticks 18905500 # Number of ticks simulated
final_tick 18905500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 44009 # Simulator instruction rate (inst/s)
host_op_rate 44004 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 143620144 # Simulator tick rate (ticks/s)
host_mem_usage 227496 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1167914099 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 341911084 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1509825183 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1167914099 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1167914099 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1167914099 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 341911084 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1509825183 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 446 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 70 # Per bank write bursts
system.physmem.perBankRdBursts::1 42 # Per bank write bursts
system.physmem.perBankRdBursts::2 54 # Per bank write bursts
system.physmem.perBankRdBursts::3 59 # Per bank write bursts
system.physmem.perBankRdBursts::4 53 # Per bank write bursts
system.physmem.perBankRdBursts::5 61 # Per bank write bursts
system.physmem.perBankRdBursts::6 52 # Per bank write bursts
system.physmem.perBankRdBursts::7 13 # Per bank write bursts
system.physmem.perBankRdBursts::8 8 # Per bank write bursts
system.physmem.perBankRdBursts::9 28 # Per bank write bursts
system.physmem.perBankRdBursts::10 2 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdBursts::12 0 # Per bank write bursts
system.physmem.perBankRdBursts::13 0 # Per bank write bursts
system.physmem.perBankRdBursts::14 4 # Per bank write bursts
system.physmem.perBankRdBursts::15 0 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 18777000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 446 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 329.846154 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 165.491272 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 472.454851 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 36 46.15% 46.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 8 10.26% 56.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 8 10.26% 66.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 4 5.13% 71.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 2 2.56% 74.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 3 3.85% 78.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 1 1.28% 79.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 2 2.56% 82.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 2 2.56% 84.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 2 2.56% 87.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896 1 1.28% 88.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960 1 1.28% 89.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024 2 2.56% 92.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088 1 1.28% 93.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280 1 1.28% 94.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600 1 1.28% 96.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920 1 1.28% 97.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112 2 2.56% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation
system.physmem.totQLat 3018500 # Total ticks spent queuing
system.physmem.totMemAccLat 11958500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers
system.physmem.totBankLat 6710000 # Total ticks spent accessing banks
system.physmem.avgQLat 6767.94 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 15044.84 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26812.78 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1509.83 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1509.83 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 11.80 # Data bus utilization in percentage
system.physmem.busUtilRead 11.80 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 368 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 42100.90 # Average gap between requests
system.physmem.pageHitRate 82.51 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 1509825183 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 399 # Transaction distribution
system.membus.trans_dist::ReadResp 399 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 28544 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 566000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 22.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 2238 # Number of BP lookups
system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1851 # Number of BTB lookups
system.cpu.branchPred.BTBHits 603 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 32.576985 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.numCycles 37812 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 7436 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2263 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked
system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 11776 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.117612 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.534017 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9513 80.78% 80.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 178 1.51% 82.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 176 1.49% 83.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 142 1.21% 84.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 227 1.93% 86.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 133 1.13% 88.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 257 2.18% 90.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 110 0.93% 91.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1040 8.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 11776 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.059188 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.348064 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 7513 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2098 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1987 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11308 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 226 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 9701 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 18192 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 18166 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 4703 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 575 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8904 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4244 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3486 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 11776 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.756114 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.487258 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 8416 71.47% 71.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 789 6.70% 87.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 501 4.25% 91.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 456 3.87% 95.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 11776 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.62% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 73 42.20% 46.82% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5478 61.52% 61.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1628 18.28% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8904 # Type of FU issued
system.cpu.iq.rate 0.235481 # Inst issue rate
system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.019429 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 29936 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 14577 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8131 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9043 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 457 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10362 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8503 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3202 # number of memory reference insts executed
system.cpu.iew.exec_branches 1351 # Number of branches executed
system.cpu.iew.exec_stores 1524 # Number of stores executed
system.cpu.iew.exec_rate 0.224876 # Inst execution rate
system.cpu.iew.wb_sent 8273 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8158 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4220 # num instructions producing a value
system.cpu.iew.wb_consumers 6682 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.215752 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.631547 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11067 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.523358 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.324283 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 8688 78.50% 78.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1007 9.10% 87.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 608 5.49% 93.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 271 2.45% 95.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 170 1.54% 97.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 108 0.98% 98.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11067 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2007 # Number of memory references committed
system.cpu.commit.loads 961 # Number of loads committed
system.cpu.commit.membars 7 # Number of memory barriers committed
system.cpu.commit.branches 1037 # Number of branches committed
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
system.cpu.commit.function_calls 103 # Number of function calls committed.
system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 21334 # The number of ROB reads
system.cpu.rob.rob_writes 21446 # The number of ROB writes
system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 26036 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
system.cpu.cpi 6.528315 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.528315 # CPI: Total CPI of All Threads
system.cpu.ipc 0.153179 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.153179 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 13476 # number of integer regfile reads
system.cpu.int_regfile_writes 7049 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.toL2Bus.throughput 1533521991 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 587000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 169.362417 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 169.362417 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.082696 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.082696 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 3979 # Number of tag accesses
system.cpu.icache.tags.data_accesses 3979 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1372 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1372 # number of overall hits
system.cpu.icache.overall_hits::total 1372 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses
system.cpu.icache.overall_misses::total 442 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30183750 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 30183750 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 30183750 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 30183750 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 30183750 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1814 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1814 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1814 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243660 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.243660 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.243660 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68289.027149 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 68289.027149 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 68289.027149 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 68289.027149 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 72.166667 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24475000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 24475000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24475000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 24475000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24475000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 24475000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.344729 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.344729 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 199.747174 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.225208 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521966 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006096 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4070 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4070 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 7 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 345 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24063500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 28138000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3590250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3590250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 24063500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7664750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 31728250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 24063500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7664750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 31728250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982906 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.982759 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69749.275362 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70521.303258 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76388.297872 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76388.297872 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71139.573991 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71139.573991 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23130500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3013250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3013250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6423750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26143750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6423750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26143750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57159.420290 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57971.177945 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64111.702128 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64111.702128 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 63.784946 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 63.784946 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.015572 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.015572 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5348 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5348 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits
system.cpu.dcache.overall_hits::total 2188 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses
system.cpu.dcache.overall_misses::total 435 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7365250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7365250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19851746 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 19851746 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 27216996 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 27216996 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 27216996 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 27216996 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70819.711538 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 70819.711538 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59975.063444 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59975.063444 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62567.806897 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62567.806897 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3640248 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3640248 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7780248 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7780248 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7780248 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7780248 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77452.085106 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77452.085106 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|