blob: 1ce5039d0b656bd3db2eba2033dc9910f1351e8a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18201500 # Number of ticks simulated
final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 29731 # Simulator instruction rate (inst/s)
host_tick_rate 101330259 # Simulator tick rate (ticks/s)
host_mem_usage 213072 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
system.physmem.bytes_read 27072 # Number of bytes read from this memory
system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 423 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 1487349944 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1016179985 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1487349944 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 36404 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9720 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30130 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 6274 # Number of cycles cpu stages are processed.
system.cpu.activity 17.234370 # Percentage of cycles cpu is active
system.cpu.comLoads 716 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1116 # Number of Branches instructions committed
system.cpu.comNops 173 # Number of Nop instructions committed
system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
system.cpu.comInts 2537 # Number of Integer instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
system.cpu.committedInsts 5340 # Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 5340 # Number of Instructions Simulated (Total)
system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads
system.cpu.ipc 0.146687 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.146687 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 1662 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1123 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1455 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 643 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 44.192440 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 710 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 952 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9612 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 1747 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 1473 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 394 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 442 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 3977 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 31738 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4666 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 12.817273 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 33193 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3211 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 8.820459 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33357 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3047 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 8.369959 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 35421 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.700253 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 33233 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3171 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 8.710581 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 136.669321 # Cycle average of tags in use
system.cpu.icache.total_refs 791 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 136.669321 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.066733 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 791 # number of ReadReq hits
system.cpu.icache.demand_hits 791 # number of demand (read+write) hits
system.cpu.icache.overall_hits 791 # number of overall hits
system.cpu.icache.ReadReq_misses 347 # number of ReadReq misses
system.cpu.icache.demand_misses 347 # number of demand (read+write) misses
system.cpu.icache.overall_misses 347 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 19110500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 19110500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 19110500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 1138 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 1138 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 1138 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.304921 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.304921 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.304921 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 55073.487032 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 55073.487032 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 55073.487032 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 291 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 291 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 291 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 15470000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 15470000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 15470000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.255712 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.255712 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.255712 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53161.512027 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use
system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 82.859932 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.020229 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 657 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 392 # number of WriteReq hits
system.cpu.dcache.demand_hits 1049 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 1049 # number of overall hits
system.cpu.dcache.ReadReq_misses 59 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 281 # number of WriteReq misses
system.cpu.dcache.demand_misses 340 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 340 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 3290500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 15457500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 18748000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 18748000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.082402 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.417533 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.244780 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.244780 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 55771.186441 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 55008.896797 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 55141.176471 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 55141.176471 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 200 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 205 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 205 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2865500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 4327000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 7192500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 7192500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53064.814815 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53419.753086 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 162.297266 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.004953 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 3 # number of overall hits
system.cpu.l2cache.ReadReq_misses 342 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 423 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 17918500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 4230500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 22149000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 22149000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 345 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 426 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 426 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.991304 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.992958 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.992958 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52393.274854 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52228.395062 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52361.702128 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52361.702128 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 342 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 13747000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3255500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 17002500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 17002500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.991304 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.992958 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.992958 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40195.906433 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40191.358025 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
