path: root/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000021                       # Number of seconds simulated
sim_ticks                                    20970500                       # Number of ticks simulated
final_tick                                   20970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  71497                       # Simulator instruction rate (inst/s)
host_op_rate                                    71482                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              281347268                       # Simulator tick rate (ticks/s)
host_mem_usage                                 269780                       # Number of bytes of host memory used
host_seconds                                     0.07                       # Real time elapsed on the host
sim_insts                                        5327                       # Number of instructions simulated
sim_ops                                          5327                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             18496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
system.physmem.bytes_read::total                27072                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        18496                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           18496                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                289                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   423                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            882000906                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            408955437                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1290956343                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       882000906                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          882000906                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           882000906                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           408955437                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1290956343                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           423                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         423                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    27072                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     27072                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  24                       # Per bank write bursts
system.physmem.perBankRdBursts::1                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::2                   1                       # Per bank write bursts
system.physmem.perBankRdBursts::3                   8                       # Per bank write bursts
system.physmem.perBankRdBursts::4                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  78                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  80                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  62                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  35                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  18                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 10                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 52                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 12                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 21                       # Per bank write bursts
system.physmem.perBankRdBursts::14                  7                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  8                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        20901000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     423                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       251                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       129                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           48                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      337.333333                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     221.579222                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     300.401245                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             13     27.08%     27.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255            9     18.75%     45.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383            6     12.50%     58.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            7     14.58%     72.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            6     12.50%     85.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            2      4.17%     89.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            5     10.42%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             48                       # Bytes accessed per row activation
system.physmem.totQLat                        3113750                       # Total ticks spent queuing
system.physmem.totMemAccLat                  11732500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2115000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                     6503750                       # Total ticks spent accessing banks
system.physmem.avgQLat                        7361.11                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    15375.30                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27736.41                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        1290.96                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     1290.96                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                          10.09                       # Data bus utilization in percentage
system.physmem.busUtilRead                      10.09                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.66                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        339                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.14                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        49411.35                       # Average gap between requests
system.physmem.pageHitRate                      80.14                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                   1290956343                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 342                       # Transaction distribution
system.membus.trans_dist::ReadResp                342                       # Transaction distribution
system.membus.trans_dist::ReadExReq                81                       # Transaction distribution
system.membus.trans_dist::ReadExResp               81                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          846                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    846                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        27072                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               27072                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  27072                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              501500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3929500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             18.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                    1636                       # Number of BP lookups
system.cpu.branchPred.condPredicted              1090                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               897                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 1343                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     584                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             43.484736                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                      67                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls                   11                       # Number of system calls
system.cpu.numCycles                            41942                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken          651                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken          985                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads         5611                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites         3988                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses         9599                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads            0                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites            0                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses            0                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards           1718                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                       1472                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect          376                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect          458                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted            834                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted               281                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     74.798206                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions             3957                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.threadCycles                          9659                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                             424                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           35694                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                             6248                       # Number of cycles cpu stages are processed.
system.cpu.activity                         14.896762                       # Percentage of cycles cpu is active
system.cpu.comLoads                               715                       # Number of Load instructions committed
system.cpu.comStores                              673                       # Number of Store instructions committed
system.cpu.comBranches                           1115                       # Number of Branches instructions committed
system.cpu.comNops                                173                       # Number of Nop instructions committed
system.cpu.comNonSpec                             106                       # Number of Non-Speculative instructions committed
system.cpu.comInts                               2526                       # Number of Integer instructions committed
system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
system.cpu.committedInsts                        5327                       # Number of Instructions committed (Per-Thread)
system.cpu.committedOps                          5327                       # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total                  5327                       # Number of Instructions committed (Total)
system.cpu.cpi                               7.873475                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
system.cpu.cpi_total                         7.873475                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.127009                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         0.127009                       # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles                    37302                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                      4640                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization               11.062896                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles                    38748                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                      3194                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization                7.615278                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles                    38908                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                      3034                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization                7.233799                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles                    40966                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                       976                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization                2.327023                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                    38785                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                      3157                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization                7.527061                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           142.644710                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                 892                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               291                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              3.065292                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   142.644710                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.069651                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.069651                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          291                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          147                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.142090                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              2807                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             2807                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst          892                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total             892                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst           892                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total              892                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst          892                       # number of overall hits
system.cpu.icache.overall_hits::total             892                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          366                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           366                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          366                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            366                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          366                       # number of overall misses
system.cpu.icache.overall_misses::total           366                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     25482750                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     25482750                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     25482750                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     25482750                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     25482750                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     25482750                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         1258                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         1258                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         1258                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         1258                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         1258                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         1258                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.290938                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.290938                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.290938                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.290938                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.290938                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.290938                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        69625                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total        69625                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst        69625                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total        69625                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst        69625                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total        69625                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           75                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           75                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           75                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           75                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           75                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           75                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          291                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          291                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          291                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          291                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          291                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          291                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20711750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     20711750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20711750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     20711750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20711750                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     20711750                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.231320                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.231320                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.231320                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.231320                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.231320                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.231320                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71174.398625                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71174.398625                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71174.398625                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71174.398625                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71174.398625                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71174.398625                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput              1300112062                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq            345                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           345                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           81                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           81                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          582                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          270                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               852                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18624                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8640                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total          27264                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus             27264                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy         213000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        485750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          2.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        216250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          169.087834                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              342                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.008772                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   142.075458                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    27.012376                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004336                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.000824                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.005160                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          342                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010437                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             3831                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            3831                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          289                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          342                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           81                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           81                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          289                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           423                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          289                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
system.cpu.l2cache.overall_misses::total          423                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20393250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4031000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     24424250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6031750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      6031750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     20393250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     10062750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     30456000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     20393250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     10062750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     30456000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          291                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           54                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          345                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           81                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           81                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          291                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          135                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          426                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          291                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          135                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          426                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993127                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.981481                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.991304                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993127                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.992593                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.992958                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993127                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.992958                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70564.878893                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76056.603774                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71415.935673                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74466.049383                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74466.049383                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70564.878893                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75095.149254                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        72000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70564.878893                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75095.149254                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        72000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          289                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          342                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           81                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           81                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          289                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          134                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          423                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          289                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          423                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16781250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3376000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20157250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5037250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5037250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16781250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8413250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     25194500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16781250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8413250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     25194500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.991304                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.992958                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.992958                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58066.608997                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63698.113208                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58939.327485                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62188.271605                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62188.271605                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58066.608997                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62785.447761                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59561.465721                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58066.608997                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62785.447761                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59561.465721                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            85.369033                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                 914                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               135                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              6.770370                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    85.369033                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.020842                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.020842                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.032959                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              2911                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             2911                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data          654                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total             654                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          260                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            260                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data           914                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total              914                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data          914                       # number of overall hits
system.cpu.dcache.overall_hits::total             914                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          413                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          413                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          474                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            474                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          474                       # number of overall misses
system.cpu.dcache.overall_misses::total           474                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      4594750                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      4594750                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     29091500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     29091500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     33686250                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     33686250                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     33686250                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     33686250                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data          715                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total          715                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          673                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         1388                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         1388                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         1388                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         1388                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085315                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.085315                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.613670                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.613670                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.341499                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.341499                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.341499                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.341499                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75323.770492                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 75323.770492                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70439.467312                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 70439.467312                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71068.037975                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 71068.037975                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71068.037975                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 71068.037975                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          818                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                31                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    26.387097                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data            7                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total            7                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          332                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          332                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          339                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          339                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          339                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          339                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           54                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           81                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           81                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          135                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4097500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      4097500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6115250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      6115250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10212750                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     10212750                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10212750                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     10212750                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075524                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075524                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.120357                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097262                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.097262                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097262                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.097262                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75879.629630                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75879.629630                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75496.913580                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75496.913580                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        75650                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total        75650                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        75650                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total        75650                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------