path: root/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000015                       # Number of seconds simulated
sim_ticks                                    15249000                       # Number of ticks simulated
final_tick                                   15249000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  41998                       # Simulator instruction rate (inst/s)
host_op_rate                                    76065                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              119014725                       # Simulator tick rate (ticks/s)
host_mem_usage                                 225728                       # Number of bytes of host memory used
host_seconds                                     0.13                       # Real time elapsed on the host
sim_insts                                        5380                       # Number of instructions simulated
sim_ops                                          9745                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             19520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              9280                       # Number of bytes read from this memory
system.physmem.bytes_read::total                28800                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        19520                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           19520                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                305                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                145                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   450                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst           1280083940                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            608564496                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1888648436                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      1280083940                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         1280083940                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          1280083940                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           608564496                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1888648436                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           451                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                            451                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                        28800                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                  28800                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                    40                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                    20                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                    55                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                    23                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                    52                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                    23                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                    16                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                    14                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                    22                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                    35                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                   31                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                   40                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                   12                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                   17                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                   34                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                   17                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                        15226500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                     451                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                      0                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                       230                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       155                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        56                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                        1663951                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                  11993951                       # Sum of mem lat for all requests
system.physmem.totBusLat                      1804000                       # Total cycles spent in databus access
system.physmem.totBankLat                     8526000                       # Total cycles spent in bank access
system.physmem.avgQLat                        3689.47                       # Average queueing delay per request
system.physmem.avgBankLat                    18904.66                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  26594.13                       # Average memory access latency
system.physmem.avgRdBW                        1888.65                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                1888.65                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                          11.80                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.79                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                        354                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   78.49                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        33761.64                       # Average gap between requests
system.cpu.workload.num_syscalls                   11                       # Number of system calls
system.cpu.numCycles                            30499                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                     3124                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted               3124                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect                575                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups                  2554                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                      779                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles               9097                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          15002                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        3124                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches                779                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          4073                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    2573                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles                   3671                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   39                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           217                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           15                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                      1972                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   311                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              19065                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.398846                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.899430                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    15096     79.18%     79.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      179      0.94%     80.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      149      0.78%     80.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      207      1.09%     81.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      179      0.94%     82.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      177      0.93%     83.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      231      1.21%     85.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      192      1.01%     86.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     2655     13.93%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                19065                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.102430                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.491885                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                     9663                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  3644                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      3665                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   140                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                   1953                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts                  25430                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                   1953                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                    10013                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    2382                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles            508                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      3439                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                   770                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  23869                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                     27                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents                   648                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands               26126                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 57405                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            57389                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                 11060                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                    15066                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 31                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             31                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                      2094                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 2405                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1772                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                13                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      21302                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  37                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                     17998                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued               209                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined           10762                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined        14777                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             24                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         19065                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.944034                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.806602                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               13533     70.98%     70.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1394      7.31%     78.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                1058      5.55%     83.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 719      3.77%     87.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 757      3.97%     91.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 676      3.55%     95.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 613      3.22%     98.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                 275      1.44%     99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  40      0.21%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           19065                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     132     74.58%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     74.58% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                     23     12.99%     87.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    22     12.43%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                 14399     80.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.03% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 2084     11.58%     91.60% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1511      8.40%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  17998                       # Type of FU issued
system.cpu.iq.rate                           0.590118                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                         177                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.009834                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              55439                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             32107                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses        16514                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                  18167                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads              180                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1353                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses           24                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           11                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          838                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            15                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                   1953                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                    1731                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                    30                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               21339                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                34                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  2405                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1772                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 33                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             11                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect             65                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          652                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  717                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                 17023                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  1944                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               975                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                         3334                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1674                       # Number of branches executed
system.cpu.iew.exec_stores                       1390                       # Number of stores executed
system.cpu.iew.exec_rate                     0.558149                       # Inst execution rate
system.cpu.iew.wb_sent                          16747                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                         16518                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                     10593                       # num instructions producing a value
system.cpu.iew.wb_consumers                     16382                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.541592                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.646624                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts           11593                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               604                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        17112                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.569483                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.430880                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        13541     79.13%     79.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         1338      7.82%     86.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          619      3.62%     90.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          703      4.11%     94.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          373      2.18%     96.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          140      0.82%     97.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          121      0.71%     98.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           74      0.43%     98.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          203      1.19%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        17112                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
system.cpu.commit.committedOps                   9745                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           1986                       # Number of memory references committed
system.cpu.commit.loads                          1052                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                       1208                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      9650                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events                   203                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                        38247                       # The number of ROB reads
system.cpu.rob.rob_writes                       44659                       # The number of ROB writes
system.cpu.timesIdled                             152                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           11434                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
system.cpu.committedOps                          9745                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total                  5380                       # Number of Instructions Simulated
system.cpu.cpi                               5.668959                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         5.668959                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.176399                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.176399                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    29908                       # number of integer regfile reads
system.cpu.int_regfile_writes                   17845                       # number of integer regfile writes
system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
system.cpu.misc_regfile_reads                    7467                       # number of misc regfile reads
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.tagsinuse                145.993781                       # Cycle average of tags in use
system.cpu.icache.total_refs                     1566                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    306                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   5.117647                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     145.993781                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.071286                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.071286                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst         1566                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1566                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          1566                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1566                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         1566                       # number of overall hits
system.cpu.icache.overall_hits::total            1566                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          406                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           406                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          406                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            406                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          406                       # number of overall misses
system.cpu.icache.overall_misses::total           406                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     19356000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     19356000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     19356000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     19356000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     19356000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     19356000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         1972                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         1972                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         1972                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         1972                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         1972                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         1972                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.205882                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.205882                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.205882                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.205882                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.205882                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.205882                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47674.876847                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 47674.876847                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 47674.876847                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 47674.876847                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47674.876847                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 47674.876847                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          302                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    43.142857                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          100                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          100                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          100                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          100                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          100                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          100                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          306                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          306                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          306                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          306                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          306                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          306                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15469000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     15469000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15469000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     15469000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15469000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     15469000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.155172                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.155172                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.155172                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.155172                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.155172                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.155172                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50552.287582                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50552.287582                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50552.287582                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50552.287582                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50552.287582                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50552.287582                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.tagsinuse                 83.489938                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     2406                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                    143                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  16.825175                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data      83.489938                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.020383                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.020383                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data         1548                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1548                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          2406                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             2406                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         2406                       # number of overall hits
system.cpu.dcache.overall_hits::total            2406                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          132                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           132                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           76                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          208                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            208                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          208                       # number of overall misses
system.cpu.dcache.overall_misses::total           208                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      6548500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      6548500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      4231000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      4231000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     10779500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     10779500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     10779500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     10779500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1680                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1680                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          934                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2614                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2614                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2614                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2614                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.078571                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.078571                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081370                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.081370                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.079572                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.079572                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.079572                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.079572                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49609.848485                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 49609.848485                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55671.052632                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55671.052632                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 51824.519231                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 51824.519231                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 51824.519231                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 51824.519231                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          108                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.600000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           62                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data           62                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total           62                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data           62                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total           62                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           70                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           76                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           76                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3696500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      3696500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4079000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      4079000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7775500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      7775500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7775500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      7775500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.041667                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.041667                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081370                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081370                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055853                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.055853                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.055853                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.055853                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52807.142857                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52807.142857                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53671.052632                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53671.052632                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53256.849315                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53256.849315                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53256.849315                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53256.849315                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse               179.176449                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                   374                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.002674                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst    146.139957                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data     33.036492                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst     0.004460                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.001008                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.005468                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          305                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           70                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          375                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           76                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           76                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          305                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          146                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           451                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          305                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          146                       # number of overall misses
system.cpu.l2cache.overall_misses::total          451                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15152000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3773500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     18925500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4003000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      4003000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     15152000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      7776500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     22928500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     15152000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      7776500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     22928500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          306                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           70                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          376                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           76                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           76                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          306                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          146                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          452                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          306                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          146                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          452                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996732                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.997340                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996732                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.997788                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996732                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.997788                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49678.688525                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53907.142857                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        50468                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52671.052632                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52671.052632                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49678.688525                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.698630                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 50839.246120                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49678.688525                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.698630                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 50839.246120                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          305                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           70                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          375                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           76                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           76                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          305                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          451                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          305                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          451                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11317954                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2918074                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14236028                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3040610                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3040610                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11317954                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5958684                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     17276638                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11317954                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5958684                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     17276638                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996732                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997340                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996732                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.997788                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996732                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.997788                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37108.045902                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41686.771429                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37962.741333                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.026316                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40008.026316                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37108.045902                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40812.904110                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38307.401330                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37108.045902                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40812.904110                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38307.401330                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------