path: root/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000020                       # Number of seconds simulated
sim_ticks                                    19678000                       # Number of ticks simulated
final_tick                                   19678000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  46918                       # Simulator instruction rate (inst/s)
host_op_rate                                    84992                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              171550123                       # Simulator tick rate (ticks/s)
host_mem_usage                                 309548                       # Number of bytes of host memory used
host_seconds                                     0.11                       # Real time elapsed on the host
sim_insts                                        5380                       # Number of instructions simulated
sim_ops                                          9747                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             17600                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
system.physmem.bytes_read::total                26624                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        17600                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           17600                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            894399837                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            458583189                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1352983027                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       894399837                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          894399837                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           894399837                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           458583189                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1352983027                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           417                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         417                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    26688                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     26688                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  34                       # Per bank write bursts
system.physmem.perBankRdBursts::1                   1                       # Per bank write bursts
system.physmem.perBankRdBursts::2                   6                       # Per bank write bursts
system.physmem.perBankRdBursts::3                   8                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  50                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  45                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  21                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  34                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  22                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  74                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 63                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 17                       # Per bank write bursts
system.physmem.perBankRdBursts::12                  2                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 17                       # Per bank write bursts
system.physmem.perBankRdBursts::14                  6                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 17                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        19629500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     417                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       241                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           98                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      242.285714                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     158.475642                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     257.521253                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             36     36.73%     36.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           30     30.61%     67.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           13     13.27%     80.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            6      6.12%     86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            6      6.12%     92.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            4      4.08%     96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            3      3.06%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             98                       # Bytes accessed per row activation
system.physmem.totQLat                        4347000                       # Total ticks spent queuing
system.physmem.totMemAccLat                  12165750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2085000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10424.46                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29174.46                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        1356.24                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     1356.24                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                          10.60                       # Data bus utilization in percentage
system.physmem.busUtilRead                      10.60                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.66                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        309                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.10                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        47073.14                       # Average gap between requests
system.physmem.pageHitRate                      74.10                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     219240                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     119625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   1084200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               10796085                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                  31500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 13267770                       # Total energy per rank (pJ)
system.physmem_0.averagePower              837.810088                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE          11000                       # Time in different power states
system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        15318250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     446040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     243375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   1567800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               10701180                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 112500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 14088015                       # Total energy per rank (pJ)
system.physmem_1.averagePower              889.816201                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE         882750                       # Time in different power states
system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        15230750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                    3423                       # Number of BP lookups
system.cpu.branchPred.condPredicted              3423                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               535                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 2544                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     864                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             33.962264                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     247                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 76                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                   11                       # Number of system calls
system.cpu.numCycles                            39357                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles              10915                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          15528                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        3423                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches               1111                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          9222                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    1203                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                   54                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1088                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.CacheLines                      2168                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   278                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              21893                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.270406                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.764504                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    17618     80.47%     80.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      236      1.08%     81.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      174      0.79%     82.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      259      1.18%     83.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      208      0.95%     84.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      227      1.04%     85.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      339      1.55%     87.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      205      0.94%     88.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     2627     12.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                21893                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.086973                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.394542                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                    10660                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  6840                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      3336                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   456                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                    601                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts                  25755                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                    601                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                    10929                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    2194                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles            719                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      3480                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                  3970                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  24219                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                     93                       # Number of times rename has blocked due to IQ full
system.cpu.rename.SQFullEvents                   3820                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands               27591                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 59364                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            33558                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                 4                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                 11063                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                    16528                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 29                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             29                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                      1503                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 2441                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1612                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                22                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                6                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      21443                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                     17897                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued                80                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined           11052                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined        16525                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             13                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         21893                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.817476                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.773238                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               16772     76.61%     76.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1137      5.19%     81.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                 886      4.05%     85.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 636      2.91%     88.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 833      3.80%     92.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 590      2.69%     95.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 599      2.74%     97.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                 316      1.44%     99.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                 124      0.57%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           21893                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     174     77.68%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     77.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                     31     13.84%     91.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    19      8.48%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 3      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                 14382     80.36%     80.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    4      0.02%     80.40% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 2122     11.86%     92.29% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1379      7.71%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  17897                       # Type of FU issued
system.cpu.iq.rate                           0.454735                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.012516                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              57983                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             32531                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses        16370                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                  18114                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads              228                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1388                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses           11                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          677                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            18                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                    601                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                    1862                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                    54                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               21468                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                32                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  2441                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1612                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 25                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                    46                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect            125                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          570                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  695                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                 16926                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  1969                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               971                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                         3251                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1662                       # Number of branches executed
system.cpu.iew.exec_stores                       1282                       # Number of stores executed
system.cpu.iew.exec_rate                     0.430063                       # Inst execution rate
system.cpu.iew.wb_sent                          16636                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                         16374                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                     11006                       # num instructions producing a value
system.cpu.iew.wb_consumers                     17135                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.416038                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.642311                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts           11720                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               588                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        19924                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.489209                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.394281                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        16684     83.74%     83.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         1003      5.03%     88.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          547      2.75%     91.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          737      3.70%     95.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          365      1.83%     97.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          142      0.71%     97.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          113      0.57%     98.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           73      0.37%     98.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          260      1.30%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        19924                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           1988                       # Number of memory references committed
system.cpu.commit.loads                          1053                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                       1208                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      9653                       # Number of committed integer instructions.
system.cpu.commit.function_calls                  106                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            1      0.01%      0.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu             7748     79.49%     79.50% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult               3      0.03%     79.53% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                7      0.07%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     79.60% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead            1053     10.80%     90.41% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite            935      9.59%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total              9747                       # Class of committed instruction
system.cpu.commit.bw_lim_events                   260                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                        41131                       # The number of ROB reads
system.cpu.rob.rob_writes                       44929                       # The number of ROB writes
system.cpu.timesIdled                             158                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           17464                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
system.cpu.committedOps                          9747                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               7.315428                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.315428                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.136697                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.136697                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    21341                       # number of integer regfile reads
system.cpu.int_regfile_writes                   13120                       # number of integer regfile writes
system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
system.cpu.cc_regfile_reads                      8069                       # number of cc regfile reads
system.cpu.cc_regfile_writes                     5036                       # number of cc regfile writes
system.cpu.misc_regfile_reads                    7491                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            82.331185                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                2400                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             17.021277                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    82.331185                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.020100                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.020100                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              5369                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             5369                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         1543                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1543                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          857                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            857                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          2400                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             2400                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         2400                       # number of overall hits
system.cpu.dcache.overall_hits::total            2400                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          136                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           136                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           78                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           78                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          214                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            214                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          214                       # number of overall misses
system.cpu.dcache.overall_misses::total           214                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      9815500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      9815500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      5771000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      5771000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     15586500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     15586500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     15586500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     15586500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1679                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1679                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2614                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2614                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2614                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2614                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081001                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.081001                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.083422                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.083422                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.081867                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.081867                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.081867                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.081867                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72834.112150                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 72834.112150                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          201                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    40.200000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           72                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           72                       # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data           72                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total           72                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data           72                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total           72                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           64                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           78                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           78                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5009500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      5009500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5588000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      5588000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10597500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     10597500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10597500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     10597500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.038118                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.038118                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083422                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083422                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.054323                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.054323                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.054323                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.054323                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           131.539722                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                1800                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               276                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              6.521739                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   131.539722                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.064228                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.064228                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          276                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          121                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.134766                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              4612                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             4612                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         1800                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1800                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          1800                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1800                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         1800                       # number of overall hits
system.cpu.icache.overall_hits::total            1800                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          368                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           368                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          368                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            368                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          368                       # number of overall misses
system.cpu.icache.overall_misses::total           368                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     25557250                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     25557250                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     25557250                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     25557250                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     25557250                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     25557250                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         2168                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         2168                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         2168                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         2168                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         2168                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         2168                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.169742                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.169742                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.169742                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.169742                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.169742                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.169742                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 69449.048913                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 69449.048913                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           92                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           92                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           92                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           92                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           92                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           92                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          276                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          276                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          276                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          276                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          276                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20059000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     20059000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20059000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     20059000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20059000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     20059000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.127306                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.127306                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.127306                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.127306                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.127306                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.127306                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          163.220102                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              338                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.002959                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   131.613484                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    31.606618                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004017                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.000965                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.004981                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          338                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010315                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             3760                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            3760                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          275                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           64                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          339                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           78                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           78                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          275                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          142                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           417                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          275                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
system.cpu.l2cache.overall_misses::total          417                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19772500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4946500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     24719000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5510000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      5510000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     19772500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     10456500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     30229000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     19772500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     10456500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     30229000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          276                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           64                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          340                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           78                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           78                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          276                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          142                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          276                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          142                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996377                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.997059                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996377                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.997608                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996377                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.997608                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        71900                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        71900                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        71900                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          275                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           64                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          339                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           78                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           78                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          417                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          417                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16317000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4156000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20473000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4539500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4539500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16317000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8695500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     25012500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16317000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8695500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     25012500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997059                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.997608                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996377                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.997608                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq            340                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           78                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           78                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          552                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          283                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               835                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17664                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              26688                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples          418                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                418    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            418                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         209000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        462500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          2.4                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        234500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
system.membus.trans_dist::ReadReq                 339                       # Transaction distribution
system.membus.trans_dist::ReadResp                338                       # Transaction distribution
system.membus.trans_dist::ReadExReq                78                       # Transaction distribution
system.membus.trans_dist::ReadExResp               78                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          833                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total          833                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    833                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total        26624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   26624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples               417                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     417    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 417                       # Request fanout histogram
system.membus.reqLayer0.occupancy              505000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3897000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             19.8                       # Layer utilization (%)

---------- End Simulation Statistics   ----------