path: root/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000013                       # Number of seconds simulated
sim_ticks                                    12803000                       # Number of ticks simulated
final_tick                                   12803000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  24032                       # Simulator instruction rate (inst/s)
host_op_rate                                    43521                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               56800152                       # Simulator tick rate (ticks/s)
host_mem_usage                                 227452                       # Number of bytes of host memory used
host_seconds                                     0.23                       # Real time elapsed on the host
sim_insts                                        5416                       # Number of instructions simulated
sim_ops                                          9809                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              9280                       # Number of bytes read from this memory
system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        19264                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           19264                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                145                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst           1504647348                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            724830118                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              2229477466                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      1504647348                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         1504647348                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          1504647348                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           724830118                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             2229477466                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                   11                       # Number of system calls
system.cpu.numCycles                            25607                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                     3125                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted               3125                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect                558                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups                  2605                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                      830                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles               8034                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          14981                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        3125                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches                830                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          4070                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    2483                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles                   3408                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   41                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           244                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                      1957                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   281                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              17679                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.502687                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.975668                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    13710     77.55%     77.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      177      1.00%     78.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      164      0.93%     79.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      211      1.19%     80.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      170      0.96%     81.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      182      1.03%     82.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      260      1.47%     84.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      162      0.92%     85.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     2643     14.95%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                17679                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.122037                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.585035                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                     8588                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  3390                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      3692                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   127                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                   1882                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts                  25327                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                   1882                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                     8910                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    2031                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles            505                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      3461                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                   890                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  23802                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                     47                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents                   747                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents                1                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands               34224                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 68607                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            68591                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                 14707                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                    19517                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 35                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             35                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                      1875                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 2306                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1775                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      21232                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  40                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                     17582                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued                92                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined           10865                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined        19620                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             27                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         17679                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.994513                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.826049                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               12114     68.52%     68.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1582      8.95%     77.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                1012      5.72%     83.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 689      3.90%     87.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 696      3.94%     91.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 692      3.91%     94.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 627      3.55%     98.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                 233      1.32%     99.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  34      0.19%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           17679                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     133     73.08%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                     29     15.93%     89.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    20     10.99%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                 14185     80.68%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.70% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 1924     10.94%     91.64% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1469      8.36%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  17582                       # Type of FU issued
system.cpu.iq.rate                           0.686609                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                         182                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.010351                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              53109                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             32144                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses        16183                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                  17756                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads              148                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1250                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses           14                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           11                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          841                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                   1882                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                    1425                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                    33                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               21272                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                46                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  2306                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1775                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 36                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             11                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect             65                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          640                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  705                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                 16602                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  1794                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               980                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                         3144                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1642                       # Number of branches executed
system.cpu.iew.exec_stores                       1350                       # Number of stores executed
system.cpu.iew.exec_rate                     0.648338                       # Inst execution rate
system.cpu.iew.wb_sent                          16384                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                         16187                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                     10480                       # num instructions producing a value
system.cpu.iew.wb_consumers                     24095                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.632132                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.434945                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts           5416                       # The number of committed instructions
system.cpu.commit.commitCommittedOps             9809                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts           11462                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               589                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        15797                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.620941                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.463366                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        12065     76.38%     76.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         1534      9.71%     86.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          576      3.65%     89.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          731      4.63%     94.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          367      2.32%     96.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          129      0.82%     97.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          134      0.85%     98.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           75      0.47%     98.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          186      1.18%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        15797                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 5416                       # Number of instructions committed
system.cpu.commit.committedOps                   9809                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           1990                       # Number of memory references committed
system.cpu.commit.loads                          1056                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                       1214                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      9714                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events                   186                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                        36882                       # The number of ROB reads
system.cpu.rob.rob_writes                       44457                       # The number of ROB writes
system.cpu.timesIdled                             153                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                            7928                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        5416                       # Number of Instructions Simulated
system.cpu.committedOps                          9809                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total                  5416                       # Number of Instructions Simulated
system.cpu.cpi                               4.728028                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         4.728028                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.211505                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.211505                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    35136                       # number of integer regfile reads
system.cpu.int_regfile_writes                   21832                       # number of integer regfile writes
system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
system.cpu.misc_regfile_reads                    7303                       # number of misc regfile reads
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.tagsinuse                144.987593                       # Cycle average of tags in use
system.cpu.icache.total_refs                     1569                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    302                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   5.195364                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     144.987593                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.070795                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.070795                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst         1569                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1569                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          1569                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1569                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         1569                       # number of overall hits
system.cpu.icache.overall_hits::total            1569                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          388                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           388                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          388                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            388                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          388                       # number of overall misses
system.cpu.icache.overall_misses::total           388                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     14367500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     14367500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     14367500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     14367500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     14367500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     14367500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         1957                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         1957                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         1957                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         1957                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         1957                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         1957                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.198263                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.198263                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.198263                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.198263                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.198263                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.198263                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37029.639175                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 37029.639175                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37029.639175                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 37029.639175                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37029.639175                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 37029.639175                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           86                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           86                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           86                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           86                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           86                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           86                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          302                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          302                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          302                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          302                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          302                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11138000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     11138000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11138000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     11138000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11138000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     11138000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.154318                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.154318                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.154318                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.154318                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.154318                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.154318                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36880.794702                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36880.794702                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36880.794702                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36880.794702                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36880.794702                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36880.794702                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.tagsinuse                 83.196834                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     2330                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                    144                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  16.180556                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data      83.196834                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.020312                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.020312                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data         1472                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1472                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          2330                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             2330                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         2330                       # number of overall hits
system.cpu.dcache.overall_hits::total            2330                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          112                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           112                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           76                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          188                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            188                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          188                       # number of overall misses
system.cpu.dcache.overall_misses::total           188                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      4401500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      4401500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      3078500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      3078500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data      7480000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total      7480000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data      7480000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total      7480000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1584                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1584                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          934                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2518                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2518                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2518                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2518                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070707                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.070707                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081370                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.081370                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.074662                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.074662                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.074662                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.074662                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39299.107143                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 39299.107143                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40506.578947                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 40506.578947                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39787.234043                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39787.234043                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39787.234043                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39787.234043                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           43                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           43                       # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data           43                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total           43                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data           43                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total           43                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           69                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           76                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           76                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          145                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          145                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          145                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          145                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2699500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      2699500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2850500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      2850500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5550000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      5550000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5550000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      5550000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.043561                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.043561                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081370                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081370                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057585                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.057585                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.057585                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.057585                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39123.188406                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39123.188406                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37506.578947                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37506.578947                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38275.862069                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38275.862069                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38275.862069                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38275.862069                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse               177.887385                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                   369                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.002710                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst    144.949907                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data     32.937478                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst     0.004424                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.001005                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.005429                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          301                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           69                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          370                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           76                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           76                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          301                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          145                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          145                       # number of overall misses
system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10831500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2627000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     13458500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2772000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      2772000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     10831500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      5399000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     16230500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     10831500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      5399000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     16230500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          302                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           69                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          371                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           76                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           76                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          302                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          145                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          447                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          302                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          145                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          447                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996689                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.997305                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996689                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.997763                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996689                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.997763                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35985.049834                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38072.463768                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36374.324324                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36473.684211                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36473.684211                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35985.049834                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37234.482759                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 36391.255605                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35985.049834                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37234.482759                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 36391.255605                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           69                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          370                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           76                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           76                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          145                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          145                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9877000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2416500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12293500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2541500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2541500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9877000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4958000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     14835000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9877000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4958000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     14835000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997305                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.997763                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.997763                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32813.953488                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35021.739130                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33225.675676                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32813.953488                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34193.103448                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33262.331839                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32813.953488                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34193.103448                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33262.331839                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------