path: root/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000020                       # Number of seconds simulated
sim_ticks                                    19639500                       # Number of ticks simulated
final_tick                                   19639500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  28578                       # Simulator instruction rate (inst/s)
host_op_rate                                    51768                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              104294046                       # Simulator tick rate (ticks/s)
host_mem_usage                                 245432                       # Number of bytes of host memory used
host_seconds                                     0.19                       # Real time elapsed on the host
sim_insts                                        5380                       # Number of instructions simulated
sim_ops                                          9747                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             17536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              9088                       # Number of bytes read from this memory
system.physmem.bytes_read::total                26624                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        17536                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           17536                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                274                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                142                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            892894422                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            462740905                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1355635327                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       892894422                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          892894422                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           892894422                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           462740905                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1355635327                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           417                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                            417                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                        26624                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                  26624                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                    34                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                     1                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                     6                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                     8                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                    51                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                    44                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                    20                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                    35                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                    23                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                    73                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                   63                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                   17                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                    2                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                   17                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                    6                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                   17                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                        19591000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                     417                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                       248                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       126                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        37                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           88                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean             216                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     132.605669                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     322.610045                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64                42     47.73%     47.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128               13     14.77%     62.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192               12     13.64%     76.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256                4      4.55%     80.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320                6      6.82%     87.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384                3      3.41%     90.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512                1      1.14%     92.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640                1      1.14%     93.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704                1      1.14%     94.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768                1      1.14%     95.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960                2      2.27%     97.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344               1      1.14%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368               1      1.14%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             88                       # Bytes accessed per row activation
system.physmem.totQLat                        1395750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                  11125750                       # Sum of mem lat for all requests
system.physmem.totBusLat                      2085000                       # Total cycles spent in databus access
system.physmem.totBankLat                     7645000                       # Total cycles spent in bank access
system.physmem.avgQLat                        3347.12                       # Average queueing delay per request
system.physmem.avgBankLat                    18333.33                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  26680.46                       # Average memory access latency
system.physmem.avgRdBW                        1355.64                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                1355.64                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                          10.59                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.57                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                        329                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   78.90                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        46980.82                       # Average gap between requests
system.membus.throughput                   1355635327                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 340                       # Transaction distribution
system.membus.trans_dist::ReadResp                339                       # Transaction distribution
system.membus.trans_dist::ReadExReq                77                       # Transaction distribution
system.membus.trans_dist::ReadExResp               77                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          833                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total          833                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port          833                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    833                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total        26624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port        26624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               26624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  26624                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              505500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3891500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             19.8                       # Layer utilization (%)
system.cpu.branchPred.lookups                    3060                       # Number of BP lookups
system.cpu.branchPred.condPredicted              3060                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               546                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 2257                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     719                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             31.856447                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     208                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 72                       # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls                   11                       # Number of system calls
system.cpu.numCycles                            39280                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles              10420                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          14154                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        3060                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches                927                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          3932                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    2487                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles                   5289                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   61                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           384                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                      1977                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   258                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              21952                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.145317                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.661061                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    18121     82.55%     82.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      212      0.97%     83.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      149      0.68%     84.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      217      0.99%     85.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      180      0.82%     86.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      202      0.92%     86.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      278      1.27%     88.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      161      0.73%     88.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     2432     11.08%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                21952                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.077902                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.360336                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                    11197                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  5173                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      3579                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   137                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                   1866                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts                  24141                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                   1866                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                    11552                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    3842                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles            569                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      3343                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                   780                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  22717                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    10                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                     35                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents                   666                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands               25267                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 55251                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            55235                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                 11063                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                    14204                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 30                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             30                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                      2015                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 2290                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1582                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      20306                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  28                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                     17094                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued               292                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined            9804                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined        14093                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         21952                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.778699                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.655311                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               16455     74.96%     74.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1544      7.03%     81.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                1078      4.91%     86.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 728      3.32%     90.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 707      3.22%     93.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 584      2.66%     96.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 572      2.61%     98.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                 242      1.10%     99.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  42      0.19%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           21952                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     143     77.72%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     77.72% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                     26     14.13%     91.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    15      8.15%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 3      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                 13719     80.26%     80.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    4      0.02%     80.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 1979     11.58%     91.92% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1382      8.08%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  17094                       # Type of FU issued
system.cpu.iq.rate                           0.435183                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                         184                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.010764                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              56608                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             30145                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses        15699                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                  17271                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads              170                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1237                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses           11                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           12                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          647                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            12                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                   1866                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                    3033                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                    35                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               20334                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                50                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  2290                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1582                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 28                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             12                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect            113                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          578                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  691                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                 16182                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  1848                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               912                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                         3125                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1615                       # Number of branches executed
system.cpu.iew.exec_stores                       1277                       # Number of stores executed
system.cpu.iew.exec_rate                     0.411965                       # Inst execution rate
system.cpu.iew.wb_sent                          15923                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                         15703                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                     10139                       # num instructions producing a value
system.cpu.iew.wb_consumers                     15623                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.399771                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.648979                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts           10598                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               599                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        20086                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.485263                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.340827                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        16512     82.21%     82.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         1365      6.80%     89.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          596      2.97%     91.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          708      3.52%     95.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          362      1.80%     97.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          137      0.68%     97.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          121      0.60%     98.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           73      0.36%     98.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          212      1.06%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        20086                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           1988                       # Number of memory references committed
system.cpu.commit.loads                          1053                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                       1208                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      9654                       # Number of committed integer instructions.
system.cpu.commit.function_calls                  106                       # Number of function calls committed.
system.cpu.commit.bw_lim_events                   212                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                        40219                       # The number of ROB reads
system.cpu.rob.rob_writes                       42582                       # The number of ROB writes
system.cpu.timesIdled                             167                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           17328                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
system.cpu.committedOps                          9747                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total                  5380                       # Number of Instructions Simulated
system.cpu.cpi                               7.301115                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.301115                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.136965                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.136965                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    28824                       # number of integer regfile reads
system.cpu.int_regfile_writes                   17237                       # number of integer regfile writes
system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
system.cpu.misc_regfile_reads                    7122                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.throughput              1362152804                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq            342                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           341                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           77                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           77                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side          550                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side          287                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count                      837                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        17600                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side         9152                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size                 26752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus             26752                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy         209500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        463250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          2.4                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        239750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
system.cpu.icache.tags.replacements                      0                       # number of replacements
system.cpu.icache.tags.tagsinuse                130.740950                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                     1608                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs                    275                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs                   5.847273                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst     130.740950                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst      0.063838                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total         0.063838                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst         1608                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1608                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          1608                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1608                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         1608                       # number of overall hits
system.cpu.icache.overall_hits::total            1608                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          369                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           369                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          369                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            369                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          369                       # number of overall misses
system.cpu.icache.overall_misses::total           369                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     24439500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     24439500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     24439500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     24439500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     24439500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     24439500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         1977                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         1977                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         1977                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         1977                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         1977                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         1977                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.186646                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.186646                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.186646                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.186646                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.186646                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.186646                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66231.707317                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 66231.707317                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66231.707317                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 66231.707317                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 66231.707317                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 66231.707317                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs           70                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs           70                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           94                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           94                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           94                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           94                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           94                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           94                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          275                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          275                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          275                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          275                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19054250                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     19054250                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19054250                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     19054250                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19054250                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     19054250                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.139100                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.139100                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.139100                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.139100                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.139100                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.139100                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69288.181818                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69288.181818                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69288.181818                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 69288.181818                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                     0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse               163.561658                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                       2                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs                   339                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs                  0.005900                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst    130.812999                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data     32.748659                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003992                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.000999                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total        0.004992                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          274                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           66                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          340                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           77                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           77                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          274                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          143                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           417                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          274                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          143                       # number of overall misses
system.cpu.l2cache.overall_misses::total          417                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18767750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5075750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     23843500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5461000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      5461000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     18767750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     10536750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     29304500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     18767750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     10536750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     29304500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          275                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           67                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          342                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           77                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           77                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          275                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          144                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          419                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          275                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          144                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          419                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996364                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.985075                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.994152                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996364                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.993056                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.995227                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996364                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.993056                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.995227                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68495.437956                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76905.303030                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70127.941176                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70922.077922                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70922.077922                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68495.437956                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73683.566434                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70274.580336                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68495.437956                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73683.566434                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70274.580336                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          274                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           66                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          340                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           77                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           77                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          274                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          143                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          417                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          274                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          417                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15323250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4265250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     19588500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4500500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4500500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15323250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8765750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     24089000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15323250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8765750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     24089000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996364                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.985075                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994152                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996364                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.993056                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.995227                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996364                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.993056                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.995227                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55924.270073                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        64625                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57613.235294                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58448.051948                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58448.051948                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55924.270073                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61298.951049                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57767.386091                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                      0                       # number of replacements
system.cpu.dcache.tags.tagsinuse                 82.722336                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                     2341                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs                    143                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs                  16.370629                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data      82.722336                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data      0.020196                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total         0.020196                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data         1483                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1483                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          2341                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             2341                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         2341                       # number of overall hits
system.cpu.dcache.overall_hits::total            2341                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          133                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           133                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           77                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           77                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          210                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            210                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          210                       # number of overall misses
system.cpu.dcache.overall_misses::total           210                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      9610000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      9610000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      5723000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      5723000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     15333000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     15333000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     15333000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     15333000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1616                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1616                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2551                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2551                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2551                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2551                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.082302                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.082302                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.082353                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.082353                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.082321                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.082321                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.082321                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.082321                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72255.639098                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72255.639098                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74324.675325                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74324.675325                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73014.285714                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73014.285714                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73014.285714                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73014.285714                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          163                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    54.333333                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           66                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data           66                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total           66                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data           66                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total           66                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           67                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           67                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           77                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           77                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          144                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          144                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          144                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          144                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5151750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      5151750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5538000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      5538000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10689750                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     10689750                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10689750                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     10689750                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.041460                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.041460                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.082353                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.082353                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.056448                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.056448                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.056448                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.056448                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------