path: root/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000026                       # Number of seconds simulated
sim_ticks                                    25580500                       # Number of ticks simulated
final_tick                                   25580500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  85448                       # Simulator instruction rate (inst/s)
host_op_rate                                    85436                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              171120344                       # Simulator tick rate (ticks/s)
host_mem_usage                                 253996                       # Number of bytes of host memory used
host_seconds                                     0.15                       # Real time elapsed on the host
sim_insts                                       12770                       # Number of instructions simulated
sim_ops                                         12770                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             39680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             21824                       # Number of bytes read from this memory
system.physmem.bytes_read::total                61504                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        39680                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           39680                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                620                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                341                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   961                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst           1551181564                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            853149860                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              2404331424                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      1551181564                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         1551181564                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          1551181564                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           853149860                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             2404331424                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           962                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         962                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    61568                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     61568                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  83                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 150                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  78                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  59                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  86                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  46                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  32                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  50                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  41                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  37                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 28                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 34                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 15                       # Per bank write bursts
system.physmem.perBankRdBursts::13                120                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 67                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 36                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        25549500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     962                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       350                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       315                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       188                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        80                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        23                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          209                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      281.722488                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     176.924618                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     290.527007                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             69     33.01%     33.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           64     30.62%     63.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           20      9.57%     73.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           12      5.74%     78.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           11      5.26%     84.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            8      3.83%     88.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            9      4.31%     92.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            4      1.91%     94.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           12      5.74%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            209                       # Bytes accessed per row activation
system.physmem.totQLat                       12704750                       # Total ticks spent queuing
system.physmem.totMemAccLat                  30742250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      4810000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13206.60                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31956.60                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        2406.83                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     2406.83                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                          18.80                       # Data bus utilization in percentage
system.physmem.busUtilRead                      18.80                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.38                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        743                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.23                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        26558.73                       # Average gap between requests
system.physmem.pageHitRate                      77.23                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     824040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     449625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   4453800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               16092810                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                  54750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 23400705                       # Total energy per rank (pJ)
system.physmem_0.averagePower              990.768140                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE         694500                       # Time in different power states
system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        22830000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     733320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     400125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   2683200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               15873930                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 246750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 21463005                       # Total energy per rank (pJ)
system.physmem_1.averagePower              908.727388                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE         326750                       # Time in different power states
system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        22525750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                    4883                       # Number of BP lookups
system.cpu.branchPred.condPredicted              2924                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               790                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 3812                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                    1143                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             29.984260                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     681                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 53                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups             814                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits                150                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses              664                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted          136                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                         4166                       # DTB read hits
system.cpu.dtb.read_misses                         75                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                     4241                       # DTB read accesses
system.cpu.dtb.write_hits                        1988                       # DTB write hits
system.cpu.dtb.write_misses                        49                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                    2037                       # DTB write accesses
system.cpu.dtb.data_hits                         6154                       # DTB hits
system.cpu.dtb.data_misses                        124                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                     6278                       # DTB accesses
system.cpu.itb.fetch_hits                        3823                       # ITB hits
system.cpu.itb.fetch_misses                        51                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                    3874                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload0.num_syscalls                  17                       # Number of system calls
system.cpu.workload1.num_syscalls                  17                       # Number of system calls
system.cpu.numCycles                            51162                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles                749                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          28166                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        4883                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches               1974                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          9785                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                     870                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  559                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines                      3823                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   565                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              26518                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.062146                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.446390                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    21410     80.74%     80.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      517      1.95%     82.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      399      1.50%     84.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      426      1.61%     85.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      581      2.19%     87.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      343      1.29%     89.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      470      1.77%     91.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      262      0.99%     92.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     2110      7.96%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                26518                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.095442                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.550526                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                    35549                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                 11706                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      4004                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   486                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                    721                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                  379                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   151                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                  24714                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   389                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                    721                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                    35923                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    4419                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           1518                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      4115                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                  5770                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  23686                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    47                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                    451                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                    687                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                   4626                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands               17749                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 29662                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            29644                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                  9154                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                     8595                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 57                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             45                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                      1784                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 2582                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1268                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                15                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
system.cpu.memDep1.insertedLoads                 1972                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep1.insertedStores                1081                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep1.conflictingLoads                 6                       # Number of conflicting loads.
system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      21922                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  50                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                     19305                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued                46                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined            9201                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined         4899                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         26518                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.727996                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.455439                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               19215     72.46%     72.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                2319      8.75%     81.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                1762      6.64%     87.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                1149      4.33%     92.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                1009      3.80%     95.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 611      2.30%     98.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 303      1.14%     99.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                  94      0.35%     99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  56      0.21%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           26518                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                      25      8.33%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                    198     66.00%     74.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    77     25.67%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                  6801     65.70%     65.72% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.73% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 2445     23.62%     89.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1101     10.64%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  10352                       # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_1::IntAlu                  5921     66.13%     66.16% # Type of FU issued
system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.17% # Type of FU issued
system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.19% # Type of FU issued
system.cpu.iq.FU_type_1::MemRead                 2023     22.60%     88.79% # Type of FU issued
system.cpu.iq.FU_type_1::MemWrite                1004     11.21%    100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_1::total                   8953                       # Type of FU issued
system.cpu.iq.FU_type::total                    19305      0.00%      0.00% # Type of FU issued
system.cpu.iq.rate                           0.377331                       # Inst issue rate
system.cpu.iq.fu_busy_cnt::0                      160                       # FU busy when requested
system.cpu.iq.fu_busy_cnt::1                      140                       # FU busy when requested
system.cpu.iq.fu_busy_cnt::total                  300                       # FU busy when requested
system.cpu.iq.fu_busy_rate::0                0.008288                       # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::1                0.007252                       # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total            0.015540                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              65432                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             31184                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses        17495                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                  19579                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads               93                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1397                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          403                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           284                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread1.forwLoads               47                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread1.squashedLoads          787                       # Number of loads squashed
system.cpu.iew.lsq.thread1.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread1.memOrderViolation           13                       # Number of memory ordering violations
system.cpu.iew.lsq.thread1.squashedStores          216                       # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread1.cacheBlocked           280                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                    721                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                    2770                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                   755                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               22107                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts               169                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  4554                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 2349                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 50                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                     22                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   722                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             32                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect            132                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          639                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  771                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                 18606                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0               2294                       # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::1               1956                       # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::total           4250                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               699                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
system.cpu.iew.exec_nop::0                         68                       # number of nop insts executed
system.cpu.iew.exec_nop::1                         67                       # number of nop insts executed
system.cpu.iew.exec_nop::total                    135                       # number of nop insts executed
system.cpu.iew.exec_refs::0                      3353                       # number of memory reference insts executed
system.cpu.iew.exec_refs::1                      2946                       # number of memory reference insts executed
system.cpu.iew.exec_refs::total                  6299                       # number of memory reference insts executed
system.cpu.iew.exec_branches::0                  1561                       # Number of branches executed
system.cpu.iew.exec_branches::1                  1400                       # Number of branches executed
system.cpu.iew.exec_branches::total              2961                       # Number of branches executed
system.cpu.iew.exec_stores::0                    1059                       # Number of stores executed
system.cpu.iew.exec_stores::1                     990                       # Number of stores executed
system.cpu.iew.exec_stores::total                2049                       # Number of stores executed
system.cpu.iew.exec_rate                     0.363668                       # Inst execution rate
system.cpu.iew.wb_sent::0                        9443                       # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::1                        8345                       # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::total                   17788                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count::0                       9266                       # cumulative count of insts written-back
system.cpu.iew.wb_count::1                       8249                       # cumulative count of insts written-back
system.cpu.iew.wb_count::total                  17515                       # cumulative count of insts written-back
system.cpu.iew.wb_producers::0                   4880                       # num instructions producing a value
system.cpu.iew.wb_producers::1                   4386                       # num instructions producing a value
system.cpu.iew.wb_producers::total               9266                       # num instructions producing a value
system.cpu.iew.wb_consumers::0                   6580                       # num instructions consuming a value
system.cpu.iew.wb_consumers::1                   5911                       # num instructions consuming a value
system.cpu.iew.wb_consumers::total              12491                       # num instructions consuming a value
system.cpu.iew.wb_rate::0                    0.181111                       # insts written-back per cycle
system.cpu.iew.wb_rate::1                    0.161233                       # insts written-back per cycle
system.cpu.iew.wb_rate::total                0.342344                       # insts written-back per cycle
system.cpu.iew.wb_fanout::0                  0.741641                       # average fanout of values written-back
system.cpu.iew.wb_fanout::1                  0.742006                       # average fanout of values written-back
system.cpu.iew.wb_fanout::total              0.741814                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts            9276                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               642                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        26498                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.483206                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.376058                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        21430     80.87%     80.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         2543      9.60%     90.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          900      3.40%     93.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          463      1.75%     95.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          308      1.16%     96.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          165      0.62%     97.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          178      0.67%     98.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7          141      0.53%     98.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          370      1.40%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        26498                       # Number of insts commited each cycle
system.cpu.commit.committedInsts::0              6402                       # Number of instructions committed
system.cpu.commit.committedInsts::1              6402                       # Number of instructions committed
system.cpu.commit.committedInsts::total         12804                       # Number of instructions committed
system.cpu.commit.committedOps::0                6402                       # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::1                6402                       # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::total           12804                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count::0                      0                       # Number of s/w prefetches committed
system.cpu.commit.swp_count::1                      0                       # Number of s/w prefetches committed
system.cpu.commit.swp_count::total                  0                       # Number of s/w prefetches committed
system.cpu.commit.refs::0                        2050                       # Number of memory references committed
system.cpu.commit.refs::1                        2050                       # Number of memory references committed
system.cpu.commit.refs::total                    4100                       # Number of memory references committed
system.cpu.commit.loads::0                       1185                       # Number of loads committed
system.cpu.commit.loads::1                       1185                       # Number of loads committed
system.cpu.commit.loads::total                   2370                       # Number of loads committed
system.cpu.commit.membars::0                        0                       # Number of memory barriers committed
system.cpu.commit.membars::1                        0                       # Number of memory barriers committed
system.cpu.commit.membars::total                    0                       # Number of memory barriers committed
system.cpu.commit.branches::0                    1056                       # Number of branches committed
system.cpu.commit.branches::1                    1056                       # Number of branches committed
system.cpu.commit.branches::total                2112                       # Number of branches committed
system.cpu.commit.fp_insts::0                      10                       # Number of committed floating point instructions.
system.cpu.commit.fp_insts::1                      10                       # Number of committed floating point instructions.
system.cpu.commit.fp_insts::total                  20                       # Number of committed floating point instructions.
system.cpu.commit.int_insts::0                   6319                       # Number of committed integer instructions.
system.cpu.commit.int_insts::1                   6319                       # Number of committed integer instructions.
system.cpu.commit.int_insts::total              12638                       # Number of committed integer instructions.
system.cpu.commit.function_calls::0               127                       # Number of function calls committed.
system.cpu.commit.function_calls::1               127                       # Number of function calls committed.
system.cpu.commit.function_calls::total           254                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass           19      0.30%      0.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu             4330     67.64%     67.93% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult               1      0.02%     67.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              2      0.03%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead            1185     18.51%     86.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite            865     13.51%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total              6402                       # Class of committed instruction
system.cpu.commit.op_class_1::No_OpClass           19      0.30%      0.30% # Class of committed instruction
system.cpu.commit.op_class_1::IntAlu             4330     67.64%     67.93% # Class of committed instruction
system.cpu.commit.op_class_1::IntMult               1      0.02%     67.95% # Class of committed instruction
system.cpu.commit.op_class_1::IntDiv                0      0.00%     67.95% # Class of committed instruction
system.cpu.commit.op_class_1::FloatAdd              2      0.03%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCmp              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCvt              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatMult             0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatDiv              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatSqrt             0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAdd               0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAddAcc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAlu               0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCmp               0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCvt               0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMisc              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMult              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMultAcc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShift             0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShiftAcc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdSqrt              0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAdd            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAlu            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCmp            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCvt            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatDiv            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMisc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMult            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMultAcc            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatSqrt            0      0.00%     67.98% # Class of committed instruction
system.cpu.commit.op_class_1::MemRead            1185     18.51%     86.49% # Class of committed instruction
system.cpu.commit.op_class_1::MemWrite            865     13.51%    100.00% # Class of committed instruction
system.cpu.commit.op_class_1::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_1::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_1::total              6402                       # Class of committed instruction
system.cpu.commit.op_class::total               12804      0.00%      0.00% # Class of committed instruction
system.cpu.commit.bw_lim_events                   370                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                       113336                       # The number of ROB reads
system.cpu.rob.rob_writes                       45860                       # The number of ROB writes
system.cpu.timesIdled                             410                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           24644                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0                     6385                       # Number of Instructions Simulated
system.cpu.committedInsts::1                     6385                       # Number of Instructions Simulated
system.cpu.committedInsts::total                12770                       # Number of Instructions Simulated
system.cpu.committedOps::0                       6385                       # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1                       6385                       # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total                  12770                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi::0                            8.012843                       # CPI: Cycles Per Instruction
system.cpu.cpi::1                            8.012843                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         4.006421                       # CPI: Total CPI of All Threads
system.cpu.ipc::0                            0.124800                       # IPC: Instructions Per Cycle
system.cpu.ipc::1                            0.124800                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.249599                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    23495                       # number of integer regfile reads
system.cpu.int_regfile_writes                   13160                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      2                       # number of misc regfile writes
system.cpu.dcache.tags.replacements::0              0                       # number of replacements
system.cpu.dcache.tags.replacements::1              0                       # number of replacements
system.cpu.dcache.tags.replacements::total            0                       # number of replacements
system.cpu.dcache.tags.tagsinuse           216.394211                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                4263                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               341                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             12.501466                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   216.394211                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.052831                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.052831                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          341                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          269                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.083252                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses             10889                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses            10889                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         3245                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            3245                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data         1018                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total           1018                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          4263                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             4263                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         4263                       # number of overall hits
system.cpu.dcache.overall_hits::total            4263                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          299                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           299                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          712                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          712                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         1011                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           1011                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         1011                       # number of overall misses
system.cpu.dcache.overall_misses::total          1011                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     23300000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     23300000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     52494934                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     52494934                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     75794934                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     75794934                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     75794934                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     75794934                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         3544                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         3544                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         5274                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         5274                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         5274                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         5274                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.084368                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.084368                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.411561                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.411561                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.191695                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.191695                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.191695                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.191695                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77926.421405                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77926.421405                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73728.839888                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73728.839888                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74970.261128                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 74970.261128                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74970.261128                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 74970.261128                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         5977                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               130                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.976923                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          103                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          103                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          566                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          566                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          669                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          669                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          669                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          669                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          196                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          196                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data          146                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total          146                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          342                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          342                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          342                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          342                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17233500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     17233500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12825986                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     12825986                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     30059486                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     30059486                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     30059486                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     30059486                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.055305                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.055305                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.064846                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.064846                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.064846                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.064846                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87926.020408                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87926.020408                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87849.219178                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87849.219178                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918                       # average overall mshr miss latency
system.cpu.icache.tags.replacements::0              7                       # number of replacements
system.cpu.icache.tags.replacements::1              0                       # number of replacements
system.cpu.icache.tags.replacements::total            7                       # number of replacements
system.cpu.icache.tags.tagsinuse           317.276824                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                2916                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               623                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              4.680578                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   317.276824                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.154920                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.154920                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          616                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          237                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          379                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.300781                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              8261                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             8261                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         2916                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            2916                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          2916                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             2916                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         2916                       # number of overall hits
system.cpu.icache.overall_hits::total            2916                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          903                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           903                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          903                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            903                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          903                       # number of overall misses
system.cpu.icache.overall_misses::total           903                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     69936495                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     69936495                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     69936495                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     69936495                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     69936495                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     69936495                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         3819                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         3819                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         3819                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         3819                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         3819                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         3819                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.236449                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.236449                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.236449                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.236449                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.236449                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.236449                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77449.053156                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77449.053156                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77449.053156                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77449.053156                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77449.053156                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77449.053156                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         3083                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                55                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    56.054545                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks            7                       # number of writebacks
system.cpu.icache.writebacks::total                 7                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          280                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          280                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          280                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          280                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          280                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          280                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          623                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          623                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          623                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          623                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          623                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          623                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50404995                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     50404995                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50404995                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     50404995                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50404995                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     50404995                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.163132                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.163132                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.163132                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.163132                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.163132                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.163132                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80906.894061                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80906.894061                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061                       # average overall mshr miss latency
system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          438.773475                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                 10                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              815                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.012270                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   317.771557                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   121.001918                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009698                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.003693                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.013390                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          815                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          286                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          529                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.024872                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             8737                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            8737                       # Number of data accesses
system.cpu.l2cache.WritebackClean_hits::writebacks            7                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total            7                       # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            3                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total            3                       # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data          146                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          146                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          620                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          620                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data          196                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total          196                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          620                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          342                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           962                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          620                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          342                       # number of overall misses
system.cpu.l2cache.overall_misses::total          962                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     12598500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     12598500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     49432000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     49432000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     16931000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     16931000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     49432000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     29529500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     78961500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     49432000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     29529500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     78961500                       # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks            7                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total            7                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data          146                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total          146                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          623                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          623                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          196                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total          196                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          623                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          342                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          965                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          623                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          342                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          965                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.995185                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.995185                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995185                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.996891                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995185                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.996891                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86291.095890                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86291.095890                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79729.032258                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79729.032258                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86382.653061                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86382.653061                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79729.032258                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86343.567251                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82080.561331                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79729.032258                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86343.567251                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82080.561331                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          146                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          146                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          620                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          620                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          196                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total          196                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          620                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          342                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          962                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          620                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          342                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          962                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     11138500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     11138500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43232000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43232000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     14981000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     14981000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43232000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     26119500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     69351500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43232000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     26119500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     69351500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.995185                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.995185                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995185                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.996891                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995185                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.996891                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76291.095890                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76291.095890                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69729.032258                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69729.032258                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76433.673469                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76433.673469                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69729.032258                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76372.807018                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72090.956341                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69729.032258                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76372.807018                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72090.956341                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests          972                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests            9                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp           818                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean            7                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq          146                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp          146                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          623                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq          196                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1253                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          683                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total              1936                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40320                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        21824                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              62144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples          965                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.002073                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.045502                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                963     99.79%     99.79% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  2      0.21%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            965                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         493000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        934500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          3.7                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        511500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
system.membus.trans_dist::ReadResp                815                       # Transaction distribution
system.membus.trans_dist::ReadExReq               146                       # Transaction distribution
system.membus.trans_dist::ReadExResp              146                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           816                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1923                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1923                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        61504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   61504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples               962                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     962    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 962                       # Request fanout histogram
system.membus.reqLayer0.occupancy             1181000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               4.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy            5115750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             20.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------