path: root/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000025                       # Number of seconds simulated
sim_ticks                                    25499500                       # Number of ticks simulated
final_tick                                   25499500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  60058                       # Simulator instruction rate (inst/s)
host_op_rate                                    60053                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              120151989                       # Simulator tick rate (ticks/s)
host_mem_usage                                 226048                       # Number of bytes of host memory used
host_seconds                                     0.21                       # Real time elapsed on the host
sim_insts                                       12744                       # Number of instructions simulated
sim_ops                                         12744                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             40704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             22144                       # Number of bytes read from this memory
system.physmem.bytes_read::total                62848                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        40704                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           40704                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                636                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                346                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   982                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst           1596266593                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            868409184                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              2464675778                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      1596266593                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         1596266593                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          1596266593                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           868409184                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             2464675778                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           982                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         982                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    62848                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     62848                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  86                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 152                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  79                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  59                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  88                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  49                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  33                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  50                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  42                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  39                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 30                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 34                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 15                       # Per bank write bursts
system.physmem.perBankRdBursts::13                120                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 69                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 37                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        25359500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     982                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       342                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       327                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       190                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        82                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          220                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      270.836364                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     169.810990                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     284.156672                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             81     36.82%     36.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           62     28.18%     65.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           22     10.00%     75.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           14      6.36%     81.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           10      4.55%     85.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            7      3.18%     89.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            6      2.73%     91.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            6      2.73%     94.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           12      5.45%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            220                       # Bytes accessed per row activation
system.physmem.totQLat                       12877000                       # Total ticks spent queuing
system.physmem.totMemAccLat                  31289500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      4910000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13113.03                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31863.03                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        2464.68                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     2464.68                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                          19.26                       # Data bus utilization in percentage
system.physmem.busUtilRead                      19.26                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.46                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        752                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.58                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        25824.34                       # Average gap between requests
system.physmem.pageHitRate                      76.58                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     929880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     507375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   4547400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               16092810                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                  54750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 23657895                       # Total energy per rank (pJ)
system.physmem_0.averagePower             1001.657370                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE         688500                       # Time in different power states
system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        22830000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     703080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     383625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   2652000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               15503715                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 591000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 21359100                       # Total energy per rank (pJ)
system.physmem_1.averagePower              903.085461                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE         888000                       # Time in different power states
system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        21996000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                    7477                       # Number of BP lookups
system.cpu.branchPred.condPredicted              4177                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect              1616                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 5400                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     850                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             15.740741                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                    1012                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 79                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                         4911                       # DTB read hits
system.cpu.dtb.read_misses                        100                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                     5011                       # DTB read accesses
system.cpu.dtb.write_hits                        2106                       # DTB write hits
system.cpu.dtb.write_misses                        69                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                    2175                       # DTB write accesses
system.cpu.dtb.data_hits                         7017                       # DTB hits
system.cpu.dtb.data_misses                        169                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                     7186                       # DTB accesses
system.cpu.itb.fetch_hits                        5467                       # ITB hits
system.cpu.itb.fetch_misses                        60                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                    5527                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload0.num_syscalls                  17                       # Number of system calls
system.cpu.workload1.num_syscalls                  17                       # Number of system calls
system.cpu.numCycles                            51000                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles               1416                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          41297                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        7477                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches               1862                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                         10878                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    1697                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  471                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines                      5467                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   803                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              27699                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.490920                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.868697                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    20832     75.21%     75.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      522      1.88%     77.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      376      1.36%     78.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      569      2.05%     80.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      524      1.89%     82.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      456      1.65%     84.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      499      1.80%     85.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      422      1.52%     87.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     3499     12.63%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                27699                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.146608                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.809745                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                    36892                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                 11130                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      5276                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   643                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                   1210                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                  704                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   509                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                  33151                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   887                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                   1210                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                    37566                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    5376                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           1365                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      5257                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                  4377                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  30969                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   146                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                    361                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                    477                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                   3380                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands               23374                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 38597                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            38579                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                  9140                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                    14234                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 57                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             43                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                      2267                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 2994                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1466                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                45                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores               23                       # Number of conflicting stores.
system.cpu.memDep1.insertedLoads                 2948                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep1.insertedStores                1410                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep1.conflictingLoads                 7                       # Number of conflicting loads.
system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      27629                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  50                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                     22900                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued               102                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined           14934                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined         8231                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         27699                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.826745                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.538980                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               19213     69.36%     69.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                2603      9.40%     78.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                1960      7.08%     85.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                1418      5.12%     90.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                1237      4.47%     95.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 696      2.51%     97.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 372      1.34%     99.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                 137      0.49%     99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  63      0.23%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           27699                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                      27      8.23%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.23% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                    211     64.33%     72.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    90     27.44%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                  7493     65.81%     65.83% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.85% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 2715     23.85%     89.70% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1173     10.30%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  11386                       # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_1::IntAlu                  7630     66.27%     66.28% # Type of FU issued
system.cpu.iq.FU_type_1::IntMult                    1      0.01%     66.29% # Type of FU issued
system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     66.29% # Type of FU issued
system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     66.31% # Type of FU issued
system.cpu.iq.FU_type_1::MemRead                 2714     23.57%     89.88% # Type of FU issued
system.cpu.iq.FU_type_1::MemWrite                1165     10.12%    100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_1::total                  11514                       # Type of FU issued
system.cpu.iq.FU_type::total                    22900      0.00%      0.00% # Type of FU issued
system.cpu.iq.rate                           0.449020                       # Inst issue rate
system.cpu.iq.fu_busy_cnt::0                      160                       # FU busy when requested
system.cpu.iq.fu_busy_cnt::1                      168                       # FU busy when requested
system.cpu.iq.fu_busy_cnt::total                  328                       # FU busy when requested
system.cpu.iq.fu_busy_rate::0                0.006987                       # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::1                0.007336                       # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total            0.014323                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              73887                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             42626                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses        20089                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                  23202                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads               64                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1811                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          601                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           281                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread1.forwLoads               75                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread1.squashedLoads         1765                       # Number of loads squashed
system.cpu.iew.lsq.thread1.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread1.memOrderViolation           20                       # Number of memory ordering violations
system.cpu.iew.lsq.thread1.squashedStores          545                       # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread1.cacheBlocked           256                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                   1210                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                    3002                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                   780                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               27815                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts               312                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  5942                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 2876                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 50                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                     29                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   747                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             36                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect            144                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect         1217                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                 1361                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                 21491                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0               2518                       # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::1               2502                       # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::total           5020                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts              1409                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
system.cpu.iew.exec_nop::0                         69                       # number of nop insts executed
system.cpu.iew.exec_nop::1                         67                       # number of nop insts executed
system.cpu.iew.exec_nop::total                    136                       # number of nop insts executed
system.cpu.iew.exec_refs::0                      3616                       # number of memory reference insts executed
system.cpu.iew.exec_refs::1                      3607                       # number of memory reference insts executed
system.cpu.iew.exec_refs::total                  7223                       # number of memory reference insts executed
system.cpu.iew.exec_branches::0                  1734                       # Number of branches executed
system.cpu.iew.exec_branches::1                  1745                       # Number of branches executed
system.cpu.iew.exec_branches::total              3479                       # Number of branches executed
system.cpu.iew.exec_stores::0                    1098                       # Number of stores executed
system.cpu.iew.exec_stores::1                    1105                       # Number of stores executed
system.cpu.iew.exec_stores::total                2203                       # Number of stores executed
system.cpu.iew.exec_rate                     0.421392                       # Inst execution rate
system.cpu.iew.wb_sent::0                       10180                       # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::1                       10330                       # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::total                   20510                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count::0                       9974                       # cumulative count of insts written-back
system.cpu.iew.wb_count::1                      10135                       # cumulative count of insts written-back
system.cpu.iew.wb_count::total                  20109                       # cumulative count of insts written-back
system.cpu.iew.wb_producers::0                   5251                       # num instructions producing a value
system.cpu.iew.wb_producers::1                   5302                       # num instructions producing a value
system.cpu.iew.wb_producers::total              10553                       # num instructions producing a value
system.cpu.iew.wb_consumers::0                   7044                       # num instructions consuming a value
system.cpu.iew.wb_consumers::1                   7008                       # num instructions consuming a value
system.cpu.iew.wb_consumers::total              14052                       # num instructions consuming a value
system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate::0                    0.195569                       # insts written-back per cycle
system.cpu.iew.wb_rate::1                    0.198725                       # insts written-back per cycle
system.cpu.iew.wb_rate::total                0.394294                       # insts written-back per cycle
system.cpu.iew.wb_fanout::0                  0.745457                       # average fanout of values written-back
system.cpu.iew.wb_fanout::1                  0.756564                       # average fanout of values written-back
system.cpu.iew.wb_fanout::total              0.750996                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts           15019                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts              1130                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        27612                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.462770                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.343029                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        22639     81.99%     81.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         2318      8.39%     90.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2         1067      3.86%     94.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          382      1.38%     95.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          325      1.18%     96.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          202      0.73%     97.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          208      0.75%     98.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7          146      0.53%     98.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          325      1.18%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        27612                       # Number of insts commited each cycle
system.cpu.commit.committedInsts::0              6389                       # Number of instructions committed
system.cpu.commit.committedInsts::1              6389                       # Number of instructions committed
system.cpu.commit.committedInsts::total         12778                       # Number of instructions committed
system.cpu.commit.committedOps::0                6389                       # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::1                6389                       # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::total           12778                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count::0                      0                       # Number of s/w prefetches committed
system.cpu.commit.swp_count::1                      0                       # Number of s/w prefetches committed
system.cpu.commit.swp_count::total                  0                       # Number of s/w prefetches committed
system.cpu.commit.refs::0                        2048                       # Number of memory references committed
system.cpu.commit.refs::1                        2048                       # Number of memory references committed
system.cpu.commit.refs::total                    4096                       # Number of memory references committed
system.cpu.commit.loads::0                       1183                       # Number of loads committed
system.cpu.commit.loads::1                       1183                       # Number of loads committed
system.cpu.commit.loads::total                   2366                       # Number of loads committed
system.cpu.commit.membars::0                        0                       # Number of memory barriers committed
system.cpu.commit.membars::1                        0                       # Number of memory barriers committed
system.cpu.commit.membars::total                    0                       # Number of memory barriers committed
system.cpu.commit.branches::0                    1050                       # Number of branches committed
system.cpu.commit.branches::1                    1050                       # Number of branches committed
system.cpu.commit.branches::total                2100                       # Number of branches committed
system.cpu.commit.fp_insts::0                      10                       # Number of committed floating point instructions.
system.cpu.commit.fp_insts::1                      10                       # Number of committed floating point instructions.
system.cpu.commit.fp_insts::total                  20                       # Number of committed floating point instructions.
system.cpu.commit.int_insts::0                   6307                       # Number of committed integer instructions.
system.cpu.commit.int_insts::1                   6307                       # Number of committed integer instructions.
system.cpu.commit.int_insts::total              12614                       # Number of committed integer instructions.
system.cpu.commit.function_calls::0               127                       # Number of function calls committed.
system.cpu.commit.function_calls::1               127                       # Number of function calls committed.
system.cpu.commit.function_calls::total           254                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass           19      0.30%      0.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu             4319     67.60%     67.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult               1      0.02%     67.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.91% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              2      0.03%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead            1183     18.52%     86.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite            865     13.54%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total              6389                       # Class of committed instruction
system.cpu.commit.op_class_1::No_OpClass           19      0.30%      0.30% # Class of committed instruction
system.cpu.commit.op_class_1::IntAlu             4319     67.60%     67.90% # Class of committed instruction
system.cpu.commit.op_class_1::IntMult               1      0.02%     67.91% # Class of committed instruction
system.cpu.commit.op_class_1::IntDiv                0      0.00%     67.91% # Class of committed instruction
system.cpu.commit.op_class_1::FloatAdd              2      0.03%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCmp              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCvt              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatMult             0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatDiv              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatSqrt             0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAdd               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAddAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAlu               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCmp               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCvt               0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMisc              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMult              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMultAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShift             0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShiftAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdSqrt              0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAdd            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAlu            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCmp            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCvt            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatDiv            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMisc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMult            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMultAcc            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatSqrt            0      0.00%     67.94% # Class of committed instruction
system.cpu.commit.op_class_1::MemRead            1183     18.52%     86.46% # Class of committed instruction
system.cpu.commit.op_class_1::MemWrite            865     13.54%    100.00% # Class of committed instruction
system.cpu.commit.op_class_1::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_1::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_1::total              6389                       # Class of committed instruction
system.cpu.commit.op_class::total               12778      0.00%      0.00% # Class of committed instruction
system.cpu.commit.bw_lim_events                   325                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                       130940                       # The number of ROB reads
system.cpu.rob.rob_writes                       58397                       # The number of ROB writes
system.cpu.timesIdled                             389                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           23301                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0                     6372                       # Number of Instructions Simulated
system.cpu.committedInsts::1                     6372                       # Number of Instructions Simulated
system.cpu.committedInsts::total                12744                       # Number of Instructions Simulated
system.cpu.committedOps::0                       6372                       # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1                       6372                       # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total                  12744                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi::0                            8.003766                       # CPI: Cycles Per Instruction
system.cpu.cpi::1                            8.003766                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         4.001883                       # CPI: Total CPI of All Threads
system.cpu.ipc::0                            0.124941                       # IPC: Instructions Per Cycle
system.cpu.ipc::1                            0.124941                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.249882                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    26966                       # number of integer regfile reads
system.cpu.int_regfile_writes                   15368                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      2                       # number of misc regfile writes
system.cpu.dcache.tags.replacements::0              0                       # number of replacements
system.cpu.dcache.tags.replacements::1              0                       # number of replacements
system.cpu.dcache.tags.replacements::total            0                       # number of replacements
system.cpu.dcache.tags.tagsinuse           213.719872                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                5036                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               346                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             14.554913                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   213.719872                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.052178                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.052178                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          346                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          265                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.084473                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses             12454                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses            12454                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         4006                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            4006                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data         1030                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total           1030                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          5036                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             5036                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         5036                       # number of overall hits
system.cpu.dcache.overall_hits::total            5036                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          318                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           318                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          700                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          700                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         1018                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           1018                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         1018                       # number of overall misses
system.cpu.dcache.overall_misses::total          1018                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     26557000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     26557000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     48843926                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     48843926                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     75400926                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     75400926                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     75400926                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     75400926                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         4324                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         4324                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         6054                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         6054                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         6054                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         6054                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.073543                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.073543                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.404624                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.404624                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.168153                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.168153                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.168153                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.168153                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83512.578616                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 83512.578616                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69777.037143                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69777.037143                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74067.707269                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 74067.707269                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74067.707269                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 74067.707269                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         5713                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               130                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.946154                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          116                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          116                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          556                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          556                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          672                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          672                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          672                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          672                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          202                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          202                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data          144                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total          144                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          346                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          346                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          346                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          346                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     18304750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     18304750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     11840493                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     11840493                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     30145243                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     30145243                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     30145243                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     30145243                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046716                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046716                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057152                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.057152                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.057152                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.057152                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90617.574257                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90617.574257                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82225.645833                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82225.645833                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87124.979769                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 87124.979769                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87124.979769                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 87124.979769                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements::0              8                       # number of replacements
system.cpu.icache.tags.replacements::1              0                       # number of replacements
system.cpu.icache.tags.replacements::total            8                       # number of replacements
system.cpu.icache.tags.tagsinuse           322.759154                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                4537                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               638                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.111285                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   322.759154                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.157597                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.157597                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          630                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          243                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          387                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.307617                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses             11558                       # Number of tag accesses
system.cpu.icache.tags.data_accesses            11558                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         4537                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            4537                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          4537                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             4537                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         4537                       # number of overall hits
system.cpu.icache.overall_hits::total            4537                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          923                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           923                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          923                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            923                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          923                       # number of overall misses
system.cpu.icache.overall_misses::total           923                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     70921745                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     70921745                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     70921745                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     70921745                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     70921745                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     70921745                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         5460                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         5460                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         5460                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         5460                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         5460                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         5460                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.169048                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.169048                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.169048                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.169048                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.169048                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.169048                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76838.293608                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76838.293608                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76838.293608                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76838.293608                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76838.293608                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76838.293608                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         3978                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                87                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    45.724138                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          285                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          285                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          285                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          285                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          285                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          285                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          638                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          638                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          638                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          638                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          638                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          638                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     51664496                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     51664496                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     51664496                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     51664496                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     51664496                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     51664496                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116850                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116850                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116850                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.116850                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116850                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.116850                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80978.833856                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80978.833856                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80978.833856                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 80978.833856                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80978.833856                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 80978.833856                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          444.038251                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              838                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.002387                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   323.497640                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   120.540612                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009872                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.003679                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.013551                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          838                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          301                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          537                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025574                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             8854                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            8854                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          636                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          202                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          838                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data          144                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          144                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          636                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          346                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           982                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          636                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          346                       # number of overall misses
system.cpu.l2cache.overall_misses::total          982                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     51000750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     18093750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     69094500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     11692500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     11692500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     51000750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     29786250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     80787000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     51000750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     29786250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     80787000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          638                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          202                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          840                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data          144                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total          144                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          638                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          346                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          984                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          638                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          346                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          984                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996865                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.997619                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996865                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.997967                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996865                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.997967                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80189.858491                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89573.019802                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 82451.670644                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81197.916667                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81197.916667                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80189.858491                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86087.427746                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82267.820774                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80189.858491                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86087.427746                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82267.820774                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          636                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          202                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          838                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          144                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          144                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          636                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          346                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          982                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          636                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          346                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          982                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     43045250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     15573250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58618500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      9895500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      9895500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43045250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     25468750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     68514000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43045250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     25468750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     68514000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996865                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997619                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996865                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.997967                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996865                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.997967                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67681.210692                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77095.297030                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69950.477327                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68718.750000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68718.750000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67681.210692                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73609.104046                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69769.857434                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67681.210692                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73609.104046                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69769.857434                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq            840                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           840                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq          144                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp          144                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1276                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          692                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total              1968                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              62976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples          984                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                984    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            984                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         492000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1076750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          4.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        574250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
system.membus.trans_dist::ReadReq                 838                       # Transaction distribution
system.membus.trans_dist::ReadResp                838                       # Transaction distribution
system.membus.trans_dist::ReadExReq               144                       # Transaction distribution
system.membus.trans_dist::ReadExResp              144                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1964                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1964                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   62848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples               982                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     982    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 982                       # Request fanout histogram
system.membus.reqLayer0.occupancy             1219500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               4.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy            5224000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             20.5                       # Layer utilization (%)

---------- End Simulation Statistics   ----------