blob: 32254e280a2a1e16e5520867afcbeda521c74321 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000353 # Number of seconds simulated
sim_ticks 352925500 # Number of ticks simulated
final_tick 352925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 23308 # Simulator instruction rate (inst/s)
host_op_rate 23308 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40827277 # Simulator tick rate (ticks/s)
host_mem_usage 243536 # Number of bytes of host memory used
host_seconds 8.64 # Real time elapsed on the host
sim_insts 201478 # Number of instructions simulated
sim_ops 201478 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 55168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18368 # Number of bytes read from this memory
system.physmem.bytes_read::total 73536 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 55168 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 55168 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 862 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 287 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1149 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 156316276 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 52044978 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 208361255 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 156316276 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 156316276 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 156316276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 52044978 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 208361255 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 130 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 352925500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 705851 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 201478 # Number of instructions committed
system.cpu.committedOps 201478 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 201477 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 14627 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 30164 # number of instructions that are conditional controls
system.cpu.num_int_insts 201477 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 266871 # number of times the integer registers were read
system.cpu.num_int_register_writes 137624 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 80078 # number of memory refs
system.cpu.num_load_insts 46389 # Number of load instructions
system.cpu.num_store_insts 33689 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 705851 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 44791 # Number of branches fetched
system.cpu.op_class::No_OpClass 132 0.07% 0.07% # Class of executed instruction
system.cpu.op_class::IntAlu 120936 59.99% 60.05% # Class of executed instruction
system.cpu.op_class::IntMult 297 0.15% 60.20% # Class of executed instruction
system.cpu.op_class::IntDiv 166 0.08% 60.28% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.28% # Class of executed instruction
system.cpu.op_class::MemRead 46389 23.01% 83.29% # Class of executed instruction
system.cpu.op_class::MemWrite 33689 16.71% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 201609 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 237.806291 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 79790 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 287 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 278.013937 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 237.806291 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.058058 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.058058 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 287 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.070068 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 160441 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 160441 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 46314 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 46314 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 33476 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 33476 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 79790 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 79790 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 79790 # number of overall hits
system.cpu.dcache.overall_hits::total 79790 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 212 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 212 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 287 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 287 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 287 # number of overall misses
system.cpu.dcache.overall_misses::total 287 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4725000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4725000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13356000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 13356000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18081000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18081000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18081000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18081000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 46389 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 46389 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 80077 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 80077 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 80077 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 80077 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001617 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001617 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006293 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006293 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.003584 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.003584 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.003584 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.003584 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 75 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 75 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 212 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 212 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4650000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4650000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13144000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13144000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17794000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 17794000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17794000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 17794000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001617 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001617 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006293 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006293 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003584 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003584 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 16 # number of replacements
system.cpu.icache.tags.tagsinuse 467.242122 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 200748 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 862 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 232.886311 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 467.242122 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.228146 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.228146 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 846 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 632 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.413086 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 404082 # Number of tag accesses
system.cpu.icache.tags.data_accesses 404082 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 200748 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 200748 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 200748 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 200748 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 200748 # number of overall hits
system.cpu.icache.overall_hits::total 200748 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 862 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 862 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 862 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 862 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 862 # number of overall misses
system.cpu.icache.overall_misses::total 862 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 54307500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 54307500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 54307500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 54307500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 54307500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 54307500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 201610 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 201610 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 201610 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 201610 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 201610 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 201610 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004276 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.004276 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.004276 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.004276 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.004276 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.004276 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63001.740139 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 63001.740139 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 63001.740139 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 63001.740139 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 16 # number of writebacks
system.cpu.icache.writebacks::total 16 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 862 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 862 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 862 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 862 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53445500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 53445500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53445500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 53445500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53445500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 53445500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004276 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.004276 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.004276 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62001.740139 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62001.740139 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 708.129693 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1149 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.013925 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 470.314864 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 237.814829 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014353 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007258 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.021610 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1149 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.035065 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 10469 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 10469 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 212 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 212 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 862 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 862 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 75 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 862 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 287 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1149 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 862 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 287 # number of overall misses
system.cpu.l2cache.overall_misses::total 1149 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12826000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12826000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52152000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 52152000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4537500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4537500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 52152000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 17363500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 69515500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 52152000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 17363500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 69515500 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 212 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 212 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 862 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 862 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 75 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 75 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 862 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 287 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1149 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 862 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 287 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1149 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.160093 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.160093 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60500.870322 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60500.870322 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 212 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 212 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 862 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 862 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 75 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 75 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1149 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1149 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10706000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10706000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43532000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43532000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3787500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3787500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43532000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14493500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 58025500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43532000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14493500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 58025500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.160093 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.160093 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1165 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 16 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 937 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 212 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 212 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 862 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 75 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1740 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 574 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2314 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56192 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 74560 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1149 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1149 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 598500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1293000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 430500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 1149 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 937 # Transaction distribution
system.membus.trans_dist::ReadExReq 212 # Transaction distribution
system.membus.trans_dist::ReadExResp 212 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 937 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2298 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2298 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 73536 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1149 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1149 # Request fanout histogram
system.membus.reqLayer0.occupancy 1150000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 5745000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
|