path: root/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000067                       # Number of seconds simulated
sim_ticks                                    66743000                       # Number of ticks simulated
final_tick                                   66743000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 234636                       # Simulator instruction rate (inst/s)
host_op_rate                                   234630                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              138224430                       # Simulator tick rate (ticks/s)
host_mem_usage                                 263644                       # Number of bytes of host memory used
host_seconds                                     0.48                       # Real time elapsed on the host
sim_insts                                      113291                       # Number of instructions simulated
sim_ops                                        113291                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             49408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             16960                       # Number of bytes read from this memory
system.physmem.bytes_read::total                66368                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        49408                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           49408                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                772                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                265                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  1037                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            740272388                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            254109045                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               994381433                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       740272388                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          740272388                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           740272388                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           254109045                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              994381433                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          1038                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        1038                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    66432                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     66432                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  89                       # Per bank write bursts
system.physmem.perBankRdBursts::1                   8                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  16                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 108                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  63                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  91                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  61                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  30                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  56                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  76                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 79                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 53                       # Per bank write bursts
system.physmem.perBankRdBursts::12                133                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 64                       # Per bank write bursts
system.physmem.perBankRdBursts::14                104                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  7                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        66724000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    1038                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       579                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       293                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        50                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          201                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      318.407960                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     195.437814                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     320.986499                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             66     32.84%     32.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           49     24.38%     57.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           28     13.93%     71.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           11      5.47%     76.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           11      5.47%     82.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            6      2.99%     85.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      1.49%     86.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            5      2.49%     89.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           22     10.95%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            201                       # Bytes accessed per row activation
system.physmem.totQLat                       13663500                       # Total ticks spent queuing
system.physmem.totMemAccLat                  33126000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      5190000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13163.29                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31913.29                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         995.34                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      995.34                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           7.78                       # Data bus utilization in percentage
system.physmem.busUtilRead                       7.78                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.68                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        824                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.38                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        64281.31                       # Average gap between requests
system.physmem.pageHitRate                      79.38                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     821100                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     406065                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   3327240                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           4917120.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy                6538470                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                 110400                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy          22321770                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy           1215840                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy                 39658005                       # Total energy per rank (pJ)
system.physmem_0.averagePower              594.183051                       # Core power per rank (mW)
system.physmem_0.totalIdleTime               51789750                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE          53500                       # Time in different power states
system.physmem_0.memoryStateTime::REF         2080000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN      3164000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        12517250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN     48928250                       # Time in different power states
system.physmem_1.actEnergy                     706860                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     356730                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   4084080                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           4917120.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy                6307620                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 140640                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy          21247890                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy           2284320                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy                 40045260                       # Total energy per rank (pJ)
system.physmem_1.averagePower              599.985167                       # Core power per rank (mW)
system.physmem_1.totalIdleTime               52550750                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE         144500                       # Time in different power states
system.physmem_1.memoryStateTime::REF         2080000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN      5948000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        11967750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN     46602750                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                   40127                       # Number of BP lookups
system.cpu.branchPred.condPredicted             25071                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect              2677                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                34324                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                   19560                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             56.986365                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups            7732                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits               3910                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             3822                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted         1192                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.numSyscalls                    45                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON        66743000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                           133487                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles              32821                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                         168943                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                       40127                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches              23470                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                         44129                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    5494                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  504                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles          156                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                     22264                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                  1272                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              80357                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.102406                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.833567                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    43897     54.63%     54.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                     3425      4.26%     58.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                     6099      7.59%     66.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                     5421      6.75%     73.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                     2445      3.04%     76.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                     6593      8.20%     84.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                     1925      2.40%     86.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                     1654      2.06%     88.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     8898     11.07%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                80357                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.300606                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.265614                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                    33044                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                 11875                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                     32363                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   936                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                   2139                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                19097                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   639                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                 154927                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                  1938                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                   2139                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                    34647                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                    3538                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           1406                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                     31612                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                  7015                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                 148450                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    21                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                      3                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                    267                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                   6512                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands              101534                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                195335                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups           195335                       # Number of integer rename lookups
system.cpu.rename.CommittedMaps                 76188                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                    25346                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 57                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             57                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                      3248                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                29003                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores               22614                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads               628                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores               17                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                     137191                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  60                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                    131006                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued               401                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined           23957                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined        13441                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             13                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         80357                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.630300                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.012996                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               38076     47.38%     47.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1               10267     12.78%     60.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                8067     10.04%     70.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                8077     10.05%     80.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                5915      7.36%     87.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                4760      5.92%     93.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                3768      4.69%     98.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                1110      1.38%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                 317      0.39%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           80357                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     179      6.20%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.20% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                   1370     47.45%     53.65% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                  1338     46.35%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite                0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                45      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                 81559     62.26%     62.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                  129      0.10%     62.39% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                    30      0.02%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                27992     21.37%     83.78% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite               21251     16.22%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite              0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                 131006                       # Type of FU issued
system.cpu.iq.rate                           0.981414                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                        2887                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.022037                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads             345657                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes            161246                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses       125018                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                 133848                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads             2541                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         5223                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           35                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores         2902                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            4                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           101                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                   2139                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                    2305                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                   218                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts              137249                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts               965                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                 29003                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                22614                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 58                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   224                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             35                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect            498                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect         1896                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                 2394                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                126750                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                 27173                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts              4256                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                        47912                       # number of memory reference insts executed
system.cpu.iew.exec_branches                    29064                       # Number of branches executed
system.cpu.iew.exec_stores                      20739                       # Number of stores executed
system.cpu.iew.exec_rate                     0.949531                       # Inst execution rate
system.cpu.iew.wb_sent                         125653                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                        125018                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                     49237                       # num instructions producing a value
system.cpu.iew.wb_consumers                     72853                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.936556                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.675840                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts           23968                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              45                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts              2069                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        75913                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.492379                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.297345                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        42174     55.56%     55.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1        10790     14.21%     69.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2         5413      7.13%     76.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3         4064      5.35%     82.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4         3292      4.34%     86.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5         3056      4.03%     90.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6         2525      3.33%     93.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7          907      1.19%     95.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8         3692      4.86%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        75913                       # Number of insts commited each cycle
system.cpu.commit.committedInsts               113291                       # Number of instructions committed
system.cpu.commit.committedOps                 113291                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                          43492                       # Number of memory references committed
system.cpu.commit.loads                         23780                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                      25920                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                    113291                       # Number of committed integer instructions.
system.cpu.commit.function_calls                 8529                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu            69651     61.48%     61.48% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult             122      0.11%     61.59% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv               26      0.02%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.61% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead           23780     20.99%     82.60% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite          19712     17.40%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total            113291                       # Class of committed instruction
system.cpu.commit.bw_lim_events                  3692                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                       208895                       # The number of ROB reads
system.cpu.rob.rob_writes                      279024                       # The number of ROB writes
system.cpu.timesIdled                             415                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           53130                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                      113291                       # Number of Instructions Simulated
system.cpu.committedOps                        113291                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.178267                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.178267                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.848704                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.848704                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                   166268                       # number of integer regfile reads
system.cpu.int_regfile_writes                   85929                       # number of integer regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse           217.985310                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs               42417                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               265                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            160.064151                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   217.985310                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.053219                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.053219                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          265                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.064697                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses             88517                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses            88517                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data        24171                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total           24171                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data        18246                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total          18246                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data         42417                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total            42417                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data        42417                       # number of overall hits
system.cpu.dcache.overall_hits::total           42417                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          243                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           243                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         1466                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         1466                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         1709                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           1709                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         1709                       # number of overall misses
system.cpu.dcache.overall_misses::total          1709                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     20232000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     20232000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     95961940                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     95961940                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    116193940                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    116193940                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    116193940                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    116193940                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data        24414                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total        24414                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data        19712                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total        19712                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data        44126                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total        44126                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data        44126                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total        44126                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009953                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.009953                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.074371                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.074371                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.038730                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.038730                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.038730                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.038730                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83259.259259                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 83259.259259                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65458.349250                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 65458.349250                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67989.432417                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67989.432417                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67989.432417                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67989.432417                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         5526                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                63                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    87.714286                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          173                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          173                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1269                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         1269                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         1442                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         1442                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         1442                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         1442                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           70                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data          197                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total          197                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          267                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          267                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6391500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      6391500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     15709000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     15709000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     22100500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     22100500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     22100500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     22100500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002867                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002867                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009994                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009994                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006051                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006051                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006051                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006051                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91307.142857                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91307.142857                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79741.116751                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79741.116751                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82773.408240                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 82773.408240                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82773.408240                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 82773.408240                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                16                       # number of replacements
system.cpu.icache.tags.tagsinuse           390.093191                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs               21217                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               773                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             27.447607                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   390.093191                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.190475                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.190475                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          757                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          678                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.369629                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses             45285                       # Number of tag accesses
system.cpu.icache.tags.data_accesses            45285                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst        21217                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total           21217                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst         21217                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total            21217                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst        21217                       # number of overall hits
system.cpu.icache.overall_hits::total           21217                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1039                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1039                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1039                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1039                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1039                       # number of overall misses
system.cpu.icache.overall_misses::total          1039                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     81350998                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     81350998                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     81350998                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     81350998                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     81350998                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     81350998                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst        22256                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total        22256                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst        22256                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total        22256                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst        22256                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total        22256                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.046684                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.046684                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.046684                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.046684                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.046684                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.046684                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78297.399423                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 78297.399423                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 78297.399423                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 78297.399423                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 78297.399423                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 78297.399423                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         2508                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                37                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    67.783784                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks           16                       # number of writebacks
system.cpu.icache.writebacks::total                16                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          266                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          266                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          266                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          266                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          266                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          266                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          773                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          773                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          773                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          773                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          773                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          773                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     65540000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     65540000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     65540000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     65540000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     65540000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     65540000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.034732                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.034732                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.034732                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.034732                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.034732                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.034732                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84786.545925                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84786.545925                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84786.545925                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 84786.545925                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84786.545925                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 84786.545925                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          612.540827                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                 16                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             1037                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.015429                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   394.513827                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   218.027000                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.012040                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.006654                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.018693                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         1037                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          950                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.031647                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             9477                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            9477                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks           16                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total           16                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_misses::cpu.data          197                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          197                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          772                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          772                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data           70                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total           70                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          772                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          267                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          1039                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          772                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          267                       # number of overall misses
system.cpu.l2cache.overall_misses::total         1039                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     15413500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     15413500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     64376500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     64376500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      6288000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total      6288000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     64376500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     21701500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     86078000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     64376500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     21701500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     86078000                       # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks           16                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total           16                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data          197                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total          197                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          772                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          772                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           70                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total           70                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          772                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          267                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         1039                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          772                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          267                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         1039                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78241.116751                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78241.116751                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83389.248705                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83389.248705                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89828.571429                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89828.571429                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83389.248705                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81279.026217                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82846.968239                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83389.248705                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81279.026217                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82846.968239                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          197                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          197                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          772                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          772                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           70                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total           70                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          772                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          267                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         1039                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          772                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          267                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         1039                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     13443500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     13443500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     56656500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     56656500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5608000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      5608000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     56656500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     19051500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     75708000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     56656500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     19051500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     75708000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68241.116751                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68241.116751                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73389.248705                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73389.248705                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80114.285714                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80114.285714                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73389.248705                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71353.932584                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72866.217517                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73389.248705                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71353.932584                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72866.217517                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests         1056                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests           17                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp           841                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean           16                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq          197                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp          197                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          773                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq           70                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1561                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          532                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total              2093                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        50432                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        16960                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              67392                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           1                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                    64                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples         1040                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.000962                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.031009                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0               1039     99.90%     99.90% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  1      0.10%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total           1040                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         544000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1159500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.7                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        397500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests          1038                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED     66743000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                840                       # Transaction distribution
system.membus.trans_dist::ReadExReq               197                       # Transaction distribution
system.membus.trans_dist::ReadExResp              197                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           841                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         2075                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   2075                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        66368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   66368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples              1038                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    1038    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                1038                       # Request fanout histogram
system.membus.reqLayer0.occupancy             1251500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
system.membus.respLayer1.occupancy            5471250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              8.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------