summaryrefslogtreecommitdiff
path: root/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
blob: 3353b4aadf5c126dc9ab55f78428a2c9df62968e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000023                       # Number of seconds simulated
sim_ticks                                    22838500                       # Number of ticks simulated
final_tick                                   22838500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  21741                       # Simulator instruction rate (inst/s)
host_op_rate                                    21740                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               32746771                       # Simulator tick rate (ticks/s)
host_mem_usage                                 278448                       # Number of bytes of host memory used
host_seconds                                     0.70                       # Real time elapsed on the host
sim_insts                                       15162                       # Number of instructions simulated
sim_ops                                         15162                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             19072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                27904                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        19072                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           19072                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                298                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   436                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            835081113                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            386715415                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1221796528                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       835081113                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          835081113                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           835081113                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           386715415                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1221796528                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           436                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                            436                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                        27904                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                  27904                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                    69                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                    32                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                    25                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                     4                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                     5                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                    34                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                     3                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                    17                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                    37                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                    27                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                   31                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                   11                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                   76                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                   43                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                   22                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                        22805000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                     436                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                      0                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                       279                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                        2325934                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                  11335934                       # Sum of mem lat for all requests
system.physmem.totBusLat                      1744000                       # Total cycles spent in databus access
system.physmem.totBankLat                     7266000                       # Total cycles spent in bank access
system.physmem.avgQLat                        5334.71                       # Average queueing delay per request
system.physmem.avgBankLat                    16665.14                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  25999.85                       # Average memory access latency
system.physmem.avgRdBW                        1221.80                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                1221.80                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           7.64                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.50                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                        359                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.34                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        52305.05                       # Average gap between requests
system.cpu.branchPred.lookups                    5147                       # Number of BP lookups
system.cpu.branchPred.condPredicted              3529                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect              2366                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 4101                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                    2720                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             66.325287                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     174                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  5                       # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls                   18                       # Number of system calls
system.cpu.numCycles                            45678                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken         2894                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken         2253                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads        14397                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites        11099                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses        25496                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads            0                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites            0                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses            0                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards           5052                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                       3844                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect         1541                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect          762                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted           2303                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted              1055                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     68.582490                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions            11045                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.threadCycles                         21903                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                             502                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           28109                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                            17569                       # Number of cycles cpu stages are processed.
system.cpu.activity                         38.462717                       # Percentage of cycles cpu is active
system.cpu.comLoads                              2225                       # Number of Load instructions committed
system.cpu.comStores                             1448                       # Number of Store instructions committed
system.cpu.comBranches                           3358                       # Number of Branches instructions committed
system.cpu.comNops                                726                       # Number of Nop instructions committed
system.cpu.comNonSpec                             222                       # Number of Non-Speculative instructions committed
system.cpu.comInts                               7166                       # Number of Integer instructions committed
system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
system.cpu.committedInsts                       15162                       # Number of Instructions committed (Per-Thread)
system.cpu.committedOps                         15162                       # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total                 15162                       # Number of Instructions committed (Total)
system.cpu.cpi                               3.012663                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
system.cpu.cpi_total                         3.012663                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.331932                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         0.331932                       # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles                    32252                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                     13426                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization               29.392705                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles                    36324                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                      9354                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization               20.478130                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles                    36874                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                      8804                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization               19.274049                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles                    42800                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                      2878                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization                6.300626                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                    36369                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                      9309                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization               20.379614                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.tagsinuse                172.574474                       # Cycle average of tags in use
system.cpu.icache.total_refs                     3004                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    299                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  10.046823                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     172.574474                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.084265                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.084265                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst         3004                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            3004                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          3004                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             3004                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         3004                       # number of overall hits
system.cpu.icache.overall_hits::total            3004                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          381                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           381                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          381                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            381                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          381                       # number of overall misses
system.cpu.icache.overall_misses::total           381                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     18868500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     18868500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     18868500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     18868500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     18868500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     18868500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         3385                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         3385                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         3385                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         3385                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         3385                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         3385                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.112555                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.112555                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.112555                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.112555                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.112555                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.112555                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49523.622047                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49523.622047                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49523.622047                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49523.622047                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49523.622047                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49523.622047                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           80                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           80                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           80                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           80                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          301                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          301                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          301                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15157500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     15157500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15157500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     15157500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15157500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     15157500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.088922                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.088922                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.088922                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50357.142857                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50357.142857                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50357.142857                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50357.142857                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50357.142857                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50357.142857                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse               204.083022                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                   351                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.005698                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst    171.933146                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data     32.149876                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst     0.005247                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.000981                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.006228                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          299                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          352                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           85                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           85                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          299                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           437                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          299                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
system.cpu.l2cache.overall_misses::total          437                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14874500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2846000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     17720500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4426000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      4426000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     14874500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      7272000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     22146500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     14874500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      7272000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     22146500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          301                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          354                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           85                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           85                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          301                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          439                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          301                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          439                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993355                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.994350                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993355                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.995444                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993355                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.995444                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49747.491639                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53698.113208                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 50342.329545                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52070.588235                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52070.588235                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49747.491639                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52695.652174                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 50678.489703                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49747.491639                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52695.652174                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 50678.489703                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          299                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          352                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          299                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          437                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          299                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          437                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11105481                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2181568                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13287049                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3382064                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3382064                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11105481                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5563632                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     16669113                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11105481                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5563632                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     16669113                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994350                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.995444                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.995444                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37142.076923                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37747.298295                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37142.076923                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38144.423341                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37142.076923                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38144.423341                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.tagsinuse                 99.519804                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     3193                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  23.137681                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data      99.519804                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.024297                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.024297                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data         2167                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            2167                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data         1020                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total           1020                       # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data          3187                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             3187                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         3187                       # number of overall hits
system.cpu.dcache.overall_hits::total            3187                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           58                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            58                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          422                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          422                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          480                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            480                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          480                       # number of overall misses
system.cpu.dcache.overall_misses::total           480                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      3301000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      3301000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     19263500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     19263500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     22564500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     22564500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     22564500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     22564500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         3667                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         3667                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         3667                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         3667                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026067                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.026067                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292649                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.292649                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.130897                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.130897                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.130897                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.130897                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56913.793103                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56913.793103                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45648.104265                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45648.104265                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47009.375000                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 47009.375000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47009.375000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 47009.375000                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          680                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                34                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           20                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          337                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          337                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          342                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          342                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          342                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          342                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           85                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2900500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      2900500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4514000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      4514000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7414500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      7414500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7414500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      7414500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.058946                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54726.415094                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54726.415094                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53105.882353                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53105.882353                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53728.260870                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53728.260870                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53728.260870                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53728.260870                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------