summaryrefslogtreecommitdiff
path: root/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
blob: c7e6fdca455a2f7f7279def8a0aedd31aba1cdbf (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Jan  4 2013 21:16:54
gem5 started Jan  4 2013 21:59:36
gem5 executing on u200540
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0.  Starting simulation...
Begining test of difficult SPARC instructions...
LDSTUB:		Passed
SWAP:		Passed
CAS FAIL:	Passed
CAS WORK:	Passed
CASX FAIL:	Passed
CASX WORK:	Passed
LDTX:		Passed
LDTW:		Passed
STTW:		Passed
Done
Exiting @ tick 23180500 because target called exit()