path: root/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000020                       # Number of seconds simulated
sim_ticks                                    19778500                       # Number of ticks simulated
final_tick                                   19778500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  52882                       # Simulator instruction rate (inst/s)
host_op_rate                                    52877                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               72439157                       # Simulator tick rate (ticks/s)
host_mem_usage                                 223656                       # Number of bytes of host memory used
host_seconds                                     0.27                       # Real time elapsed on the host
sim_insts                                       14436                       # Number of instructions simulated
sim_ops                                         14436                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             21568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              9344                       # Number of bytes read from this memory
system.physmem.bytes_read::total                30912                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        21568                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           21568                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                337                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                146                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   483                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst           1090477033                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            472432186                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1562909220                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      1090477033                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         1090477033                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          1090477033                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           472432186                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1562909220                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           483                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                            483                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                        30912                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                  30912                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                    70                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                    36                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                    24                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                     6                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                     8                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                    44                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                     3                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                    21                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                    43                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                    32                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                   31                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                    0                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                   13                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                   80                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                   46                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                   26                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                        19726000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                     483                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                      0                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                       271                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       137                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                        3361480                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                  13231480                       # Sum of mem lat for all requests
system.physmem.totBusLat                      1932000                       # Total cycles spent in databus access
system.physmem.totBankLat                     7938000                       # Total cycles spent in bank access
system.physmem.avgQLat                        6959.59                       # Average queueing delay per request
system.physmem.avgBankLat                    16434.78                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  27394.37                       # Average memory access latency
system.physmem.avgRdBW                        1562.91                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                1562.91                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           9.77                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.67                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                        394                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.57                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        40840.58                       # Average gap between requests
system.cpu.workload.num_syscalls                   18                       # Number of system calls
system.cpu.numCycles                            39558                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                     6961                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted               4635                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect               1124                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups                  5126                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                     2626                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                      443                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                 168                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles              11957                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          32537                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        6961                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches               3069                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          9617                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    3192                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles                   7429                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           834                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                      5561                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   468                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              31813                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.022758                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.197280                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    22196     69.77%     69.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                     4753     14.94%     84.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      498      1.57%     86.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      475      1.49%     87.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      708      2.23%     89.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      718      2.26%     92.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      247      0.78%     93.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      285      0.90%     93.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     1933      6.08%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                31813                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.175969                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.822514                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                    12679                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  8183                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      8793                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   186                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                   1972                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts                  30371                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                   1972                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                    13365                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                     199                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           7520                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      8338                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                   419                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  27570                       # Number of instructions processed by rename
system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents                   112                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands               24556                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 51144                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            51144                       # Number of integer rename lookups
system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                    10737                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                696                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            697                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                      2824                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 3648                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                2459                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      23227                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 659                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                     21740                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued               113                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined            8509                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined         6060                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            184                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         31813                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.683368                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.298612                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               22340     70.22%     70.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                3583     11.26%     81.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                2473      7.77%     89.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                1697      5.33%     94.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 903      2.84%     97.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 492      1.55%     98.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 244      0.77%     99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                  64      0.20%     99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  17      0.05%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           31813                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                      50     28.09%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.09% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                     26     14.61%     42.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                   102     57.30%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                 16052     73.84%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.84% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 3424     15.75%     89.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                2264     10.41%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  21740                       # Type of FU issued
system.cpu.iq.rate                           0.549573                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                         178                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.008188                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              75584                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             32421                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses        19938                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                  21918                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads               26                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1423                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           27                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores         1011                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                   1972                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                     103                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                     4                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               25068                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts               512                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  3648                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 2459                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                659                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             27                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect            296                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          961                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                 1257                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                 20524                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  3260                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts              1216                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          1182                       # number of nop insts executed
system.cpu.iew.exec_refs                         5396                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     4297                       # Number of branches executed
system.cpu.iew.exec_stores                       2136                       # Number of stores executed
system.cpu.iew.exec_rate                     0.518833                       # Inst execution rate
system.cpu.iew.wb_sent                          20197                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                         19938                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                      9248                       # num instructions producing a value
system.cpu.iew.wb_consumers                     11357                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.504019                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.814300                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts            9816                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts              1124                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        29858                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.507804                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.195478                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        22523     75.43%     75.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         3989     13.36%     88.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2         1473      4.93%     93.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          787      2.64%     96.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          343      1.15%     97.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          245      0.82%     98.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          323      1.08%     99.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           69      0.23%     99.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          106      0.36%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        29858                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                15162                       # Number of instructions committed
system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           3673                       # Number of memory references committed
system.cpu.commit.loads                          2225                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                       3358                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                     12174                       # Number of committed integer instructions.
system.cpu.commit.function_calls                  187                       # Number of function calls committed.
system.cpu.commit.bw_lim_events                   106                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                        53907                       # The number of ROB reads
system.cpu.rob.rob_writes                       51935                       # The number of ROB writes
system.cpu.timesIdled                             182                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                            7745                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total                 14436                       # Number of Instructions Simulated
system.cpu.cpi                               2.740233                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.740233                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.364933                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.364933                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    32646                       # number of integer regfile reads
system.cpu.int_regfile_writes                   18155                       # number of integer regfile writes
system.cpu.misc_regfile_reads                    7050                       # number of misc regfile reads
system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.tagsinuse                200.987114                       # Cycle average of tags in use
system.cpu.icache.total_refs                     5096                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    339                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  15.032448                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     200.987114                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.098138                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.098138                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst         5096                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            5096                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          5096                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             5096                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         5096                       # number of overall hits
system.cpu.icache.overall_hits::total            5096                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          465                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           465                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          465                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            465                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          465                       # number of overall misses
system.cpu.icache.overall_misses::total           465                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     14626000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     14626000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     14626000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     14626000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     14626000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     14626000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         5561                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         5561                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         5561                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         5561                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         5561                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         5561                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.083618                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.083618                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.083618                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.083618                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.083618                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.083618                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31453.763441                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 31453.763441                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 31453.763441                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 31453.763441                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 31453.763441                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 31453.763441                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          126                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          126                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          126                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          126                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          126                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          126                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          339                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          339                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          339                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          339                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          339                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          339                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11056500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     11056500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11056500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     11056500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11056500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     11056500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.060960                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.060960                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.060960                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.060960                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.060960                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.060960                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32615.044248                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32615.044248                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32615.044248                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 32615.044248                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32615.044248                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 32615.044248                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.tagsinuse                102.726852                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     4058                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                    146                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  27.794521                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     102.726852                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.025080                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.025080                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data         3017                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            3017                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data         1035                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total           1035                       # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data          4052                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             4052                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         4052                       # number of overall hits
system.cpu.dcache.overall_hits::total            4052                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          128                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           128                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          407                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          407                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          535                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            535                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          535                       # number of overall misses
system.cpu.dcache.overall_misses::total           535                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      5512500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      5512500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     14390000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     14390000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     19902500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     19902500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     19902500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     19902500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         3145                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         3145                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         4587                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         4587                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         4587                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         4587                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040700                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.040700                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.282247                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.282247                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.116634                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.116634                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.116634                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.116634                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43066.406250                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 43066.406250                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35356.265356                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35356.265356                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37200.934579                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37200.934579                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37200.934579                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 37200.934579                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           65                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           65                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          324                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          324                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          389                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          389                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          389                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          389                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           63                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           63                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           83                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           83                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3018500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      3018500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3172000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      3172000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6190500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      6190500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6190500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      6190500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020032                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020032                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031829                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.031829                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031829                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.031829                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47912.698413                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47912.698413                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38216.867470                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38216.867470                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42400.684932                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 42400.684932                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42400.684932                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 42400.684932                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse               236.256243                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                   400                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.005000                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst    200.252174                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data     36.004069                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst     0.006111                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.001099                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.007210                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          337                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           63                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          400                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           83                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           83                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          337                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          146                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           483                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          337                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          146                       # number of overall misses
system.cpu.l2cache.overall_misses::total          483                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10715500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2955000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     13670500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3088000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      3088000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     10715500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      6043000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     16758500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     10715500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      6043000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     16758500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          339                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           63                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          402                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           83                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           83                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          339                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          146                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          485                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          339                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          146                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          485                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.994100                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.995025                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994100                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.995876                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994100                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.995876                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31796.735905                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 46904.761905                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34176.250000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37204.819277                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37204.819277                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31796.735905                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41390.410959                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34696.687371                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31796.735905                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41390.410959                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34696.687371                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          337                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           63                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          400                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           83                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           83                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          337                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          483                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          337                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          483                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9509513                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2743056                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12252569                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2822546                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2822546                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9509513                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5565602                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     15075115                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9509513                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5565602                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     15075115                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.994100                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995025                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994100                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.995876                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994100                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.995876                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28218.139466                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43540.571429                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30631.422500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34006.578313                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34006.578313                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28218.139466                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38120.561644                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.418219                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28218.139466                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38120.561644                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.418219                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------