blob: eba0d27828f8cb0974c14cb787c535fecf3d6163 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000027 # Number of seconds simulated
sim_ticks 27482500 # Number of ticks simulated
final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 15220 # Simulator instruction rate (inst/s)
host_op_rate 15220 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28973949 # Simulator tick rate (ticks/s)
host_mem_usage 223564 # Number of bytes of host memory used
host_seconds 0.95 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory
system.physmem.bytes_read::total 31488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22016 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory
system.physmem.num_reads::total 492 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 801091604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 344655690 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1145747294 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 801091604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 801091604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 801091604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 344655690 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1145747294 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 492 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 107 # Per bank write bursts
system.physmem.perBankRdBursts::1 28 # Per bank write bursts
system.physmem.perBankRdBursts::2 51 # Per bank write bursts
system.physmem.perBankRdBursts::3 24 # Per bank write bursts
system.physmem.perBankRdBursts::4 20 # Per bank write bursts
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
system.physmem.perBankRdBursts::7 35 # Per bank write bursts
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
system.physmem.perBankRdBursts::9 2 # Per bank write bursts
system.physmem.perBankRdBursts::10 1 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdBursts::12 57 # Per bank write bursts
system.physmem.perBankRdBursts::13 31 # Per bank write bursts
system.physmem.perBankRdBursts::14 61 # Per bank write bursts
system.physmem.perBankRdBursts::15 39 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 27431000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 492 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 404.732394 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 270.110571 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 339.824701 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 13 18.31% 18.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18 25.35% 43.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9 12.68% 56.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7 9.86% 66.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 7 9.86% 76.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1 1.41% 77.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4 5.63% 83.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 2.82% 85.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 14.08% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation
system.physmem.totQLat 3613750 # Total ticks spent queuing
system.physmem.totMemAccLat 12838750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7345.02 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26095.02 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1145.75 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1145.75 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 8.95 # Data bus utilization in percentage
system.physmem.busUtilRead 8.95 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 412 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 55754.07 # Average gap between requests
system.physmem.pageHitRate 83.74 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2059200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 15743115 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 361500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 20156895 # Total energy per rank (pJ)
system.physmem_0.averagePower 853.427679 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 520250 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 22332250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 15564420 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 518250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 19277100 # Total energy per rank (pJ)
system.physmem_1.averagePower 816.177825 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2637000 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 22058500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 8538 # Number of BP lookups
system.cpu.branchPred.condPredicted 5461 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1059 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 5976 # Number of BTB lookups
system.cpu.branchPred.BTBHits 3053 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 51.087684 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 609 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 54966 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 14246 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 40057 # Number of instructions fetch has processed
system.cpu.fetch.Branches 8538 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 3662 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 15957 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 6438 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 32422 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.235488 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.378208 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 20898 64.46% 64.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 5494 16.95% 81.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 685 2.11% 83.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 505 1.56% 85.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 819 2.53% 87.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 909 2.80% 90.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 334 1.03% 91.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 371 1.14% 92.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2407 7.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 32422 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.155332 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.728760 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 11347 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12433 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 6847 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 640 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 30502 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 11955 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1146 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 9859 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 6898 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1409 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 27684 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
system.cpu.rename.SQFullEvents 1012 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 25054 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 51692 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 42838 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 11235 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 767 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 3842 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3673 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 23655 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 9945 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 6501 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 32422 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.676208 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.425800 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 24009 74.05% 74.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3087 9.52% 83.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1572 4.85% 88.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1483 4.57% 93.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 954 2.94% 95.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 709 2.19% 98.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 413 1.27% 99.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 155 0.48% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 40 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 32422 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 111 49.33% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 49 21.78% 71.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 65 28.89% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 16300 74.35% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 3501 15.97% 90.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 21924 # Type of FU issued
system.cpu.iq.rate 0.398865 # Inst issue rate
system.cpu.iq.fu_busy_cnt 225 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010263 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 76549 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 34352 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 22149 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1147 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 25507 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 203 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3673 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1194 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 20914 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3347 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1126 # number of nop insts executed
system.cpu.iew.exec_refs 5371 # number of memory reference insts executed
system.cpu.iew.exec_branches 4427 # Number of branches executed
system.cpu.iew.exec_stores 2024 # Number of stores executed
system.cpu.iew.exec_rate 0.380490 # Inst execution rate
system.cpu.iew.wb_sent 20501 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 20244 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9848 # num instructions producing a value
system.cpu.iew.wb_consumers 12670 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.368300 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.777269 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 10287 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1059 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 30361 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.499391 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.308685 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 23816 78.44% 78.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 3429 11.29% 89.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1193 3.93% 93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 637 2.10% 95.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 331 1.09% 96.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 224 0.74% 97.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 397 1.31% 98.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 272 0.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 30361 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3673 # Number of memory references committed
system.cpu.commit.loads 2225 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 3358 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 54715 # The number of ROB reads
system.cpu.rob.rob_writes 52974 # The number of ROB writes
system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads
system.cpu.ipc 0.262635 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.262635 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 33408 # number of integer regfile reads
system.cpu.int_regfile_writes 18606 # number of integer regfile writes
system.cpu.misc_regfile_reads 7133 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 98.556611 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4125 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 28.061224 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 98.556611 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.024062 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.024062 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 9489 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 9489 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 3086 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3086 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 4119 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4119 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4119 # number of overall hits
system.cpu.dcache.overall_hits::total 4119 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 137 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 137 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 546 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 546 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 546 # number of overall misses
system.cpu.dcache.overall_misses::total 546 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9397000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9397000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 27538481 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 27538481 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 36935481 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 36935481 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 36935481 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 36935481 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3223 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3223 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 4665 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 4665 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 4665 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 4665 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042507 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.042507 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.117042 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.117042 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.117042 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117042 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68591.240876 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 68591.240876 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67331.249389 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 67331.249389 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67647.401099 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67647.401099 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1052 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.818182 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 398 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 398 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 398 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 398 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5143250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5143250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6389250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6389250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11532500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11532500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11532500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11532500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020168 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020168 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.031726 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031726 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79126.923077 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79126.923077 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76978.915663 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76978.915663 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 190.975563 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5904 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 17.063584 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 190.975563 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.093250 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.093250 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13222 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13222 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5904 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5904 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5904 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5904 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5904 # number of overall hits
system.cpu.icache.overall_hits::total 5904 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 534 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 534 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 534 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 534 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 534 # number of overall misses
system.cpu.icache.overall_misses::total 534 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 37367000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 37367000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 37367000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 37367000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 37367000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 37367000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6438 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6438 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6438 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6438 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6438 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6438 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082945 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.082945 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.082945 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.082945 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.082945 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.082945 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69975.655431 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 69975.655431 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 69975.655431 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 69975.655431 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 188 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 188 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 188 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 188 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 188 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 188 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26526250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 26526250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26526250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 26526250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26526250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 26526250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053743 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.053743 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.053743 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76665.462428 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76665.462428 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 224.896195 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 190.368376 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.527819 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005810 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001054 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006863 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 409 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
system.cpu.l2cache.overall_misses::total 492 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26158750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5078750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 31237500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6304750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6304750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 26158750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11383500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 37542250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 26158750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11383500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 37542250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 346 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 494 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 346 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 494 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994220 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.995134 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76042.877907 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78134.615385 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76375.305623 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75960.843373 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75960.843373 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76305.386179 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76305.386179 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 409 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21861250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4272750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26134000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5278250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5278250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21861250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 31412250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21861250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 31412250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63550.145349 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65734.615385 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63897.310513 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63593.373494 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63593.373494 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 245000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.membus.trans_dist::ReadReq 409 # Transaction distribution
system.membus.trans_dist::ReadResp 408 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 492 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 492 # Request fanout histogram
system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 2599750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 9.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
|