blob: 52156950fe2710e5417c52f65e108cc5da369ef5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
sim_ticks 19806500 # Number of ticks simulated
final_tick 19806500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 96556 # Simulator instruction rate (inst/s)
host_op_rate 96545 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 132327745 # Simulator tick rate (ticks/s)
host_mem_usage 221008 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
sim_insts 14449 # Number of instructions simulated
sim_ops 14449 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
system.physmem.bytes_read::total 30976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
system.physmem.num_reads::total 484 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1092166713 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 471764320 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1563931033 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1092166713 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1092166713 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1092166713 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 471764320 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1563931033 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 39614 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 6890 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 4576 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 5201 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2595 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 459 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 11869 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 32300 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6890 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 3054 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9560 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3188 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 6935 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 5516 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 31065 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.039755 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.210803 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21505 69.23% 69.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4746 15.28% 84.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 494 1.59% 86.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 444 1.43% 87.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 682 2.20% 89.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 763 2.46% 92.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 240 0.77% 92.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 277 0.89% 93.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1914 6.16% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 31065 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.173928 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.815368 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12513 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 7669 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 8722 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1971 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 30088 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1971 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13189 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6922 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 8283 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 452 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 27408 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 125 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 24445 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 50953 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 50953 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 10613 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 705 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2841 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3647 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2469 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 23180 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 670 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 21761 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8457 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 5919 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 195 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 31065 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.700499 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.316624 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 21619 69.59% 69.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3603 11.60% 81.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 2384 7.67% 88.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1730 5.57% 94.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 898 2.89% 97.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 488 1.57% 98.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 252 0.81% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 72 0.23% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 31065 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 54 29.19% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.19% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 26 14.05% 43.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 105 56.76% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 16056 73.78% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.78% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 3441 15.81% 89.60% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2264 10.40% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 21761 # Type of FU issued
system.cpu.iq.rate 0.549326 # Inst issue rate
system.cpu.iq.fu_busy_cnt 185 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008501 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 74877 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 32333 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19979 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 21946 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1421 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1021 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 25018 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 406 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3647 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2469 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 670 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 291 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1253 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 20571 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1168 # number of nop insts executed
system.cpu.iew.exec_refs 5421 # number of memory reference insts executed
system.cpu.iew.exec_branches 4301 # Number of branches executed
system.cpu.iew.exec_stores 2143 # Number of stores executed
system.cpu.iew.exec_rate 0.519286 # Inst execution rate
system.cpu.iew.wb_sent 20246 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 19979 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9281 # num instructions producing a value
system.cpu.iew.wb_consumers 11411 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.504342 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.813338 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 9761 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 29111 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.521281 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.203804 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 21721 74.61% 74.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4069 13.98% 88.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1444 4.96% 93.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 793 2.72% 96.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 337 1.16% 97.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 258 0.89% 98.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 320 1.10% 99.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 71 0.24% 99.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 98 0.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 29111 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15175 # Number of instructions committed
system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3674 # Number of memory references committed
system.cpu.commit.loads 2226 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 3359 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 53126 # The number of ROB reads
system.cpu.rob.rob_writes 51851 # The number of ROB writes
system.cpu.timesIdled 186 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8549 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
system.cpu.cpi 2.741643 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.741643 # CPI: Total CPI of All Threads
system.cpu.ipc 0.364745 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.364745 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 32757 # number of integer regfile reads
system.cpu.int_regfile_writes 18209 # number of integer regfile writes
system.cpu.misc_regfile_reads 7073 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 201.055469 # Cycle average of tags in use
system.cpu.icache.total_refs 5034 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14.805882 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 201.055469 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.098172 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.098172 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 5034 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5034 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5034 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5034 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5034 # number of overall hits
system.cpu.icache.overall_hits::total 5034 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 482 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 482 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 482 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 482 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 482 # number of overall misses
system.cpu.icache.overall_misses::total 482 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16634500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16634500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16634500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16634500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16634500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16634500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5516 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5516 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5516 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5516 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5516 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5516 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087382 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.087382 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.087382 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.087382 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.087382 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.087382 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34511.410788 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34511.410788 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34511.410788 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34511.410788 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 142 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 142 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 142 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 142 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 142 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11937500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11937500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061639 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.061639 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.061639 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 103.574586 # Cycle average of tags in use
system.cpu.dcache.total_refs 4084 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27.972603 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 103.574586 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025287 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025287 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 3044 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3044 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 4078 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4078 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4078 # number of overall hits
system.cpu.dcache.overall_hits::total 4078 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 524 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 524 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 524 # number of overall misses
system.cpu.dcache.overall_misses::total 524 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4022000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4022000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14592500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14592500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18614500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18614500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18614500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18614500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3160 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3160 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 4602 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 4602 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 4602 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 4602 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.036709 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.036709 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.113864 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.113864 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.113864 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.113864 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34672.413793 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34672.413793 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35765.931373 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35765.931373 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 35523.854962 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35523.854962 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 378 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 378 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2978500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2978500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5222000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5222000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5222000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5222000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019937 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019937 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.031725 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031725 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35885.542169 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35885.542169 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 236.586962 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 200.308921 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 36.278041 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.006113 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001107 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.007220 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses
system.cpu.l2cache.overall_misses::total 484 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11581500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2169000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 13750500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2869000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2869000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 11581500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 5038000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 16619500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 11581500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 5038000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 16619500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 340 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994118 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.995037 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994118 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.995885 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34264.792899 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34290.523691 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34337.809917 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34337.809917 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10495000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1969500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12464500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2607500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2607500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10495000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15072000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10495000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15072000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050.295858 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31261.904762 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.541147 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050.295858 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31140.495868 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050.295858 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31140.495868 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|