path: root/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000729                       # Number of seconds simulated
sim_ticks                                   728920000                       # Number of ticks simulated
final_tick                                  728920000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1560894                       # Simulator instruction rate (inst/s)
host_op_rate                                  1560871                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              568880584                       # Simulator tick rate (ticks/s)
host_mem_usage                                 223172                       # Number of bytes of host memory used
host_seconds                                     1.28                       # Real time elapsed on the host
sim_insts                                     1999954                       # Number of instructions simulated
sim_ops                                       1999954                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                      219392                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                 103168                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                        0                       # Number of bytes written to this memory
system.physmem.num_reads                         3428                       # Number of read requests responded to by this memory
system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                      300982275                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                 141535422                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total                     300982275                       # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                      124435                       # DTB read hits
system.cpu0.dtb.read_misses                         8                       # DTB read misses
system.cpu0.dtb.read_acv                            0                       # DTB read access violations
system.cpu0.dtb.read_accesses                  124443                       # DTB read accesses
system.cpu0.dtb.write_hits                      56340                       # DTB write hits
system.cpu0.dtb.write_misses                       10                       # DTB write misses
system.cpu0.dtb.write_acv                           0                       # DTB write access violations
system.cpu0.dtb.write_accesses                  56350                       # DTB write accesses
system.cpu0.dtb.data_hits                      180775                       # DTB hits
system.cpu0.dtb.data_misses                        18                       # DTB misses
system.cpu0.dtb.data_acv                            0                       # DTB access violations
system.cpu0.dtb.data_accesses                  180793                       # DTB accesses
system.cpu0.itb.fetch_hits                     500020                       # ITB hits
system.cpu0.itb.fetch_misses                       13                       # ITB misses
system.cpu0.itb.fetch_acv                           0                       # ITB acv
system.cpu0.itb.fetch_accesses                 500033                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.workload.num_syscalls                  18                       # Number of system calls
system.cpu0.numCycles                         1457840                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                     500001                       # Number of instructions committed
system.cpu0.committedOps                       500001                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                      474689                       # number of integer instructions
system.cpu0.num_fp_insts                           32                       # number of float instructions
system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
system.cpu0.num_mem_refs                       180793                       # number of memory refs
system.cpu0.num_load_insts                     124443                       # Number of load instructions
system.cpu0.num_store_insts                     56350                       # Number of store instructions
system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
system.cpu0.num_busy_cycles                   1457840                       # Number of busy cycles
system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
system.cpu0.icache.replacements                   152                       # number of replacements
system.cpu0.icache.tagsinuse               216.390931                       # Cycle average of tags in use
system.cpu0.icache.total_refs                  499557                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs               1078.956803                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   216.390931                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.422639                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.422639                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst       499557                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total         499557                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst       499557                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total          499557                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst       499557                       # number of overall hits
system.cpu0.icache.overall_hits::total         499557                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          463                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          463                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          463                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           463                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          463                       # number of overall misses
system.cpu0.icache.overall_misses::total          463                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     23474000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     23474000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     23474000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     23474000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     23474000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     23474000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst       500020                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total       500020                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst       500020                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total       500020                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst       500020                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total       500020                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.000926                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.000926                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.000926                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50699.784017                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50699.784017                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50699.784017                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          463                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          463                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          463                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     22085000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     22085000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     22085000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     22085000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     22085000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     22085000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.000926                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47699.784017                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47699.784017                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47699.784017                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                    61                       # number of replacements
system.cpu0.dcache.tagsinuse               273.518805                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  180312                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                389.442765                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   273.518805                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.534216                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.534216                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         56201                       # number of WriteReq hits
system.cpu0.dcache.demand_hits::cpu0.data       180312                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          180312                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       180312                       # number of overall hits
system.cpu0.dcache.overall_hits::total         180312                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          324                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          139                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
system.cpu0.dcache.demand_misses::cpu0.data          463                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total           463                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data          463                       # number of overall misses
system.cpu0.dcache.overall_misses::total          463                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     17785000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     17785000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7793000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total      7793000                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     25578000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     25578000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     25578000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     25578000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data       124435                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        56340                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        56340                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       180775                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       180775                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       180775                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       180775                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002604                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.002467                       # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.002561                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.002561                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 54891.975309                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 56064.748201                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 55244.060475                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 55244.060475                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks           29                       # number of writebacks
system.cpu0.dcache.writebacks::total               29                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          324                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          139                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          463                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          463                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data     16813000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total     16813000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7376000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7376000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     24189000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     24189000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     24189000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     24189000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002604                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002467                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002561                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51891.975309                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53064.748201                       # average WriteReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52244.060475                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52244.060475                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                      124435                       # DTB read hits
system.cpu1.dtb.read_misses                         8                       # DTB read misses
system.cpu1.dtb.read_acv                            0                       # DTB read access violations
system.cpu1.dtb.read_accesses                  124443                       # DTB read accesses
system.cpu1.dtb.write_hits                      56339                       # DTB write hits
system.cpu1.dtb.write_misses                       10                       # DTB write misses
system.cpu1.dtb.write_acv                           0                       # DTB write access violations
system.cpu1.dtb.write_accesses                  56349                       # DTB write accesses
system.cpu1.dtb.data_hits                      180774                       # DTB hits
system.cpu1.dtb.data_misses                        18                       # DTB misses
system.cpu1.dtb.data_acv                            0                       # DTB access violations
system.cpu1.dtb.data_accesses                  180792                       # DTB accesses
system.cpu1.itb.fetch_hits                     500012                       # ITB hits
system.cpu1.itb.fetch_misses                       13                       # ITB misses
system.cpu1.itb.fetch_acv                           0                       # ITB acv
system.cpu1.itb.fetch_accesses                 500025                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.workload.num_syscalls                  18                       # Number of system calls
system.cpu1.numCycles                         1457840                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                     499993                       # Number of instructions committed
system.cpu1.committedOps                       499993                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses               474681                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                      474681                       # number of integer instructions
system.cpu1.num_fp_insts                           32                       # number of float instructions
system.cpu1.num_int_register_reads             654273                       # number of times the integer registers were read
system.cpu1.num_int_register_writes            371536                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
system.cpu1.num_mem_refs                       180792                       # number of memory refs
system.cpu1.num_load_insts                     124443                       # Number of load instructions
system.cpu1.num_store_insts                     56349                       # Number of store instructions
system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
system.cpu1.num_busy_cycles                   1457840                       # Number of busy cycles
system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
system.cpu1.icache.replacements                   152                       # number of replacements
system.cpu1.icache.tagsinuse               216.386658                       # Cycle average of tags in use
system.cpu1.icache.total_refs                  499549                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs               1078.939525                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   216.386658                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.422630                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.422630                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst       499549                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         499549                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst       499549                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          499549                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst       499549                       # number of overall hits
system.cpu1.icache.overall_hits::total         499549                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          463                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          463                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          463                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           463                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          463                       # number of overall misses
system.cpu1.icache.overall_misses::total          463                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     23473000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     23473000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     23473000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     23473000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     23473000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     23473000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst       500012                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total       500012                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst       500012                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total       500012                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst       500012                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total       500012                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.000926                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.000926                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.000926                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 50697.624190                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 50697.624190                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 50697.624190                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          463                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          463                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          463                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     22084000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total     22084000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     22084000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total     22084000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     22084000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total     22084000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.000926                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47697.624190                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47697.624190                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47697.624190                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                    61                       # number of replacements
system.cpu1.dcache.tagsinuse               273.512548                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                  180311                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                389.440605                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   273.512548                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.534204                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.534204                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        56200                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
system.cpu1.dcache.demand_hits::cpu1.data       180311                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total          180311                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data       180311                       # number of overall hits
system.cpu1.dcache.overall_hits::total         180311                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          324                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
system.cpu1.dcache.demand_misses::cpu1.data          463                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           463                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          463                       # number of overall misses
system.cpu1.dcache.overall_misses::total          463                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     17785000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total     17785000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      7803000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      7803000                       # number of WriteReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data     25588000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total     25588000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data     25588000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total     25588000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data       124435                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total       124435                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        56339                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data       180774                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total       180774                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data       180774                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total       180774                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.002604                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.002467                       # miss rate for WriteReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.002561                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.002561                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 54891.975309                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 56136.690647                       # average WriteReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 55265.658747                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 55265.658747                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks           29                       # number of writebacks
system.cpu1.dcache.writebacks::total               29                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          324                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          139                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          463                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          463                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data     16813000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total     16813000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      7386000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      7386000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data     24199000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total     24199000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data     24199000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total     24199000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002604                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002467                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002561                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51891.975309                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53136.690647                       # average WriteReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52265.658747                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52265.658747                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits                          0                       # ITB hits
system.cpu2.dtb.fetch_misses                        0                       # ITB misses
system.cpu2.dtb.fetch_acv                           0                       # ITB acv
system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu2.dtb.read_hits                      124433                       # DTB read hits
system.cpu2.dtb.read_misses                         8                       # DTB read misses
system.cpu2.dtb.read_acv                            0                       # DTB read access violations
system.cpu2.dtb.read_accesses                  124441                       # DTB read accesses
system.cpu2.dtb.write_hits                      56339                       # DTB write hits
system.cpu2.dtb.write_misses                       10                       # DTB write misses
system.cpu2.dtb.write_acv                           0                       # DTB write access violations
system.cpu2.dtb.write_accesses                  56349                       # DTB write accesses
system.cpu2.dtb.data_hits                      180772                       # DTB hits
system.cpu2.dtb.data_misses                        18                       # DTB misses
system.cpu2.dtb.data_acv                            0                       # DTB access violations
system.cpu2.dtb.data_accesses                  180790                       # DTB accesses
system.cpu2.itb.fetch_hits                     500001                       # ITB hits
system.cpu2.itb.fetch_misses                       13                       # ITB misses
system.cpu2.itb.fetch_acv                           0                       # ITB acv
system.cpu2.itb.fetch_accesses                 500014                       # ITB accesses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.read_acv                            0                       # DTB read access violations
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.write_acv                           0                       # DTB write access violations
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.data_hits                           0                       # DTB hits
system.cpu2.itb.data_misses                         0                       # DTB misses
system.cpu2.itb.data_acv                            0                       # DTB access violations
system.cpu2.itb.data_accesses                       0                       # DTB accesses
system.cpu2.workload.num_syscalls                  18                       # Number of system calls
system.cpu2.numCycles                         1457840                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                     499982                       # Number of instructions committed
system.cpu2.committedOps                       499982                       # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses               474671                       # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
system.cpu2.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
system.cpu2.num_int_insts                      474671                       # number of integer instructions
system.cpu2.num_fp_insts                           32                       # number of float instructions
system.cpu2.num_int_register_reads             654261                       # number of times the integer registers were read
system.cpu2.num_int_register_writes            371526                       # number of times the integer registers were written
system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
system.cpu2.num_mem_refs                       180789                       # number of memory refs
system.cpu2.num_load_insts                     124440                       # Number of load instructions
system.cpu2.num_store_insts                     56349                       # Number of store instructions
system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
system.cpu2.num_busy_cycles                   1457840                       # Number of busy cycles
system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
system.cpu2.icache.replacements                   152                       # number of replacements
system.cpu2.icache.tagsinuse               216.383557                       # Cycle average of tags in use
system.cpu2.icache.total_refs                  499538                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs               1078.915767                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst   216.383557                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.422624                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.422624                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst       499538                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total         499538                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst       499538                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total          499538                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst       499538                       # number of overall hits
system.cpu2.icache.overall_hits::total         499538                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          463                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          463                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          463                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           463                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          463                       # number of overall misses
system.cpu2.icache.overall_misses::total          463                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     23483000                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     23483000                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     23483000                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     23483000                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     23483000                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     23483000                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst       500001                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total       500001                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst       500001                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total       500001                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst       500001                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total       500001                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.000926                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.000926                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.000926                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 50719.222462                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 50719.222462                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 50719.222462                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          463                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          463                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          463                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     22094000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total     22094000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     22094000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total     22094000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     22094000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total     22094000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.000926                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47719.222462                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47719.222462                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47719.222462                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                    61                       # number of replacements
system.cpu2.dcache.tagsinuse               273.508588                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                  180309                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs                389.436285                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data   273.508588                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.534196                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.534196                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data       124109                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total         124109                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        56200                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
system.cpu2.dcache.demand_hits::cpu2.data       180309                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total          180309                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data       180309                       # number of overall hits
system.cpu2.dcache.overall_hits::total         180309                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          324                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
system.cpu2.dcache.demand_misses::cpu2.data          463                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           463                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          463                       # number of overall misses
system.cpu2.dcache.overall_misses::total          463                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     17794000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total     17794000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      7797000                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      7797000                       # number of WriteReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data     25591000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total     25591000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data     25591000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total     25591000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data       124433                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total       124433                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        56339                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data       180772                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total       180772                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data       180772                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total       180772                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.002604                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.002467                       # miss rate for WriteReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.002561                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.002561                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 54919.753086                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 56093.525180                       # average WriteReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 55272.138229                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 55272.138229                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks           29                       # number of writebacks
system.cpu2.dcache.writebacks::total               29                       # number of writebacks
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          324                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          139                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          463                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          463                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data     16822000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total     16822000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      7380000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      7380000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data     24202000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total     24202000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data     24202000                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total     24202000                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.002604                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002467                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002561                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51919.753086                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53093.525180                       # average WriteReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52272.138229                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52272.138229                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits                          0                       # ITB hits
system.cpu3.dtb.fetch_misses                        0                       # ITB misses
system.cpu3.dtb.fetch_acv                           0                       # ITB acv
system.cpu3.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu3.dtb.read_hits                      124431                       # DTB read hits
system.cpu3.dtb.read_misses                         8                       # DTB read misses
system.cpu3.dtb.read_acv                            0                       # DTB read access violations
system.cpu3.dtb.read_accesses                  124439                       # DTB read accesses
system.cpu3.dtb.write_hits                      56339                       # DTB write hits
system.cpu3.dtb.write_misses                       10                       # DTB write misses
system.cpu3.dtb.write_acv                           0                       # DTB write access violations
system.cpu3.dtb.write_accesses                  56349                       # DTB write accesses
system.cpu3.dtb.data_hits                      180770                       # DTB hits
system.cpu3.dtb.data_misses                        18                       # DTB misses
system.cpu3.dtb.data_acv                            0                       # DTB access violations
system.cpu3.dtb.data_accesses                  180788                       # DTB accesses
system.cpu3.itb.fetch_hits                     499997                       # ITB hits
system.cpu3.itb.fetch_misses                       13                       # ITB misses
system.cpu3.itb.fetch_acv                           0                       # ITB acv
system.cpu3.itb.fetch_accesses                 500010                       # ITB accesses
system.cpu3.itb.read_hits                           0                       # DTB read hits
system.cpu3.itb.read_misses                         0                       # DTB read misses
system.cpu3.itb.read_acv                            0                       # DTB read access violations
system.cpu3.itb.read_accesses                       0                       # DTB read accesses
system.cpu3.itb.write_hits                          0                       # DTB write hits
system.cpu3.itb.write_misses                        0                       # DTB write misses
system.cpu3.itb.write_acv                           0                       # DTB write access violations
system.cpu3.itb.write_accesses                      0                       # DTB write accesses
system.cpu3.itb.data_hits                           0                       # DTB hits
system.cpu3.itb.data_misses                         0                       # DTB misses
system.cpu3.itb.data_acv                            0                       # DTB access violations
system.cpu3.itb.data_accesses                       0                       # DTB accesses
system.cpu3.workload.num_syscalls                  18                       # Number of system calls
system.cpu3.numCycles                         1457840                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.committedInsts                     499978                       # Number of instructions committed
system.cpu3.committedOps                       499978                       # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses               474667                       # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
system.cpu3.num_conditional_control_insts        38178                       # number of instructions that are conditional controls
system.cpu3.num_int_insts                      474667                       # number of integer instructions
system.cpu3.num_fp_insts                           32                       # number of float instructions
system.cpu3.num_int_register_reads             654256                       # number of times the integer registers were read
system.cpu3.num_int_register_writes            371523                       # number of times the integer registers were written
system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
system.cpu3.num_mem_refs                       180787                       # number of memory refs
system.cpu3.num_load_insts                     124438                       # Number of load instructions
system.cpu3.num_store_insts                     56349                       # Number of store instructions
system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
system.cpu3.num_busy_cycles                   1457840                       # Number of busy cycles
system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
system.cpu3.icache.replacements                   152                       # number of replacements
system.cpu3.icache.tagsinuse               216.381810                       # Cycle average of tags in use
system.cpu3.icache.total_refs                  499534                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   463                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs               1078.907127                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst   216.381810                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.422621                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.422621                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst       499534                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total         499534                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst       499534                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total          499534                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst       499534                       # number of overall hits
system.cpu3.icache.overall_hits::total         499534                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          463                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          463                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          463                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           463                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          463                       # number of overall misses
system.cpu3.icache.overall_misses::total          463                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     23492000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total     23492000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst     23492000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total     23492000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst     23492000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total     23492000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst       499997                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total       499997                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst       499997                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total       499997                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst       499997                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total       499997                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.000926                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.000926                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.000926                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 50738.660907                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 50738.660907                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 50738.660907                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          463                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          463                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          463                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          463                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          463                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     22103000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total     22103000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     22103000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total     22103000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     22103000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total     22103000                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.000926                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 47738.660907                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 47738.660907                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47738.660907                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                    61                       # number of replacements
system.cpu3.dcache.tagsinuse               273.505617                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                  180307                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                   463                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs                389.431965                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data   273.505617                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.534191                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.534191                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data       124107                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total         124107                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        56200                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         56200                       # number of WriteReq hits
system.cpu3.dcache.demand_hits::cpu3.data       180307                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total          180307                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data       180307                       # number of overall hits
system.cpu3.dcache.overall_hits::total         180307                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          324                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          324                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
system.cpu3.dcache.demand_misses::cpu3.data          463                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           463                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          463                       # number of overall misses
system.cpu3.dcache.overall_misses::total          463                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data     17791000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total     17791000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      7797000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      7797000                       # number of WriteReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data     25588000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total     25588000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data     25588000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total     25588000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data       124431                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total       124431                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        56339                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        56339                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data       180770                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total       180770                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data       180770                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total       180770                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.002604                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.002467                       # miss rate for WriteReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.002561                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.002561                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 54910.493827                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 56093.525180                       # average WriteReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 55265.658747                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 55265.658747                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
system.cpu3.dcache.writebacks::total               29                       # number of writebacks
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          324                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          324                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          139                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          139                       # number of WriteReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          463                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          463                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          463                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          463                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data     16819000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total     16819000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      7380000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      7380000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data     24199000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total     24199000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data     24199000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total     24199000                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.002604                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002467                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002561                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 51910.493827                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53093.525180                       # average WriteReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52265.658747                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52265.658747                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                      1943.298536                       # Cycle average of tags in use
system.l2c.total_refs                             332                       # Total number of references to valid blocks.
system.l2c.sampled_refs                          2932                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          0.113233                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks           17.228456                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           265.029263                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data           216.501106                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           265.023656                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data           216.496016                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst           265.019384                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data           216.492927                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst           265.017115                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data           216.490615                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000263                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.004044                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.003304                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.004044                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.003303                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.004044                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.003303                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.004044                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.003303                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.029652                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                 60                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                 60                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                 60                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                 60                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks             116                       # number of Writeback hits
system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
system.l2c.overall_hits::total                    276                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              403                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data              315                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              403                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              315                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst              403                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data              315                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst              403                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data              315                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
system.l2c.overall_misses::total                 3428                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     20968000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data     16386000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     20958000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     16380000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst     20961000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data     16382000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst     20959000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data     16381000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      149375000                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      7228000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data      7228000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data      7230000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data      7229000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total     28915000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     20968000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     23614000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     20958000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data     23608000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst     20961000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data     23612000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst     20959000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data     23610000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total       178290000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     20968000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     23614000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     20958000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data     23608000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst     20961000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data     23612000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst     20959000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data     23610000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total      178290000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            463                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data            324                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            463                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data            324                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            463                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data            324                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            463                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data            324                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks          116                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data          139                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data             463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data             463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data             463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data            463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data            463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.870410                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.972222                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.870410                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.972222                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.870410                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.972222                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.870410                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.972222                       # miss rate for ReadReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.980562                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.870410                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.980562                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.870410                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.980562                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.870410                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.980562                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.870410                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.980562                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.870410                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.980562                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52029.776675                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52019.047619                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52004.962779                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52012.406948                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 52006.349206                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52007.444169                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data 52003.174603                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data        52000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data        52000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52014.388489                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52007.194245                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52029.776675                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52013.215859                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52004.962779                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 52012.406948                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 52008.810573                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 52007.444169                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 52004.405286                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52029.776675                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52013.215859                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52004.962779                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 52012.406948                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 52008.810573                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 52007.444169                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 52004.405286                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_misses::cpu0.inst          403                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data          315                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          403                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          315                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst          403                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data          315                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst          403                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data          315                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            2872                       # number of ReadReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data          139                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data          139                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data          139                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data          139                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           556                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          403                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          454                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          403                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data          454                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst          403                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data          454                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst          403                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data          454                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total             3428                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          403                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          454                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          403                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data          454                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst          403                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data          454                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst          403                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data          454                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total            3428                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     16132000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data     12606000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     16122000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     12600000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst     16125000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data     12602000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst     16123000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data     12601000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    114911000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5560000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data      5560000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      5562000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      5561000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total     22243000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     16132000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     18166000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     16122000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data     18160000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst     16125000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data     18164000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst     16123000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data     18162000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total    137154000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     16132000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     18166000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     16122000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data     18160000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst     16125000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data     18164000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst     16123000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data     18162000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total    137154000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.972222                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.972222                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.972222                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.972222                       # mshr miss rate for ReadReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.980562                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.980562                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.980562                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.980562                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.870410                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.980562                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.870410                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.980562                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.870410                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.980562                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.870410                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.980562                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40029.776675                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40019.047619                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.962779                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40012.406948                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40006.349206                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40007.444169                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40003.174603                       # average ReadReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40014.388489                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40007.194245                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40029.776675                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.215859                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.962779                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40012.406948                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40008.810573                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40007.444169                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40004.405286                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40029.776675                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.215859                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.962779                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40012.406948                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40008.810573                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40007.444169                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40004.405286                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------