path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000125                       # Number of seconds simulated
sim_ticks                                   124830000                       # Number of ticks simulated
final_tick                                  124830000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 284956                       # Simulator instruction rate (inst/s)
host_op_rate                                   284955                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               30713692                       # Simulator tick rate (ticks/s)
host_mem_usage                                 268476                       # Number of bytes of host memory used
host_seconds                                     4.06                       # Real time elapsed on the host
sim_insts                                     1158143                       # Number of instructions simulated
sim_ops                                       1158143                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst            24000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             5888                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              896                       # Number of bytes read from this memory
system.physmem.bytes_read::total                45824                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        24000                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         5888                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          896                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          896                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           31680                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               375                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               170                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                92                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                22                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   716                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           192261476                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            87158536                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            47168149                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            11279340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             7177762                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7690459                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             7177762                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7177762                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               367091244                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      192261476                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       47168149                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        7177762                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        7177762                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          253785148                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          192261476                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           87158536                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           47168149                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           11279340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            7177762                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7690459                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            7177762                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7177762                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              367091244                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           716                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         716                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    45824                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     45824                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 120                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  44                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  33                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  63                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  69                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  19                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  27                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  31                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 72                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 47                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 19                       # Per bank write bursts
system.physmem.perBankRdBursts::15                101                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                       124590000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     716                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       416                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          174                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      246.436782                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     161.758718                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     247.924177                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             67     38.51%     38.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           43     24.71%     63.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           26     14.94%     78.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           12      6.90%     85.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            7      4.02%     89.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            8      4.60%     93.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            3      1.72%     95.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            2      1.15%     96.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            6      3.45%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            174                       # Bytes accessed per row activation
system.physmem.totQLat                       12446750                       # Total ticks spent queuing
system.physmem.totMemAccLat                  25871750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3580000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       17383.73                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  36133.73                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         367.09                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      367.09                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.87                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.87                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.26                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        530                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.02                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       174008.38                       # Average gap between requests
system.physmem.pageHitRate                      74.02                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     856800                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     432630                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   2877420                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           9834240.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy                6410790                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                 304320                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy          34392090                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy          13115040                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       649140.000000                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy                 68872470                       # Total energy per rank (pJ)
system.physmem_0.averagePower              551.730113                       # Core power per rank (mW)
system.physmem_0.totalIdleTime              109416750                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE         358500                       # Time in different power states
system.physmem_0.memoryStateTime::REF         4166000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF         403000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN     34152000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        10318500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN     75432000                       # Time in different power states
system.physmem_1.actEnergy                     471240                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     227700                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   2234820                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           9834240.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy                5188140                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 617280                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy          32401650                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy          11725440                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy            3565380                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy                 66265890                       # Total energy per rank (pJ)
system.physmem_1.averagePower              530.849075                       # Core power per rank (mW)
system.physmem_1.totalIdleTime              111659250                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE        1125500                       # Time in different power states
system.physmem_1.memoryStateTime::REF         4172000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF       10253750                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN     30535250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT         7679500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN     71064000                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu0.branchPred.lookups                  98509                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            93993                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1599                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               95823                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                   1115                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups          95823                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits             88367                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses            7456                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted         1077                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.pwrStateResidencyTicks::ON      124830000                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                          249661                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             22650                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        581099                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      98509                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             89482                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       193985                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3497                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                        78                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         2191                       # Number of stall cycles due to pending traps
system.cpu0.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                     7995                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  871                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples            220664                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.633411                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.264413                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   33866     15.35%     15.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   91353     41.40%     56.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     668      0.30%     57.05% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     983      0.45%     57.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     516      0.23%     57.73% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   86959     39.41%     97.14% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     734      0.33%     97.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     482      0.22%     97.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    5103      2.31%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              220664                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.394571                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.327552                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   17658                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                19166                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   181260                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  832                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  1748                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                563638                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  1748                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18349                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   2015                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         15764                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   181386                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                 1402                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                558452                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                    11                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents                   925                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands             382172                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups              1112707                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          840550                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups                4                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps               362927                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   19245                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts              1073                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts          1102                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     5312                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              178069                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              89965                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            86828                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           86540                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    465662                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded               1094                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   461556                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              118                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          16666                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        13597                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           535                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       220664                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.091669                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.110492                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              36803     16.68%     16.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4402      1.99%     18.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              88094     39.92%     58.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              87764     39.77%     98.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1699      0.77%     99.14% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                985      0.45%     99.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                568      0.26%     99.84% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                247      0.11%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                102      0.05%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         220664                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                    129     39.09%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMultAcc                0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMisc                   0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     39.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    77     23.33%     62.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  124     37.58%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               194924     42.23%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMultAcc              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMisc                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              177454     38.45%     80.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              89178     19.32%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                461556                       # Type of FU issued
system.cpu0.iq.rate                          1.848731                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        330                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000715                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1144224                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           483466                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       458888                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 8                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                461886                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           86265                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         3016                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            7                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1932                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           12                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  1748                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   2015                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   29                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             554202                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              154                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               178069                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               89965                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               980                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    30                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           232                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1714                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1946                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               460023                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               177079                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1533                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        87446                       # number of nop insts executed
system.cpu0.iew.exec_refs                      266047                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   91396                       # Number of branches executed
system.cpu0.iew.exec_stores                     88968                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.842591                       # Inst execution rate
system.cpu0.iew.wb_sent                        459364                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       458888                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   272127                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   275688                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      1.838044                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.987083                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts          17379                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1599                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       217244                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.470687                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.142582                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        36715     16.90%     16.90% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        90144     41.49%     58.39% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2018      0.93%     59.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          613      0.28%     59.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          486      0.22%     59.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        86051     39.61%     99.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          459      0.21%     99.65% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          294      0.14%     99.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          464      0.21%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       217244                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              536742                       # Number of instructions committed
system.cpu0.commit.committedOps                536742                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        263086                       # Number of memory references committed
system.cpu0.commit.loads                       175053                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     89920                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   361258                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass        86652     16.14%     16.14% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu          186920     34.82%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMultAcc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMisc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead         175137     32.63%     83.60% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite         88033     16.40%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total           536742                       # Class of committed instruction
system.cpu0.commit.bw_lim_events                  464                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                      769740                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1111721                       # The number of ROB writes
system.cpu0.timesIdled                            320                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          28997                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     450006                       # Number of Instructions Simulated
system.cpu0.committedOps                       450006                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              0.554795                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.554795                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.802468                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.802468                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  822274                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 370684                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 268168                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          142.144997                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs             177494                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              172                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs          1031.941860                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.144997                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277627                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.277627                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          170                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.332031                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           715284                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          715284                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data        90136                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          90136                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        87436                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         87436                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           24                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             24                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       177572                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          177572                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       177572                       # number of overall hits
system.cpu0.dcache.overall_hits::total         177572                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          571                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          571                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          555                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          555                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           18                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           18                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1126                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1126                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1126                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1126                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16338000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     16338000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     35699989                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     35699989                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       501500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       501500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     52037989                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     52037989                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     52037989                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     52037989                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        90707                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        90707                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        87991                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        87991                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       178698                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       178698                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       178698                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       178698                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006295                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.006295                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006307                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.006307                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.428571                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.428571                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006301                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006301                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006301                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006301                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28612.959720                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 28612.959720                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64324.304505                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 64324.304505                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27861.111111                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 27861.111111                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46214.910302                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 46214.910302                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46214.910302                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 46214.910302                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          885                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    42.142857                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          369                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          369                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          385                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          385                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          754                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          754                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          754                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          754                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          202                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          202                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          170                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          170                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           18                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           18                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          372                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          372                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          372                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          372                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      7501000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      7501000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8169500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8169500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       483500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       483500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15670500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     15670500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15670500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     15670500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002227                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002227                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.001932                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.001932                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.428571                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002082                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002082                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002082                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002082                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37133.663366                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37133.663366                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48055.882353                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48055.882353                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26861.111111                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26861.111111                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data        42125                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total        42125                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data        42125                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total        42125                       # average overall mshr miss latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements              393                       # number of replacements
system.cpu0.icache.tags.tagsinuse          248.700617                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs               7078                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              695                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.184173                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   248.700617                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.485743                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.485743                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          302                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           44                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          188                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.589844                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses             8690                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses            8690                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst         7078                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           7078                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         7078                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            7078                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         7078                       # number of overall hits
system.cpu0.icache.overall_hits::total           7078                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          917                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          917                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          917                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           917                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          917                       # number of overall misses
system.cpu0.icache.overall_misses::total          917                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     47775500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     47775500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     47775500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     47775500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     47775500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     47775500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         7995                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         7995                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         7995                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         7995                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         7995                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         7995                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.114697                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.114697                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.114697                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.114697                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.114697                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.114697                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52099.781897                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 52099.781897                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52099.781897                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 52099.781897                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52099.781897                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 52099.781897                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs          151                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                4                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    37.750000                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks          393                       # number of writebacks
system.cpu0.icache.writebacks::total              393                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          221                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          221                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          221                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          221                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          221                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          221                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          696                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          696                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          696                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          696                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          696                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          696                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     36615000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     36615000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     36615000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     36615000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     36615000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     36615000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087054                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.087054                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087054                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.087054                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087054                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.087054                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52607.758621                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52607.758621                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52607.758621                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 52607.758621                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52607.758621                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 52607.758621                       # average overall mshr miss latency
system.cpu1.branchPred.lookups                  69942                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            62611                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             2168                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               62876                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                   1880                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups          62876                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits             52518                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses           10358                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted         1122                       # Number of mispredicted indirect branches.
system.cpu1.pwrStateResidencyTicks::ON      124830000                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                          191834                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             35275                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        386727                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      69942                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             54398                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       146033                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   4493                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles                   6                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1374                       # Number of stall cycles due to pending traps
system.cpu1.fetch.IcacheWaitRetryStallCycles           38                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                    23469                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  905                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            184982                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             2.090620                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.368236                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   58784     31.78%     31.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   61509     33.25%     65.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    6216      3.36%     68.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3423      1.85%     70.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     694      0.38%     70.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   43897     23.73%     94.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1064      0.58%     94.92% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                    1288      0.70%     95.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    8107      4.38%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              184982                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.364596                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       2.015946                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   21795                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                53545                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                   103882                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 3504                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2246                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                357234                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2246                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   22757                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  24349                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         13357                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                   104467                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                17796                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                350958                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                 15108                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands             246923                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               678000                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          525614                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups               22                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps               220975                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   25948                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1579                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1706                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    23252                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               99419                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              48107                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            46982                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           41894                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    289725                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               6510                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   288968                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               96                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          22905                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        18076                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved          1082                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       184982                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.562141                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.375121                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              62949     34.03%     34.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              21563     11.66%     45.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              46877     25.34%     71.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              46716     25.25%     96.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3504      1.89%     98.18% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1701      0.92%     99.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                999      0.54%     99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                396      0.21%     99.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                277      0.15%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         184982                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                    191     40.04%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMultAcc                0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMisc                   0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     40.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    60     12.58%     52.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  226     47.38%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               138690     47.99%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMultAcc              0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMisc                 0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.99% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead              103154     35.70%     83.69% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              47124     16.31%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                288968                       # Type of FU issued
system.cpu1.iq.rate                          1.506344                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        477                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001651                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            763491                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           319139                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       285378                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                44                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                289445                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           41785                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         4131                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses           40                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           43                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         2566                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2246                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   7047                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             344310                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              276                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                99419                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               48107                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1464                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    36                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            43                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           462                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         2268                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                2730                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               286645                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                97925                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             2323                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        48075                       # number of nop insts executed
system.cpu1.iew.exec_refs                      144750                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   58305                       # Number of branches executed
system.cpu1.iew.exec_stores                     46825                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.494235                       # Inst execution rate
system.cpu1.iew.wb_sent                        285841                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       285378                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   162569                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   170014                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      1.487630                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.956209                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts          23932                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           5428                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             2168                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       180468                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.775063                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.087699                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        67886     37.62%     37.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        54714     30.32%     67.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         5489      3.04%     70.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         6162      3.41%     74.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1291      0.72%     75.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        41971     23.26%     98.36% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          718      0.40%     98.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1059      0.59%     99.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8         1178      0.65%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       180468                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              320342                       # Number of instructions committed
system.cpu1.commit.committedOps                320342                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        140829                       # Number of memory references committed
system.cpu1.commit.loads                        95288                       # Number of loads committed
system.cpu1.commit.membars                       4715                       # Number of memory barriers committed
system.cpu1.commit.branches                     56221                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   219172                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass        47012     14.68%     14.68% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu          127786     39.89%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult              0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMultAcc            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMisc            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.57% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead         100003     31.22%     85.78% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite         45541     14.22%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total           320342                       # Class of committed instruction
system.cpu1.commit.bw_lim_events                 1178                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                      522978                       # The number of ROB reads
system.cpu1.rob.rob_writes                     693117                       # The number of ROB writes
system.cpu1.timesIdled                            233                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           6852                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       49387                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     268615                       # Number of Instructions Simulated
system.cpu1.committedOps                       268615                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              0.714160                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.714160                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.400247                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.400247                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  497951                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 231611                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 146596                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           26.433606                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              52423                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs          1747.433333                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.433606                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.051628                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.051628                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           406876                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          406876                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data        55612                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          55612                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        45312                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         45312                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           12                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data       100924                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total          100924                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data       100924                       # number of overall hits
system.cpu1.dcache.overall_hits::total         100924                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          502                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          502                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          162                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          162                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           55                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          664                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           664                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          664                       # number of overall misses
system.cpu1.dcache.overall_misses::total          664                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      5584500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      5584500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3659500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3659500                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       374500                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       374500                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      9244000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      9244000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      9244000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      9244000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        56114                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        56114                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        45474                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        45474                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           67                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           67                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data       101588                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total       101588                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data       101588                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total       101588                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008946                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.008946                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003562                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.003562                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.820896                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.820896                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006536                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.006536                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006536                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.006536                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11124.501992                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 11124.501992                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22589.506173                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22589.506173                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  6809.090909                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  6809.090909                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13921.686747                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 13921.686747                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13921.686747                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13921.686747                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          340                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          340                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           55                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           55                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          395                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          395                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          395                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          395                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          162                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           55                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          269                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          269                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          269                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          269                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2129000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2129000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1532000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1532000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       319500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       319500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3661000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      3661000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3661000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      3661000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002887                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002887                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002353                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002353                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.820896                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.820896                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002648                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.002648                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002648                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.002648                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13141.975309                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13141.975309                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14317.757009                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14317.757009                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  5809.090909                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  5809.090909                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13609.665428                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13609.665428                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13609.665428                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13609.665428                       # average overall mshr miss latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements              556                       # number of replacements
system.cpu1.icache.tags.tagsinuse           97.753950                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs              22636                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              690                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            32.805797                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    97.753950                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.190926                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.190926                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          134                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.261719                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses            24159                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses           24159                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst        22636                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          22636                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        22636                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           22636                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        22636                       # number of overall hits
system.cpu1.icache.overall_hits::total          22636                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          833                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          833                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          833                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           833                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          833                       # number of overall misses
system.cpu1.icache.overall_misses::total          833                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     20006500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     20006500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     20006500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     20006500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     20006500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     20006500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        23469                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        23469                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        23469                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        23469                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        23469                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        23469                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.035494                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.035494                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.035494                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.035494                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.035494                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.035494                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24017.406963                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 24017.406963                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24017.406963                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 24017.406963                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24017.406963                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 24017.406963                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          207                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                6                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    34.500000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks          556                       # number of writebacks
system.cpu1.icache.writebacks::total              556                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst          143                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total          143                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst          143                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total          143                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst          143                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total          143                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          690                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          690                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          690                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          690                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          690                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          690                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     15540500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total     15540500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     15540500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total     15540500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     15540500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total     15540500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.029400                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.029400                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.029400                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.029400                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.029400                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.029400                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22522.463768                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22522.463768                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22522.463768                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 22522.463768                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22522.463768                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 22522.463768                       # average overall mshr miss latency
system.cpu2.branchPred.lookups                  60250                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            52369                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             2399                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               52178                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                   1981                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups          52178                       # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits             41452                       # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses           10726                       # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted         1295                       # Number of mispredicted indirect branches.
system.cpu2.pwrStateResidencyTicks::ON      124830000                       # Cumulative time (in ticks) in various power states
system.cpu2.numCycles                          191431                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             42696                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        319764                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      60250                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             43433                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       142400                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   4955                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         2218                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    31580                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  988                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            189804                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.684706                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.290533                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   80855     42.60%     42.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   54436     28.68%     71.28% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    9994      5.27%     76.54% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3383      1.78%     78.33% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     680      0.36%     78.69% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   29156     15.36%     94.05% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1157      0.61%     94.66% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                    1395      0.73%     95.39% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    8748      4.61%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              189804                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.314735                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.670388                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   22561                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                83775                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    75624                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 5357                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2477                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                288545                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2477                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   23562                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  41928                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         13956                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    76490                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                31381                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                281938                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                 27181                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                    13                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents               2                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands             195781                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               524561                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          411315                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               32                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps               166026                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   29755                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1653                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1783                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    36818                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               74139                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              33614                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            35848                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           27180                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    226553                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded              10243                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   228568                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued              140                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          25915                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        20426                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved          1250                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       189804                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.204232                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.376602                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              85980     45.30%     45.30% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              32313     17.02%     62.32% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              32235     16.98%     79.31% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              31990     16.85%     96.16% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3688      1.94%     98.10% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1698      0.89%     99.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6               1058      0.56%     99.56% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                511      0.27%     99.83% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                331      0.17%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         189804                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                    232     44.96%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMultAcc                0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMisc                   0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     44.96% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    58     11.24%     56.20% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  226     43.80%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               114651     50.16%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMultAcc              0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMisc                 0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.16% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               81333     35.58%     85.74% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              32584     14.26%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                228568                       # Type of FU issued
system.cpu2.iq.rate                          1.193997                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        516                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.002258                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            647596                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           262684                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       224391                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                64                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                229084                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           27120                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         4546                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses           31                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         2695                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2477                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                  10821                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             273857                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              388                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                74139                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               33614                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1537                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    28                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            37                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           461                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         2611                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                3072                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               225860                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                72453                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             2708                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        37061                       # number of nop insts executed
system.cpu2.iew.exec_refs                      104703                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   47570                       # Number of branches executed
system.cpu2.iew.exec_stores                     32250                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.179851                       # Inst execution rate
system.cpu2.iew.wb_sent                        224905                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       224391                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   122751                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   130504                       # num instructions consuming a value
system.cpu2.iew.wb_rate                      1.172177                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.940592                       # average fanout of values written-back
system.cpu2.commit.commitSquashedInsts          27003                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           8993                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             2399                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       184731                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.336127                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.921991                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        94349     51.07%     51.07% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        43685     23.65%     74.72% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         5440      2.94%     77.67% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         9609      5.20%     82.87% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1281      0.69%     83.56% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        27371     14.82%     98.38% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          737      0.40%     98.78% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1041      0.56%     99.34% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8         1218      0.66%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       184731                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              246824                       # Number of instructions committed
system.cpu2.commit.committedOps                246824                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        100512                       # Number of memory references committed
system.cpu2.commit.loads                        69593                       # Number of loads committed
system.cpu2.commit.membars                       8278                       # Number of memory barriers committed
system.cpu2.commit.branches                     45154                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   167790                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        35943     14.56%     14.56% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu          102091     41.36%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMultAcc            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMisc            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.92% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead          77871     31.55%     87.47% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite         30919     12.53%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total           246824                       # Class of committed instruction
system.cpu2.commit.bw_lim_events                 1218                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                      456754                       # The number of ROB reads
system.cpu2.rob.rob_writes                     552779                       # The number of ROB writes
system.cpu2.timesIdled                            204                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           1627                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       49789                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     202603                       # Number of Instructions Simulated
system.cpu2.committedOps                       202603                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              0.944858                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.944858                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.058360                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.058360                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  379324                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 178066                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 106600                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           24.613342                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              38229                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               31                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1233.193548                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    24.613342                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.048073                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.048073                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           31                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.060547                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           305153                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          305153                       # Number of data accesses
system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu2.dcache.ReadReq_hits::cpu2.data        44839                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          44839                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        30714                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         30714                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           16                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        75553                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           75553                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        75553                       # number of overall hits
system.cpu2.dcache.overall_hits::total          75553                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          467                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          467                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          136                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          136                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           53                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           53                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          603                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           603                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          603                       # number of overall misses
system.cpu2.dcache.overall_misses::total          603                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      3772500                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      3772500                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3722500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      3722500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       339500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       339500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      7495000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      7495000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      7495000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      7495000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        45306                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        45306                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        30850                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        30850                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        76156                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        76156                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        76156                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        76156                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.010308                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.010308                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004408                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.004408                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.768116                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.768116                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007918                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.007918                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007918                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.007918                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data  8078.158458                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total  8078.158458                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 27371.323529                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 27371.323529                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  6405.660377                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  6405.660377                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 12429.519071                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 12429.519071                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 12429.519071                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 12429.519071                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          301                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          301                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           34                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data            1                       # number of SwapReq MSHR hits
system.cpu2.dcache.SwapReq_mshr_hits::total            1                       # number of SwapReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          335                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          335                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          335                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          335                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          166                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          166                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          102                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          102                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           52                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          268                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          268                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1217000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1217000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1941500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1941500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       286500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       286500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3158500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      3158500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3158500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      3158500                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003664                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003664                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003306                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003306                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.753623                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.753623                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003519                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.003519                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003519                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.003519                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  7331.325301                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  7331.325301                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19034.313725                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19034.313725                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  5509.615385                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  5509.615385                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11785.447761                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11785.447761                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11785.447761                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11785.447761                       # average overall mshr miss latency
system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements              564                       # number of replacements
system.cpu2.icache.tags.tagsinuse           92.356205                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs              30734                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              702                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs            43.780627                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    92.356205                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.180383                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.180383                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.269531                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses            32282                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses           32282                       # Number of data accesses
system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu2.icache.ReadReq_hits::cpu2.inst        30734                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          30734                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        30734                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           30734                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        30734                       # number of overall hits
system.cpu2.icache.overall_hits::total          30734                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          846                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          846                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          846                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           846                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          846                       # number of overall misses
system.cpu2.icache.overall_misses::total          846                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     12713000                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     12713000                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     12713000                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     12713000                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     12713000                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     12713000                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        31580                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        31580                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        31580                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        31580                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        31580                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        31580                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.026789                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.026789                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.026789                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.026789                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.026789                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.026789                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15027.186761                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 15027.186761                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15027.186761                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 15027.186761                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15027.186761                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 15027.186761                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs           48                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs           24                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.writebacks::writebacks          564                       # number of writebacks
system.cpu2.icache.writebacks::total              564                       # number of writebacks
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst          144                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total          144                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst          144                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total          144                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst          144                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total          144                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          702                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          702                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          702                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          702                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          702                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          702                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     10591000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total     10591000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     10591000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total     10591000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     10591000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total     10591000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.022229                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.022229                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.022229                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.022229                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.022229                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.022229                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15086.894587                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15086.894587                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15086.894587                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 15086.894587                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15086.894587                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 15086.894587                       # average overall mshr miss latency
system.cpu3.branchPred.lookups                  65607                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            57989                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             2329                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               57945                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                   1972                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups          57945                       # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits             47394                       # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses           10551                       # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted         1239                       # Number of mispredicted indirect branches.
system.cpu3.pwrStateResidencyTicks::ON      124830000                       # Cumulative time (in ticks) in various power states
system.cpu3.numCycles                          191064                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             38959                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        355945                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      65607                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             49366                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       146283                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   4811                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1648                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    27872                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  954                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            189308                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.880243                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.334212                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   70601     37.29%     37.29% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   58551     30.93%     68.22% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    8289      4.38%     72.60% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3543      1.87%     74.47% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     620      0.33%     74.80% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   36795     19.44%     94.24% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1123      0.59%     94.83% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                    1294      0.68%     95.51% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    8492      4.49%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              189308                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.343377                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.862962                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   22011                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                70196                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    90137                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 4549                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2405                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                325577                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2405                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   23040                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  34162                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         13425                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    90919                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                25347                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                318974                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                 21885                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.RenamedOperands             222576                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               605183                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          471258                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups               38                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps               194403                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   28173                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1623                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1757                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    30798                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               87479                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              41118                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            41854                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           34728                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    259350                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               8662                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   260097                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued              100                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          24362                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        19655                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved          1213                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       189308                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.373936                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.388628                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              75622     39.95%     39.95% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              27531     14.54%     54.49% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              39579     20.91%     75.40% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              39359     20.79%     96.19% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3671      1.94%     98.13% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1727      0.91%     99.04% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6               1045      0.55%     99.59% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                450      0.24%     99.83% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                324      0.17%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         189308                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                    198     41.42%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMultAcc                0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMisc                   0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     41.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    48     10.04%     51.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  232     48.54%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               126919     48.80%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMultAcc              0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMisc                 0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.80% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               93130     35.81%     84.60% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              40048     15.40%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                260097                       # Type of FU issued
system.cpu3.iq.rate                          1.361308                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        478                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001838                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            710080                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           292336                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       256163                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                76                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                260575                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           34620                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         4474                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses           40                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           38                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         2718                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2405                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   9114                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             311067                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              408                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                87479                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               41118                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1508                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    34                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            38                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           450                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         2479                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                2929                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               257518                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                85797                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             2579                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        43055                       # number of nop insts executed
system.cpu3.iew.exec_refs                      125534                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   53219                       # Number of branches executed
system.cpu3.iew.exec_stores                     39737                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.347810                       # Inst execution rate
system.cpu3.iew.wb_sent                        256666                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       256163                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   143359                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   150866                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      1.340718                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.950241                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts          25509                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           7449                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             2329                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       184454                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.547985                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     2.017686                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        82386     44.66%     44.66% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        49463     26.82%     71.48% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         5369      2.91%     74.39% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         8071      4.38%     78.77% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1252      0.68%     79.45% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        34869     18.90%     98.35% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          786      0.43%     98.78% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1015      0.55%     99.33% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8         1243      0.67%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       184454                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              285532                       # Number of instructions committed
system.cpu3.commit.committedOps                285532                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                        121405                       # Number of memory references committed
system.cpu3.commit.loads                        83005                       # Number of loads committed
system.cpu3.commit.membars                       6731                       # Number of memory barriers committed
system.cpu3.commit.branches                     51096                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   194617                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass        41882     14.67%     14.67% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu          115514     40.46%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult              0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMultAcc            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMisc            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.12% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead          89736     31.43%     86.55% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite         38400     13.45%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total           285532                       # Class of committed instruction
system.cpu3.commit.bw_lim_events                 1243                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                      493666                       # The number of ROB reads
system.cpu3.rob.rob_writes                     626988                       # The number of ROB writes
system.cpu3.timesIdled                            229                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1756                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       50157                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     236919                       # Number of Instructions Simulated
system.cpu3.committedOps                       236919                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              0.806453                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.806453                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.239998                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.239998                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  440410                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 205469                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 127408                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           25.184575                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              45468                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs          1567.862069                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.184575                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.049189                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.049189                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           358446                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          358446                       # Number of data accesses
system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu3.dcache.ReadReq_hits::cpu3.data        50650                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          50650                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        38188                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         38188                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        88838                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           88838                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        88838                       # number of overall hits
system.cpu3.dcache.overall_hits::total          88838                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          496                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          496                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          140                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           60                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           60                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          636                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           636                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          636                       # number of overall misses
system.cpu3.dcache.overall_misses::total          636                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      3601500                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      3601500                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2913500                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2913500                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       356500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       356500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      6515000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      6515000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      6515000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      6515000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        51146                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        51146                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        38328                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        38328                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           72                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           72                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        89474                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        89474                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        89474                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        89474                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.009698                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.009698                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003653                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.003653                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.833333                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.833333                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007108                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.007108                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007108                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.007108                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data  7261.088710                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total  7261.088710                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20810.714286                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 20810.714286                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  5941.666667                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  5941.666667                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10243.710692                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 10243.710692                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10243.710692                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 10243.710692                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          326                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          326                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           35                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data            1                       # number of SwapReq MSHR hits
system.cpu3.dcache.SwapReq_mshr_hits::total            1                       # number of SwapReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          361                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          361                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          361                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          361                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          170                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           59                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           59                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          275                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          275                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          275                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          275                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1125000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1125000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1450500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1450500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       296500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       296500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2575500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2575500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2575500                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2575500                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003324                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003324                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002740                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002740                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.819444                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.819444                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003074                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003074                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003074                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003074                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6617.647059                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6617.647059                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13814.285714                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13814.285714                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  5025.423729                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  5025.423729                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9365.454545                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9365.454545                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9365.454545                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9365.454545                       # average overall mshr miss latency
system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements              586                       # number of replacements
system.cpu3.icache.tags.tagsinuse           96.347148                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs              27016                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              724                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs            37.314917                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    96.347148                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.188178                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.188178                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.269531                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses            28596                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses           28596                       # Number of data accesses
system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.cpu3.icache.ReadReq_hits::cpu3.inst        27016                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          27016                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        27016                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           27016                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        27016                       # number of overall hits
system.cpu3.icache.overall_hits::total          27016                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          856                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          856                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          856                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           856                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          856                       # number of overall misses
system.cpu3.icache.overall_misses::total          856                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     12888000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total     12888000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst     12888000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total     12888000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst     12888000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total     12888000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        27872                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        27872                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        27872                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        27872                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        27872                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        27872                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.030712                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.030712                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.030712                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.030712                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.030712                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.030712                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15056.074766                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 15056.074766                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15056.074766                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 15056.074766                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15056.074766                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 15056.074766                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs           17                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs           17                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.writebacks::writebacks          586                       # number of writebacks
system.cpu3.icache.writebacks::total              586                       # number of writebacks
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst          132                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total          132                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst          132                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total          132                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst          132                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total          132                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          724                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          724                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          724                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          724                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          724                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          724                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     11106000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total     11106000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     11106000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total     11106000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     11106000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total     11106000                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.025976                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.025976                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.025976                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.025976                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.025976                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.025976                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 15339.779006                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 15339.779006                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 15339.779006                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 15339.779006                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 15339.779006                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 15339.779006                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  566.391309                       # Cycle average of tags in use
system.l2c.tags.total_refs                       3152                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      716                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.402235                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::cpu0.inst      300.631868                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data      144.597180                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst       70.863487                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       15.770640                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst        7.294857                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data       10.082216                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        7.192526                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        9.958536                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::cpu0.inst       0.004587                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.002206                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.001081                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000241                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000111                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000154                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000110                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000152                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.008642                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          716                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          484                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.010925                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    31812                       # Number of tag accesses
system.l2c.tags.data_accesses                   31812                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks          730                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total             730                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              23                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              22                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              25                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data              20                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  90                       # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst           318                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst           594                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst           679                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst           707                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total              2298                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst                 318                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 594                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 679                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 707                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    2330                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                318                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                594                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                679                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                707                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   2330                       # number of overall hits
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst          378                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst           96                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst           23                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst           17                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total             514                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data           76                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data            9                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data            3                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total             90                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst               378                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               170                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                96                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                22                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                23                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                15                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                17                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                14                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   735                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              378                       # number of overall misses
system.l2c.overall_misses::cpu0.data              170                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               96                       # number of overall misses
system.l2c.overall_misses::cpu1.data               22                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               23                       # number of overall misses
system.l2c.overall_misses::cpu2.data               15                       # number of overall misses
system.l2c.overall_misses::cpu3.inst               17                       # number of overall misses
system.l2c.overall_misses::cpu3.data               14                       # number of overall misses
system.l2c.overall_misses::total                  735                       # number of overall misses
system.l2c.ReadExReq_miss_latency::cpu0.data      7962000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data      1092000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data      1485500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data      1007500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total     11547000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst     32045000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst      7767000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst      1841000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst      2001000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total     43654000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data      6727000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data      1292500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data       289000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data       179500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total      8488000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     32045000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     14689000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      7767000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      2384500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      1841000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1774500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst      2001000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data      1187000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        63689000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     32045000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     14689000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      7767000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      2384500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      1841000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1774500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst      2001000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data      1187000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       63689000                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks          730                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total          730                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           23                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           25                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              90                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst          696                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst          690                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst          702                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst          724                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total          2812                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data           81                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data           14                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data           14                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total          122                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             696                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             175                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             690                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              27                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             702                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             724                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                3065                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            696                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            175                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            690                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             27                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            702                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            724                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               3065                       # number of overall (read+write) accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.543103                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.139130                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.032764                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.023481                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.182788                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.938272                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.642857                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.214286                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.153846                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.737705                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.543103                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971429                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.139130                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.814815                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.032764                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.576923                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.023481                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.560000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.239804                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.543103                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971429                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.139130                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.814815                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.032764                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.576923                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.023481                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.560000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.239804                       # miss rate for overall accesses
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84702.127660                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data        84000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 123791.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 83958.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 88145.038168                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84775.132275                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80906.250000                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 80043.478261                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 117705.882353                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 84929.961089                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88513.157895                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143611.111111                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 96333.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        89750                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 94311.111111                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 84775.132275                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 86405.882353                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80906.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 108386.363636                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 80043.478261                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data       118300                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 117705.882353                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 84785.714286                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 86651.700680                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 84775.132275                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 86405.882353                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80906.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 108386.363636                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 80043.478261                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data       118300                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 117705.882353                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 84785.714286                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 86651.700680                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            2                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            9                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            3                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           18                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          376                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           92                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           14                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst           14                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total          496                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data           76                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data            9                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data            3                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total           90                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          376                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          170                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           92                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           22                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              717                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          376                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          170                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           92                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           22                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             717                       # number of overall MSHR misses
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      7022000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       962000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      1365500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       887500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total     10237000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     28190500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      6632500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      1096000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst      1627000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total     37546000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5967000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data      1202500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       259000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data       159500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total      7588000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     28190500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     12989000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      6632500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data      2164500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      1096000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1624500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst      1627000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data      1047000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     55371000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     28190500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     12989000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      6632500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data      2164500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      1096000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1624500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst      1627000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data      1047000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     55371000                       # number of overall MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.540230                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.133333                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.019943                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.019337                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.176387                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.938272                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.642857                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.214286                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.153846                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.737705                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.540230                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.133333                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.814815                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.019943                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.576923                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.019337                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.560000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.233931                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.540230                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.133333                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.814815                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.019943                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.576923                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.019337                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.560000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.233931                       # mshr miss rate for overall accesses
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74702.127660                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        74000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 73958.333333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 78145.038168                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74974.734043                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72092.391304                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 78285.714286                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 116214.285714                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75697.580645                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78513.157895                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133611.111111                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86333.333333                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        79750                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84311.111111                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74974.734043                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76405.882353                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72092.391304                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98386.363636                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 78285.714286                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data       108300                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 116214.285714                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 74785.714286                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 77225.941423                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74974.734043                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76405.882353                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72092.391304                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98386.363636                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 78285.714286                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data       108300                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 116214.285714                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 74785.714286                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 77225.941423                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests           969                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests          253                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                585                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              194                       # Transaction distribution
system.membus.trans_dist::ReadExReq               190                       # Transaction distribution
system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           585                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1685                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1685                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        45824                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   45824                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              253                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               969                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     969    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 969                       # Request fanout histogram
system.membus.reqLayer0.occupancy              889500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3809250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.1                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests         6292                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests         1720                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         3250                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED    124830000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp              3503                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            8                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean         2099                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             284                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            284                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              395                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             395                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq          2812                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq          700                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1784                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          599                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1936                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          373                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1968                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          372                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         2034                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          380                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  9446                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        69632                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11264                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        79744                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1728                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        81024                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        83840                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total                 330496                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                            1036                       # Total snoops (count)
system.toL2Bus.snoopTraffic                     53888                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples             4191                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.288475                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.109326                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                   1322     31.54%     31.54% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                   1164     27.77%     59.32% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    879     20.97%     80.29% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                    826     19.71%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total               4191                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy            5261968                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              4.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy           1043496                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy            528992                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           1037993                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy            434459                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy           1056988                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy            424982                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           1087497                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.9                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy            445966                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.4                       # Layer utilization (%)

---------- End Simulation Statistics   ----------