path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000111                       # Number of seconds simulated
sim_ticks                                   111025500                       # Number of ticks simulated
final_tick                                  111025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 119782                       # Simulator instruction rate (inst/s)
host_op_rate                                   119782                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               12747983                       # Simulator tick rate (ticks/s)
host_mem_usage                                 275656                       # Number of bytes of host memory used
host_seconds                                     8.71                       # Real time elapsed on the host
sim_insts                                     1043212                       # Number of instructions simulated
sim_ops                                       1043212                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst            22784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst              640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst             4672                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data             1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                42176                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        22784                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst          640                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst         4672                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          384                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           28480                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               356                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                73                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   659                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           205214117                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            96842617                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst             5764442                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             7493774                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst            42080423                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data            11528883                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             3458665                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7493774                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               379876695                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      205214117                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst        5764442                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst       42080423                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        3458665                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          256517647                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          205214117                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           96842617                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst            5764442                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            7493774                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst           42080423                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data           11528883                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            3458665                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7493774                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              379876695                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           660                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         660                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    42240                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     42240                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             76                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 115                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  39                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  29                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  60                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  65                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  27                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  18                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  24                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 12                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 60                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 38                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 17                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 98                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                       110997500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     660                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       408                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       191                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        49                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          151                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      260.662252                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     168.685653                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     287.368727                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64                56     37.09%     37.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128               15      9.93%     47.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192               26     17.22%     64.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256                9      5.96%     70.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320               10      6.62%     76.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384                7      4.64%     81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448                4      2.65%     84.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512                6      3.97%     88.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576                3      1.99%     90.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640                3      1.99%     92.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704                2      1.32%     93.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768                2      1.32%     94.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832                3      1.99%     96.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024               2      1.32%     98.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152               1      0.66%     98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536               1      0.66%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984               1      0.66%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            151                       # Bytes accessed per row activation
system.physmem.totQLat                        4010250                       # Total ticks spent queuing
system.physmem.totMemAccLat                  18159000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3300000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                    10848750                       # Total ticks spent accessing banks
system.physmem.avgQLat                        6076.14                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    16437.50                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27513.64                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         380.45                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      380.45                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.97                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.16                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        509                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.12                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       168178.03                       # Average gap between requests
system.physmem.pageHitRate                      77.12                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent              11.34                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                    379876695                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 529                       # Transaction distribution
system.membus.trans_dist::ReadResp                528                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              289                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              76                       # Transaction distribution
system.membus.trans_dist::ReadExReq               164                       # Transaction distribution
system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1717                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1717                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port        42176                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               42176                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  42176                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              931500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy            6289925                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              5.7                       # Layer utilization (%)
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  417.165472                       # Cycle average of tags in use
system.l2c.tags.total_refs                       1442                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      526                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.741445                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks       0.799798                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      285.088059                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data       58.417692                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst        7.543236                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data        0.694746                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst       55.417060                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data        5.409300                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        3.063366                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        0.732215                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.004350                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.000891                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.000115                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000011                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000846                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000083                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000047                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000011                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.006365                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                229                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                412                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                349                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                420                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1442                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 229                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 412                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 349                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 420                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1442                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                229                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                412                       # number of overall hits
system.l2c.overall_hits::cpu1.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                349                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                420                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   1442                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              359                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               16                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               76                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  543                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            17                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            18                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                76                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               359                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                76                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   674                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              359                       # number of overall misses
system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               16                       # number of overall misses
system.l2c.overall_misses::cpu1.data               13                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               76                       # number of overall misses
system.l2c.overall_misses::cpu2.data               20                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  674                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     24801500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      5612000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      1162500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst      5361500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data       495250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       584250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       38166000                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      6725000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       852250                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data      1087000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       958250                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      9622500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     24801500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     12337000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      1162500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data       926750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      5361500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1582250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       584250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data      1032750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        47788500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     24801500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     12337000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      1162500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data       926750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      5361500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1582250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       584250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data      1032750                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       47788500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            588                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            428                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            425                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            429                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               1985                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           24                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           18                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             588                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             428                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             425                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             429                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2116                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            588                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            428                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            425                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            429                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2116                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.610544                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.037383                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.178824                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.583333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.020979                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.273552                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.875000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.962025                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.610544                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.037383                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.178824                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.800000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.020979                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.318526                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.610544                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.037383                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.178824                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.800000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.020979                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.318526                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69084.958217                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72656.250000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70546.052632                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        70750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64916.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 70287.292818                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71542.553191                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79854.166667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73454.198473                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 69084.958217                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 73434.523810                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72656.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 70546.052632                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 64916.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 79442.307692                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 70902.818991                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 69084.958217                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 73434.523810                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72656.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 70546.052632                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 64916.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 79442.307692                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 70902.818991                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu0.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                14                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 14                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                14                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          357                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           10                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst           73                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            6                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             529                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           21                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           17                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           18                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           76                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          357                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           73                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              660                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          357                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           73                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             660                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     20238250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      4701500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       676500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      4287250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data       408750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       369750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     30807000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       210021                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       217519                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       170017                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       180018                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       777575                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5552000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       701750                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       928000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       807750                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      7989500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     20238250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     10253500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst       676500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       764250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      4287250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1336750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       369750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       870250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     38796500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     20238250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     10253500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst       676500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       764250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      4287250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1336750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       369750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       870250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     38796500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.171765                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.583333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.013986                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.266499                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.875000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.962025                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.171765                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.013986                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.311909                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.171765                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.013986                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.311909                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56689.775910                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        67650                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58729.452055                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        61625                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 58236.294896                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10875.950000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59063.829787                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67312.500000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60988.549618                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56689.775910                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61032.738095                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        67650                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58729.452055                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        61625                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66942.307692                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58782.575758                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        67650                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        61625                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66942.307692                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58782.575758                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.toL2Bus.throughput                  1689557804                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq               2542                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp              2541                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             292                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            292                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              389                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             389                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1175                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          591                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          856                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          373                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          850                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          367                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          858                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          348                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  5418                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        37568                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11136                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        27392                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        27200                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        27456                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total             135424                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus                135424                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus           52160                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy            1628974                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              1.5                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy           2704748                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             2.4                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy           1475514                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             1.3                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           1928994                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             1.7                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy           1199245                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             1.1                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy           1926995                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             1.7                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy           1183748                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             1.1                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           1932245                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             1.7                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy           1115744                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             1.0                       # Layer utilization (%)
system.cpu0.branchPred.lookups                  83087                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            80860                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1219                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               80377                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                  78332                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            97.455740                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                    512                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               132                       # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          222052                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             17258                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        493192                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      83087                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             78844                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       161829                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3807                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 13993                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1512                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     5869                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  489                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            197037                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.503043                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.216869                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   35208     17.87%     17.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   80150     40.68%     58.55% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     582      0.30%     58.84% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     988      0.50%     59.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     452      0.23%     59.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   76210     38.68%     98.25% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     578      0.29%     98.54% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     364      0.18%     98.73% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2505      1.27%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              197037                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.374178                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.221065                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   17850                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                15597                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   160862                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  288                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2440                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                490280                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2440                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18506                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                    827                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         14176                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   160527                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  561                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                487444                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents                  187                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands             333388                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups               972038                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          734246                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               320411                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   12977                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               872                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           895                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     3641                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              155927                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              78789                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            76026                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           75860                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    407640                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                922                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   405049                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              128                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          10720                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined         9381                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           363                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       197037                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.055700                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.097210                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              34075     17.29%     17.29% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4941      2.51%     19.80% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              78065     39.62%     59.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              77366     39.26%     98.69% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1557      0.79%     99.48% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                667      0.34%     99.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                262      0.13%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 87      0.04%     99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 17      0.01%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         197037                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     57     27.01%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     27.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    42     19.91%     46.92% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  112     53.08%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               171308     42.29%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              155510     38.39%     80.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              78231     19.31%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                405049                       # Type of FU issued
system.cpu0.iq.rate                          1.824118                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        211                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000521                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1007474                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           419326                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       403236                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                405260                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           75609                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2132                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           44                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1385                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           19                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2440                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                    371                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   29                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             485139                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              313                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               155927                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               78789                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               806                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    30                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            44                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           328                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1114                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1442                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               403978                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               155175                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1071                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        76577                       # number of nop insts executed
system.cpu0.iew.exec_refs                      233309                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   80250                       # Number of branches executed
system.cpu0.iew.exec_stores                     78134                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.819295                       # Inst execution rate
system.cpu0.iew.wb_sent                        403577                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       403236                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   238895                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   241362                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.815953                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.989779                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts          12132                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1219                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       194597                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.430500                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.136019                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        34534     17.75%     17.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        80010     41.12%     58.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2413      1.24%     60.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          690      0.35%     60.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          532      0.27%     60.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        75417     38.76%     99.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          460      0.24%     99.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          239      0.12%     99.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          302      0.16%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       194597                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              472968                       # Number of instructions committed
system.cpu0.commit.committedOps                472968                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        231199                       # Number of memory references committed
system.cpu0.commit.loads                       153795                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     79291                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   318742                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events                  302                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      678234                       # The number of ROB reads
system.cpu0.rob.rob_writes                     972657                       # The number of ROB writes
system.cpu0.timesIdled                            325                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          25015                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     396861                       # Number of Instructions Simulated
system.cpu0.committedOps                       396861                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total               396861                       # Number of Instructions Simulated
system.cpu0.cpi                              0.559521                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.559521                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.787244                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.787244                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  722661                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 325773                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 235146                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.tags.replacements              297                       # number of replacements
system.cpu0.icache.tags.tagsinuse          241.313735                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs               5113                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              587                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             8.710392                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.313735                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471316                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.471316                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst         5113                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           5113                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         5113                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            5113                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         5113                       # number of overall hits
system.cpu0.icache.overall_hits::total           5113                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          756                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          756                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          756                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           756                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          756                       # number of overall misses
system.cpu0.icache.overall_misses::total          756                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     35940245                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     35940245                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     35940245                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     35940245                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     35940245                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     35940245                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         5869                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         5869                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         5869                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         5869                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         5869                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         5869                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.128812                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.128812                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.128812                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.128812                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.128812                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.128812                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47540.006614                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 47540.006614                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47540.006614                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 47540.006614                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47540.006614                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 47540.006614                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          168                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          168                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          168                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          168                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          168                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          168                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          588                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          588                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          588                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          588                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          588                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          588                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     27686252                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     27686252                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     27686252                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     27686252                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     27686252                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     27686252                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.100187                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.100187                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.100187                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.100187                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.100187                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.100187                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47085.462585                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47085.462585                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47085.462585                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 47085.462585                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47085.462585                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 47085.462585                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          142.026994                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs             155821                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              170                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs           916.594118                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.026994                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277396                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.277396                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        79085                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          79085                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        76817                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         76817                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       155902                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          155902                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       155902                       # number of overall hits
system.cpu0.dcache.overall_hits::total         155902                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          420                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          420                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          545                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          545                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data          965                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total           965                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data          965                       # number of overall misses
system.cpu0.dcache.overall_misses::total          965                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     13542707                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     13542707                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     32279504                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     32279504                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       404750                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       404750                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     45822211                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     45822211                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     45822211                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     45822211                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        79505                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        79505                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        77362                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        77362                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       156867                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       156867                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       156867                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       156867                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005283                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.005283                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007045                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007045                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006152                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006152                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006152                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006152                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32244.540476                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 32244.540476                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59228.447706                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 59228.447706                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47484.156477                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 47484.156477                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47484.156477                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 47484.156477                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          503                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.952381                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          227                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          227                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          373                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          373                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          600                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          600                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          600                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          600                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          193                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          193                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          172                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          172                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          365                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          365                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          365                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6251507                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6251507                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7188729                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7188729                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       361250                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       361250                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     13440236                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     13440236                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     13440236                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     13440236                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002428                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002428                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002223                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002223                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002327                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002327                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002327                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002327                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32391.227979                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32391.227979                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41794.936047                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41794.936047                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36822.564384                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36822.564384                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36822.564384                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36822.564384                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                  47485                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            44754                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             1270                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               41396                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                  40599                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            98.074693                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                    654                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
system.cpu1.numCycles                          177933                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             31734                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        260080                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      47485                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             41253                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                        95164                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   3727                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 37889                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         7775                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles          775                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    23379                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  257                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            175722                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.480065                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.059330                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   80558     45.84%     45.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   49339     28.08%     73.92% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    7969      4.54%     78.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3191      1.82%     80.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     687      0.39%     80.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   28723     16.35%     97.01% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1207      0.69%     97.70% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     759      0.43%     98.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3289      1.87%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              175722                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.266870                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.461674                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   38713                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                32553                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    87468                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 6833                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2380                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                256418                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2380                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   39395                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  20083                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         11723                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    80903                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                13463                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                254199                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                   22                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands             175957                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               477753                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          373133                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               162997                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   12960                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1085                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1202                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    16072                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               69810                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              31966                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            34021                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           26934                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    208112                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               8163                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   211924                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               72                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          10867                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        10911                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           602                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       175722                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.206019                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.291588                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              78073     44.43%     44.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              27855     15.85%     60.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              32175     18.31%     78.59% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              32801     18.67%     97.26% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3291      1.87%     99.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1173      0.67%     99.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                248      0.14%     99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 49      0.03%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         175722                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     12      4.51%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    44     16.54%     21.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  210     78.95%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               104746     49.43%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.43% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               75900     35.81%     85.24% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              31278     14.76%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                211924                       # Type of FU issued
system.cpu1.iq.rate                          1.191033                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        266                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001255                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            599908                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           227186                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       210080                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                212190                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           26664                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2449                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           44                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1447                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2380                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                    699                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   40                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             251202                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              408                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                69810                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               31966                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1044                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            44                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           470                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect          919                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1389                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               210729                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                68768                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1195                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        34927                       # number of nop insts executed
system.cpu1.iew.exec_refs                       99964                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   44131                       # Number of branches executed
system.cpu1.iew.exec_stores                     31196                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.184317                       # Inst execution rate
system.cpu1.iew.wb_sent                        210404                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       210080                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   116723                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   121388                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.180669                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.961570                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts          12479                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           7561                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1270                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       165567                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.441743                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.939965                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        77636     46.89%     46.89% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        42274     25.53%     72.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         6096      3.68%     76.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         8474      5.12%     81.22% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1557      0.94%     82.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        27207     16.43%     98.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          510      0.31%     98.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1010      0.61%     99.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          803      0.49%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       165567                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              238705                       # Number of instructions committed
system.cpu1.commit.committedOps                238705                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                         97880                       # Number of memory references committed
system.cpu1.commit.loads                        67361                       # Number of loads committed
system.cpu1.commit.membars                       6845                       # Number of memory barriers committed
system.cpu1.commit.branches                     43327                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   163326                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events                  803                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      415361                       # The number of ROB reads
system.cpu1.rob.rob_writes                     504754                       # The number of ROB writes
system.cpu1.timesIdled                            217                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           2211                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       44117                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     197745                       # Number of Instructions Simulated
system.cpu1.committedOps                       197745                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total               197745                       # Number of Instructions Simulated
system.cpu1.cpi                              0.899810                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.899810                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.111345                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.111345                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  358439                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 167816                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 101509                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.icache.tags.replacements              318                       # number of replacements
system.cpu1.icache.tags.tagsinuse           76.730522                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs              22903                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              428                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            53.511682                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.730522                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149864                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.149864                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst        22903                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          22903                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        22903                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           22903                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        22903                       # number of overall hits
system.cpu1.icache.overall_hits::total          22903                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          476                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          476                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          476                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           476                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          476                       # number of overall misses
system.cpu1.icache.overall_misses::total          476                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7185993                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      7185993                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      7185993                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      7185993                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      7185993                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      7185993                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        23379                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        23379                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        23379                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        23379                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        23379                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        23379                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.020360                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.020360                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.020360                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.020360                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.020360                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.020360                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15096.623950                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15096.623950                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15096.623950                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15096.623950                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15096.623950                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15096.623950                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs           13                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           48                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           48                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           48                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           48                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           48                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           48                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          428                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          428                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          428                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          428                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          428                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          428                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5726006                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      5726006                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5726006                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      5726006                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5726006                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      5726006                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.018307                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.018307                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.018307                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.018307                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.018307                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.018307                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13378.518692                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13378.518692                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13378.518692                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13378.518692                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13378.518692                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13378.518692                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           23.664777                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              36646                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs          1263.655172                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    23.664777                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.046220                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.046220                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        41736                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          41736                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        30310                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         30310                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        72046                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           72046                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        72046                       # number of overall hits
system.cpu1.dcache.overall_hits::total          72046                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          352                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          352                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           57                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          491                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           491                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          491                       # number of overall misses
system.cpu1.dcache.overall_misses::total          491                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4404095                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      4404095                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2802760                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      2802760                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       563508                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       563508                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      7206855                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      7206855                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      7206855                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      7206855                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        42088                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        42088                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        30449                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        30449                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        72537                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        72537                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        72537                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        72537                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008363                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.008363                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004565                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.004565                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.814286                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.814286                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006769                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.006769                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006769                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.006769                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12511.633523                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12511.633523                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20163.741007                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20163.741007                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  9886.105263                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  9886.105263                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14677.912424                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14677.912424                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14677.912424                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14677.912424                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          187                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          187                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           32                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           32                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          219                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          219                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          219                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          219                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          165                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          165                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           57                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          272                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          272                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          272                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          272                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1130523                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1130523                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1329240                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1329240                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       449492                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       449492                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2459763                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      2459763                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2459763                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      2459763                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003920                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003920                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003514                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003514                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.814286                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.814286                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003750                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.003750                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003750                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.003750                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  6851.654545                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  6851.654545                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12422.803738                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  7885.824561                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  7885.824561                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  9043.246324                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total  9043.246324                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  9043.246324                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total  9043.246324                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.branchPred.lookups                  51290                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            48575                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             1303                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               45092                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                  44400                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            98.465360                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                    684                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                          177568                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             28807                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        286591                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      51290                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             45084                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       100996                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   3797                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 31176                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         7777                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles          828                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    19752                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  272                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            172005                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.666178                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.140016                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   71009     41.28%     41.28% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   51379     29.87%     71.15% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    6118      3.56%     74.71% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3176      1.85%     76.56% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     688      0.40%     76.96% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   34434     20.02%     96.98% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1153      0.67%     97.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     776      0.45%     98.10% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    3272      1.90%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              172005                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.288847                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.613979                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   33784                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                27885                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    95101                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 5041                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2417                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                283083                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2417                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   34494                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  14868                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         12251                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    90316                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                 9882                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                280840                       # Number of instructions processed by rename
system.cpu2.rename.LSQFullEvents                   23                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands             196811                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               538434                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          418653                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               183802                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   13009                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1113                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1241                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    12535                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               79329                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              37643                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            37867                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           32593                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    232899                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               6340                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   234909                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               92                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          11011                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        10823                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           602                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       172005                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.365710                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.313889                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              68443     39.79%     39.79% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              22432     13.04%     52.83% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              37853     22.01%     74.84% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              38461     22.36%     97.20% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3256      1.89%     99.09% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1167      0.68%     99.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                279      0.16%     99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 57      0.03%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         172005                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     17      6.01%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    56     19.79%     25.80% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  210     74.20%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               114350     48.68%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.68% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               83601     35.59%     84.27% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              36958     15.73%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                234909                       # Type of FU issued
system.cpu2.iq.rate                          1.322924                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        283                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001205                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            642198                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           250297                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       233108                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                235192                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           32324                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         2477                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           47                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1468                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2417                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                    878                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   50                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             278010                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              351                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                79329                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               37643                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1071                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    50                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            47                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           457                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect          973                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1430                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               233765                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                78300                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             1144                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        38771                       # number of nop insts executed
system.cpu2.iew.exec_refs                      115173                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   48001                       # Number of branches executed
system.cpu2.iew.exec_stores                     36873                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.316482                       # Inst execution rate
system.cpu2.iew.wb_sent                        233421                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       233108                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   131942                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   136650                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.312782                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.965547                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts          12656                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           5738                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1303                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       161811                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.639889                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.021157                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        66196     40.91%     40.91% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        46128     28.51%     69.42% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         6098      3.77%     73.19% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         6657      4.11%     77.30% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1558      0.96%     78.26% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        32865     20.31%     98.57% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          486      0.30%     98.87% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1000      0.62%     99.49% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          823      0.51%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       161811                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              265352                       # Number of instructions committed
system.cpu2.commit.committedOps                265352                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        113027                       # Number of memory references committed
system.cpu2.commit.loads                        76852                       # Number of loads committed
system.cpu2.commit.membars                       5022                       # Number of memory barriers committed
system.cpu2.commit.branches                     47160                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   182307                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events                  823                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      438409                       # The number of ROB reads
system.cpu2.rob.rob_writes                     558438                       # The number of ROB writes
system.cpu2.timesIdled                            223                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           5563                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       44482                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     222382                       # Number of Instructions Simulated
system.cpu2.committedOps                       222382                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total               222382                       # Number of Instructions Simulated
system.cpu2.cpi                              0.798482                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.798482                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.252377                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.252377                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  404230                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 188808                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 116736                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.icache.tags.replacements              317                       # number of replacements
system.cpu2.icache.tags.tagsinuse           82.236622                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs              19259                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              425                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs            45.315294                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    82.236622                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.160618                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.160618                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst        19259                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          19259                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        19259                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           19259                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        19259                       # number of overall hits
system.cpu2.icache.overall_hits::total          19259                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          493                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          493                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          493                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           493                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          493                       # number of overall misses
system.cpu2.icache.overall_misses::total          493                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     11620241                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     11620241                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     11620241                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     11620241                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     11620241                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     11620241                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        19752                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        19752                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        19752                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        19752                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        19752                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        19752                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024959                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.024959                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024959                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.024959                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024959                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.024959                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23570.468560                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 23570.468560                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23570.468560                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 23570.468560                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23570.468560                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 23570.468560                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs           85                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs           85                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           68                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           68                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           68                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          425                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          425                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          425                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          425                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          425                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          425                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      9299505                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      9299505                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      9299505                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      9299505                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      9299505                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      9299505                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021517                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021517                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021517                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.021517                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021517                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.021517                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21881.188235                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21881.188235                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21881.188235                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 21881.188235                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21881.188235                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 21881.188235                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           26.142582                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              42207                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1507.392857                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.142582                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051060                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.051060                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        45613                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          45613                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        35966                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         35966                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        81579                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           81579                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        81579                       # number of overall hits
system.cpu2.dcache.overall_hits::total          81579                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          346                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          346                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           57                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          485                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           485                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          485                       # number of overall misses
system.cpu2.dcache.overall_misses::total          485                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5531640                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      5531640                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3131011                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      3131011                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       555006                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       555006                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      8662651                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      8662651                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      8662651                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      8662651                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        45959                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        45959                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        36105                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        36105                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        82064                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        82064                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        82064                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        82064                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.007528                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.007528                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003850                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.003850                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.814286                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.814286                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005910                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.005910                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005910                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.005910                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15987.398844                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 15987.398844                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  9736.947368                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  9736.947368                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17861.136082                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 17861.136082                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17861.136082                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 17861.136082                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          184                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          184                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           33                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          217                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          217                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          217                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          217                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          162                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          106                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           57                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          268                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          268                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1488769                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1488769                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1526989                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1526989                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       440994                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       440994                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3015758                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      3015758                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3015758                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      3015758                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003525                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003525                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002936                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002936                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.814286                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.814286                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003266                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.003266                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003266                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.003266                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9189.932099                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9189.932099                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14405.556604                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14405.556604                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  7736.736842                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  7736.736842                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11252.828358                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11252.828358                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11252.828358                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11252.828358                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.branchPred.lookups                  52302                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            49590                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             1266                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               46219                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                  45467                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            98.372963                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                    659                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
system.cpu3.numCycles                          177222                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             28850                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        291591                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      52302                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             46126                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       103443                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   3689                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 32602                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         7775                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles          799                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    20565                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  250                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            175820                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.658463                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.129406                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   72377     41.17%     41.17% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   52818     30.04%     71.21% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    6573      3.74%     74.94% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3193      1.82%     76.76% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     659      0.37%     77.14% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   35007     19.91%     97.05% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1204      0.68%     97.73% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     759      0.43%     98.16% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3230      1.84%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              175820                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.295121                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.645343                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   34476                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                28632                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    97078                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 5513                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2346                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                288057                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2346                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   35171                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  16067                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         11805                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    91834                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                10822                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                285905                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents                   21                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands             199357                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               546724                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          424837                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               186591                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   12766                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1101                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1226                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    13474                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               80900                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              38213                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            38893                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           33161                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    236458                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               6797                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   239002                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued               90                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          10736                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        10694                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           584                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       175820                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.359356                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.308484                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              69781     39.69%     39.69% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              23810     13.54%     53.23% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              38390     21.83%     75.07% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              39034     22.20%     97.27% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3259      1.85%     99.12% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1173      0.67%     99.79% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                261      0.15%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 59      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         175820                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     17      6.20%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      6.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    47     17.15%     23.36% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  210     76.64%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               115815     48.46%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.46% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               85680     35.85%     84.31% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              37507     15.69%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                239002                       # Type of FU issued
system.cpu3.iq.rate                          1.348602                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        274                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001146                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            654188                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           254038                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       237209                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                239276                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           32896                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2413                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           47                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1461                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2346                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                    674                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   43                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             283043                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              388                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                80900                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               38213                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1061                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    42                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            47                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           456                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect          929                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1385                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               237848                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                79902                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1154                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        39788                       # number of nop insts executed
system.cpu3.iew.exec_refs                      117326                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   49028                       # Number of branches executed
system.cpu3.iew.exec_stores                     37424                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.342091                       # Inst execution rate
system.cpu3.iew.wb_sent                        237529                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       237209                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   134044                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   138720                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.338485                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.966292                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts          12298                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           6213                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1266                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       165699                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.633836                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     2.016583                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        68017     41.05%     41.05% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        47143     28.45%     69.50% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6068      3.66%     73.16% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         7148      4.31%     77.48% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1577      0.95%     78.43% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        33420     20.17%     98.60% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          508      0.31%     98.90% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7          998      0.60%     99.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          820      0.49%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       165699                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              270725                       # Number of instructions committed
system.cpu3.commit.committedOps                270725                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                        115239                       # Number of memory references committed
system.cpu3.commit.loads                        78487                       # Number of loads committed
system.cpu3.commit.membars                       5499                       # Number of memory barriers committed
system.cpu3.commit.branches                     48212                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   185574                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.bw_lim_events                  820                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      447315                       # The number of ROB reads
system.cpu3.rob.rob_writes                     568397                       # The number of ROB writes
system.cpu3.timesIdled                            211                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1402                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       44828                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     226224                       # Number of Instructions Simulated
system.cpu3.committedOps                       226224                       # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total               226224                       # Number of Instructions Simulated
system.cpu3.cpi                              0.783392                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.783392                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.276501                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.276501                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  410473                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 191401                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 118878                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.icache.tags.replacements              319                       # number of replacements
system.cpu3.icache.tags.tagsinuse           79.942849                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs              20090                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              429                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs            46.829837                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    79.942849                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.156138                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.156138                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst        20090                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          20090                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        20090                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           20090                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        20090                       # number of overall hits
system.cpu3.icache.overall_hits::total          20090                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          475                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          475                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          475                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           475                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          475                       # number of overall misses
system.cpu3.icache.overall_misses::total          475                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6449245                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      6449245                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      6449245                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      6449245                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      6449245                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      6449245                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        20565                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        20565                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        20565                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        20565                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        20565                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        20565                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.023097                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.023097                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.023097                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.023097                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.023097                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.023097                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13577.357895                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13577.357895                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13577.357895                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13577.357895                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13577.357895                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13577.357895                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           46                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           46                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           46                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           46                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           46                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           46                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          429                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          429                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          429                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          429                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          429                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          429                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5223255                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      5223255                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5223255                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      5223255                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5223255                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      5223255                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.020861                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.020861                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.020861                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.020861                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.020861                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.020861                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12175.419580                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12175.419580                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12175.419580                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12175.419580                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12175.419580                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12175.419580                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           24.692253                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              42769                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs          1527.464286                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.692253                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.048227                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.048227                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        46656                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          46656                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        36553                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         36553                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        83209                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           83209                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        83209                       # number of overall hits
system.cpu3.dcache.overall_hits::total          83209                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          333                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          333                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          131                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          131                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           54                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          464                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           464                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          464                       # number of overall misses
system.cpu3.dcache.overall_misses::total          464                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4249100                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      4249100                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3352512                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      3352512                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       492006                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       492006                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      7601612                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      7601612                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      7601612                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      7601612                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        46989                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        46989                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        36684                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        36684                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        83673                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        83673                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        83673                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        83673                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007087                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.007087                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003571                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.003571                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.794118                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.794118                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005545                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.005545                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005545                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.005545                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12760.060060                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 12760.060060                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25591.694656                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 25591.694656                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9111.222222                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  9111.222222                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16382.784483                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 16382.784483                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16382.784483                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 16382.784483                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          181                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          181                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           31                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           31                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          212                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          212                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          212                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          212                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          152                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          152                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          100                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          100                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           54                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          252                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          252                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          252                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1002524                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1002524                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1408738                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1408738                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       383994                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       383994                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2411262                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2411262                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2411262                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2411262                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003235                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003235                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002726                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002726                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.794118                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.794118                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003012                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003012                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003012                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003012                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6595.552632                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6595.552632                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14087.380000                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14087.380000                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data         7111                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total         7111                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9568.500000                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9568.500000                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9568.500000                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9568.500000                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------