path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000126                       # Number of seconds simulated
sim_ticks                                   125996000                       # Number of ticks simulated
final_tick                                  125996000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 220398                       # Simulator instruction rate (inst/s)
host_op_rate                                   220398                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               23837880                       # Simulator tick rate (ticks/s)
host_mem_usage                                 265580                       # Number of bytes of host memory used
host_seconds                                     5.29                       # Real time elapsed on the host
sim_insts                                     1164916                       # Number of instructions simulated
sim_ops                                       1164916                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst            23872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             5888                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::total                45440                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        23872                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         5888                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          896                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          640                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           31296                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               373                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               170                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                92                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                22                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   710                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           189466332                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            86351948                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            46731642                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            11174958                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             7111337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7111337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             5079526                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7619290                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               360646370                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      189466332                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       46731642                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        7111337                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        5079526                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          248388838                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          189466332                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           86351948                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           46731642                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           11174958                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            7111337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7111337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            5079526                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7619290                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              360646370                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           710                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         710                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    45440                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     45440                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 120                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  44                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  31                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  62                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  69                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  19                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  27                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  31                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 70                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 47                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 18                       # Per bank write bursts
system.physmem.perBankRdBursts::15                101                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                       125756000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     710                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       408                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       221                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        19                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          174                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      244.597701                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     161.475219                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     245.687167                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             66     37.93%     37.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           43     24.71%     62.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           29     16.67%     79.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           11      6.32%     85.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            6      3.45%     89.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            8      4.60%     93.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            4      2.30%     95.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            1      0.57%     96.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            6      3.45%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            174                       # Bytes accessed per row activation
system.physmem.totQLat                       13059500                       # Total ticks spent queuing
system.physmem.totMemAccLat                  26372000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3550000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       18393.66                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  37143.66                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         360.65                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      360.65                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.82                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.82                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.26                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        525                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   73.94                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       177121.13                       # Average gap between requests
system.physmem.pageHitRate                      73.94                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     856800                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     432630                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   2856000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           8604960.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy                6114390                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                 284160                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy          31286160                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy           8898240                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy            5367840                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy                 64701180                       # Total energy per rank (pJ)
system.physmem_0.averagePower              513.516712                       # Core power per rank (mW)
system.physmem_0.totalIdleTime              111273500                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE         346500                       # Time in different power states
system.physmem_0.memoryStateTime::REF         3646000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF       20064750                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN     23172500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        10159750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN     68606500                       # Time in different power states
system.physmem_1.actEnergy                     464100                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     227700                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   2213400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           8604960.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy                4959000                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 596640                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy          28649910                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy           9231840                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy            7511880                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy                 62459430                       # Total energy per rank (pJ)
system.physmem_1.averagePower              495.724516                       # Core power per rank (mW)
system.physmem_1.totalIdleTime              113374250                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE        1113500                       # Time in different power states
system.physmem_1.memoryStateTime::REF         3652000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF       26697750                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN     24040500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT         7662500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN     62829750                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu0.branchPred.lookups                  99694                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            94929                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1689                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               96632                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                   1210                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups          96632                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits             88884                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses            7748                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted         1163                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.pwrStateResidencyTicks::ON      125996000                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                          251993                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             23206                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        587602                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      99694                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             90094                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       195641                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3677                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                        78                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         2245                       # Number of stall cycles due to pending traps
system.cpu0.fetch.IcacheWaitRetryStallCycles           21                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                     8355                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  903                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples            223034                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.634585                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.272061                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   34543     15.49%     15.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   92075     41.28%     56.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     690      0.31%     57.08% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                    1016      0.46%     57.54% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     496      0.22%     57.76% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   87579     39.27%     97.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     656      0.29%     97.32% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     548      0.25%     97.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    5431      2.44%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              223034                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.395622                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.331819                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   18204                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                19474                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   182674                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  844                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  1838                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                568807                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  1838                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18897                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   2138                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         15951                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   182807                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                 1403                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                563480                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                    12                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents                   925                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands             385856                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups              1122771                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          848321                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups                8                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps               365359                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   20497                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts              1128                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts          1160                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     5339                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              179490                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              90635                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            87474                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           87162                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    469651                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded               1149                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   465284                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              130                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          17670                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        14278                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           590                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       223034                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.086157                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.115238                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              37655     16.88%     16.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4554      2.04%     18.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              88787     39.81%     58.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              88368     39.62%     98.35% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1704      0.76%     99.12% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               1021      0.46%     99.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                603      0.27%     99.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                223      0.10%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                119      0.05%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         223034                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                    140     40.46%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMultAcc                0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMisc                   0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    83     23.99%     64.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  123     35.55%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               196646     42.26%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMultAcc              0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMisc                 0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.26% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              178800     38.43%     80.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              89838     19.31%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                465284                       # Type of FU issued
system.cpu0.iq.rate                          1.846416                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        346                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000744                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1154078                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           488506                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       462560                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                16                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                465630                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           86875                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         3221                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            9                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1994                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           12                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  1838                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   2137                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   29                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             558923                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              171                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               179490                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               90635                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts              1033                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    30                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           218                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1860                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                2078                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               463731                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               178412                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1553                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        88123                       # number of nop insts executed
system.cpu0.iew.exec_refs                      268032                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   92124                       # Number of branches executed
system.cpu0.iew.exec_stores                     89620                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.840253                       # Inst execution rate
system.cpu0.iew.wb_sent                        463047                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       462560                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   274104                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   277790                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      1.835607                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.986731                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts          18452                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1689                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       219410                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.462923                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.143392                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        37598     17.14%     17.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        90827     41.40%     58.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2058      0.94%     59.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          592      0.27%     59.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          460      0.21%     59.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        86620     39.48%     99.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          500      0.23%     99.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          309      0.14%     99.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          446      0.20%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       219410                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              540390                       # Number of instructions committed
system.cpu0.commit.committedOps                540390                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        264910                       # Number of memory references committed
system.cpu0.commit.loads                       176269                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     90528                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   363690                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass        87260     16.15%     16.15% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu          188136     34.81%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult              0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMultAcc            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMisc            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     50.96% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead         176353     32.63%     83.60% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite         88641     16.40%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total           540390                       # Class of committed instruction
system.cpu0.commit.bw_lim_events                  446                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                      776645                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1121369                       # The number of ROB writes
system.cpu0.timesIdled                            318                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          28959                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     453046                       # Number of Instructions Simulated
system.cpu0.committedOps                       453046                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              0.556219                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.556219                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.797852                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.797852                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  828824                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 373673                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 270178                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          142.283862                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs             178830                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              172                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs          1039.709302                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.283862                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277898                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.277898                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          170                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.332031                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           720603                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          720603                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data        90862                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          90862                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        88053                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         88053                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           24                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             24                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       178915                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          178915                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       178915                       # number of overall hits
system.cpu0.dcache.overall_hits::total         178915                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          568                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          568                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          546                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          546                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           18                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           18                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1114                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1114                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1114                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1114                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16630000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     16630000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     35665989                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     35665989                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       490500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       490500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     52295989                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     52295989                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     52295989                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     52295989                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        91430                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        91430                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        88599                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        88599                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       180029                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       180029                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       180029                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       180029                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006212                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.006212                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006163                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.006163                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.428571                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.428571                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006188                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006188                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006188                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006188                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29278.169014                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 29278.169014                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65322.324176                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 65322.324176                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        27250                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total        27250                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46944.334829                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 46944.334829                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46944.334829                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 46944.334829                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          885                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    42.142857                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          370                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          370                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          375                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          375                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          745                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          745                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          745                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          745                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          198                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          198                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          171                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          171                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           18                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           18                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          369                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          369                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          369                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          369                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      7613500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      7613500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8176500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8176500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       472500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       472500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15790000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     15790000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15790000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     15790000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002166                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002166                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.001930                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.001930                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.428571                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002050                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002050                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002050                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002050                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38452.020202                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38452.020202                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47815.789474                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47815.789474                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        26250                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        26250                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42791.327913                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42791.327913                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42791.327913                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42791.327913                       # average overall mshr miss latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements              391                       # number of replacements
system.cpu0.icache.tags.tagsinuse          249.990139                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs               7433                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              696                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.679598                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   249.990139                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.488262                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.488262                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          305                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           44                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          193                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.595703                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses             9051                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses            9051                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst         7433                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           7433                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         7433                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            7433                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         7433                       # number of overall hits
system.cpu0.icache.overall_hits::total           7433                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          922                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          922                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          922                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           922                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          922                       # number of overall misses
system.cpu0.icache.overall_misses::total          922                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     48154500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     48154500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     48154500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     48154500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     48154500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     48154500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         8355                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         8355                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         8355                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         8355                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         8355                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         8355                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.110353                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.110353                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.110353                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.110353                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.110353                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.110353                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52228.308026                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 52228.308026                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52228.308026                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 52228.308026                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52228.308026                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 52228.308026                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs          401                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                8                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    50.125000                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks          391                       # number of writebacks
system.cpu0.icache.writebacks::total              391                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          225                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          225                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          225                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          225                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          225                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          225                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          697                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          697                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          697                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          697                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          697                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          697                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     36741500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     36741500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     36741500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     36741500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     36741500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     36741500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.083423                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.083423                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.083423                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.083423                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.083423                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.083423                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52713.773314                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52713.773314                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52713.773314                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 52713.773314                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52713.773314                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 52713.773314                       # average overall mshr miss latency
system.cpu1.branchPred.lookups                  67120                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            59252                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             2530                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               59078                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                   2033                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups          59078                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits             48199                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses           10879                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted         1412                       # Number of mispredicted indirect branches.
system.cpu1.pwrStateResidencyTicks::ON      125996000                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                          194937                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             38450                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        366689                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      67120                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             50232                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       144025                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   5215                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1847                       # Number of stall cycles due to pending traps
system.cpu1.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                    26490                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                 1009                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            186966                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.961260                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.371242                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   66801     35.73%     35.73% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   58781     31.44%     67.17% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    7398      3.96%     71.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3358      1.80%     72.92% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     642      0.34%     73.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   38588     20.64%     93.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1104      0.59%     94.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                    1446      0.77%     95.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    8848      4.73%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              186966                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.344316                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.881064                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   23546                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                62450                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    94215                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 4138                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2607                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                335701                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2607                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   24537                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  29865                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         13172                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    95090                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                21685                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                329147                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                 18681                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                    15                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands             231661                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               629076                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          489741                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups               26                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps               200931                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   30730                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1664                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1812                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    26977                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               90636                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              43093                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            42743                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           36583                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    268793                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               7661                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   268125                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued              136                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          26316                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        21262                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved          1168                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       186966                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.434084                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.397924                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              71753     38.38%     38.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              24944     13.34%     51.72% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              41684     22.29%     74.01% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              41301     22.09%     96.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3557      1.90%     98.01% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1804      0.96%     98.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6               1118      0.60%     99.57% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                486      0.26%     99.83% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                319      0.17%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         186966                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                    231     42.39%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMultAcc                0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMisc                   0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     42.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    72     13.21%     55.60% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  242     44.40%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               130845     48.80%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMultAcc              0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMisc                 0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.80% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               95251     35.52%     84.32% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              42029     15.68%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                268125                       # Type of FU issued
system.cpu1.iq.rate                          1.375444                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        545                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.002033                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            723897                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           302756                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       263753                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                52                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                268670                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           36498                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         4839                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses           41                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           38                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         2826                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2607                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   8495                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             320469                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              297                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                90636                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               43093                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1513                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    32                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            38                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           472                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         2728                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                3200                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               265301                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                88817                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             2824                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        44015                       # number of nop insts executed
system.cpu1.iew.exec_refs                      130506                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   54427                       # Number of branches executed
system.cpu1.iew.exec_stores                     41689                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.360958                       # Inst execution rate
system.cpu1.iew.wb_sent                        264333                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       263753                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   148277                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   156026                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      1.353017                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.950335                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts          27498                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           6493                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             2530                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       181716                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.612048                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.042470                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        77632     42.72%     42.72% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        50511     27.80%     70.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         5466      3.01%     73.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         7144      3.93%     77.46% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1253      0.69%     78.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        36670     20.18%     98.33% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          792      0.44%     98.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1038      0.57%     99.33% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8         1210      0.67%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       181716                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              292935                       # Number of instructions committed
system.cpu1.commit.committedOps                292935                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        126064                       # Number of memory references committed
system.cpu1.commit.loads                        85797                       # Number of loads committed
system.cpu1.commit.membars                       5779                       # Number of memory barriers committed
system.cpu1.commit.branches                     52007                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   200194                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass        42797     14.61%     14.61% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu          118295     40.38%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult              0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMultAcc            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMisc            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.99% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead          91576     31.26%     86.25% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite         40267     13.75%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total           292935                       # Class of committed instruction
system.cpu1.commit.bw_lim_events                 1210                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                      500353                       # The number of ROB reads
system.cpu1.rob.rob_writes                     646173                       # The number of ROB writes
system.cpu1.timesIdled                            229                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           7971                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       49399                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     244359                       # Number of Instructions Simulated
system.cpu1.committedOps                       244359                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              0.797748                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.797748                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.253528                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.253528                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  456218                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 213064                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 132445                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           27.060700                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              47652                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               31                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs          1537.161290                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    27.060700                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.052853                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.052853                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           31                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.060547                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           370474                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          370474                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data        51817                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          51817                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        40051                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         40051                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        91868                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           91868                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        91868                       # number of overall hits
system.cpu1.dcache.overall_hits::total          91868                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          471                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          471                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          148                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          148                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           54                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          619                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           619                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          619                       # number of overall misses
system.cpu1.dcache.overall_misses::total          619                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4841500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      4841500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3638000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3638000                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       309000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       309000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      8479500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      8479500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      8479500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      8479500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        52288                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        52288                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        40199                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        40199                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        92487                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        92487                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        92487                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        92487                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009008                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.009008                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003682                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.003682                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.794118                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.794118                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006693                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.006693                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006693                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.006693                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10279.193206                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 10279.193206                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24581.081081                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24581.081081                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  5722.222222                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  5722.222222                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13698.707593                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 13698.707593                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13698.707593                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13698.707593                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          312                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          312                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           44                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           44                       # number of WriteReq MSHR hits
system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data            1                       # number of SwapReq MSHR hits
system.cpu1.dcache.SwapReq_mshr_hits::total            1                       # number of SwapReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          356                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          356                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          356                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          356                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          159                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          159                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          104                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           53                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           53                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          263                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          263                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          263                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          263                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1599000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1599000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1536000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1536000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       255000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       255000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3135000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      3135000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3135000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      3135000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003041                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003041                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002587                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002587                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.779412                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.779412                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002844                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.002844                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002844                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.002844                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10056.603774                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10056.603774                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14769.230769                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14769.230769                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  4811.320755                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  4811.320755                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11920.152091                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11920.152091                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11920.152091                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11920.152091                       # average overall mshr miss latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements              598                       # number of replacements
system.cpu1.icache.tags.tagsinuse           99.304712                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs              25606                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              733                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            34.933151                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    99.304712                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.193955                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.193955                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           14                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.263672                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses            27223                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses           27223                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst        25606                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          25606                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        25606                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           25606                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        25606                       # number of overall hits
system.cpu1.icache.overall_hits::total          25606                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          884                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          884                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          884                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           884                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          884                       # number of overall misses
system.cpu1.icache.overall_misses::total          884                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     21315000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     21315000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     21315000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     21315000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     21315000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     21315000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        26490                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        26490                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        26490                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        26490                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        26490                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        26490                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.033371                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.033371                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.033371                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.033371                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.033371                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.033371                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24111.990950                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 24111.990950                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24111.990950                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 24111.990950                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24111.990950                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 24111.990950                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          175                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                5                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs           35                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks          598                       # number of writebacks
system.cpu1.icache.writebacks::total              598                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst          151                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total          151                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst          151                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total          151                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst          151                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total          151                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          733                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          733                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          733                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          733                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          733                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          733                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     16848000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total     16848000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     16848000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total     16848000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     16848000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total     16848000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027671                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027671                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027671                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.027671                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027671                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.027671                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22984.993179                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22984.993179                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22984.993179                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 22984.993179                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22984.993179                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 22984.993179                       # average overall mshr miss latency
system.cpu2.branchPred.lookups                  65968                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            58235                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             2375                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               57871                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                   1935                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups          57871                       # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits             47609                       # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses           10262                       # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted         1269                       # Number of mispredicted indirect branches.
system.cpu2.pwrStateResidencyTicks::ON      125996000                       # Cumulative time (in ticks) in various power states
system.cpu2.numCycles                          194536                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             39274                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        356927                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      65968                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             49544                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       148178                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   4907                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1834                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    28474                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  909                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            191752                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.861399                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.326800                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   72282     37.70%     37.70% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   59093     30.82%     68.51% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    8567      4.47%     72.98% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3453      1.80%     74.78% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     714      0.37%     75.15% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   36701     19.14%     94.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1094      0.57%     94.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                    1368      0.71%     95.58% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    8480      4.42%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              191752                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.339104                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.834761                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   22274                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                72146                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    90170                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 4699                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2453                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                325978                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2453                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   23346                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  35274                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         13410                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    90655                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                26604                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                319217                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                 22687                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents               2                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands             222060                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               604225                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          470469                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               26                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps               194795                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   27265                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1650                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1793                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    32366                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               87706                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              41007                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            42125                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           34727                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    259651                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               8925                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   260809                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               82                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          24016                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        18768                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved          1234                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       191752                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.360137                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.380681                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              77057     40.19%     40.19% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              28387     14.80%     54.99% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              39839     20.78%     75.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              39454     20.58%     96.34% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3531      1.84%     98.18% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1665      0.87%     99.05% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6               1093      0.57%     99.62% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                433      0.23%     99.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                293      0.15%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         191752                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                    214     43.32%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMultAcc                0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMisc                   0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     43.32% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    44      8.91%     52.23% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  236     47.77%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               127216     48.78%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMultAcc              0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMisc                 0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.78% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               93561     35.87%     84.65% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              40032     15.35%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                260809                       # Type of FU issued
system.cpu2.iq.rate                          1.340672                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        494                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001894                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            713946                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           292577                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       257120                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                52                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                261303                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           34638                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         4387                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses           24                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         2568                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2453                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   9291                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   57                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             312015                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              352                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                87706                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               41007                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1521                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    36                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            37                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           454                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         2525                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                2979                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               258429                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                86072                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             2380                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        43439                       # number of nop insts executed
system.cpu2.iew.exec_refs                      125830                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   53606                       # Number of branches executed
system.cpu2.iew.exec_stores                     39758                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.328438                       # Inst execution rate
system.cpu2.iew.wb_sent                        257596                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       257120                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   143610                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   151220                       # num instructions consuming a value
system.cpu2.iew.wb_rate                      1.321709                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.949676                       # average fanout of values written-back
system.cpu2.commit.commitSquashedInsts          25270                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           7691                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             2375                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       186904                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.534044                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.009689                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        84130     45.01%     45.01% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        49844     26.67%     71.68% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         5407      2.89%     74.57% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         8359      4.47%     79.05% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1323      0.71%     79.75% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        34855     18.65%     98.40% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          714      0.38%     98.78% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1043      0.56%     99.34% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8         1229      0.66%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       186904                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              286719                       # Number of instructions committed
system.cpu2.commit.committedOps                286719                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        121758                       # Number of memory references committed
system.cpu2.commit.loads                        83319                       # Number of loads committed
system.cpu2.commit.membars                       6971                       # Number of memory barriers committed
system.cpu2.commit.branches                     51375                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   195248                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        42159     14.70%     14.70% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu          115831     40.40%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMultAcc            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMisc            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.10% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead          90290     31.49%     86.59% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite         38439     13.41%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total           286719                       # Class of committed instruction
system.cpu2.commit.bw_lim_events                 1229                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                      497078                       # The number of ROB reads
system.cpu2.rob.rob_writes                     628878                       # The number of ROB writes
system.cpu2.timesIdled                            227                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           2784                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       49801                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     237589                       # Number of Instructions Simulated
system.cpu2.committedOps                       237589                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              0.818792                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.818792                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.221311                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.221311                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  441330                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 205867                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 127741                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           25.326014                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              45457                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1567.482759                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    25.326014                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.049465                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.049465                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           359653                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          359653                       # Number of data accesses
system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu2.dcache.ReadReq_hits::cpu2.data        50904                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          50904                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        38221                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         38221                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           12                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        89125                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           89125                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        89125                       # number of overall hits
system.cpu2.dcache.overall_hits::total          89125                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          505                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          505                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          144                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          144                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           62                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           62                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          649                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           649                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          649                       # number of overall misses
system.cpu2.dcache.overall_misses::total          649                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      3857000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      3857000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3021500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      3021500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       367000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       367000                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      6878500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      6878500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      6878500                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      6878500                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        51409                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        51409                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        38365                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        38365                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           74                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           74                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        89774                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        89774                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        89774                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        89774                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.009823                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.009823                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003753                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.003753                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.837838                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.837838                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007229                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.007229                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007229                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.007229                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data  7637.623762                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total  7637.623762                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20982.638889                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 20982.638889                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  5919.354839                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  5919.354839                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10598.613251                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 10598.613251                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10598.613251                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 10598.613251                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          337                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          337                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           41                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           41                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          378                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          378                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          378                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          378                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          168                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          168                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          103                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          103                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           62                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           62                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          271                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          271                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          271                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          271                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1115500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1115500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1450500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1450500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       305000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       305000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      2566000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      2566000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      2566000                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      2566000                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003268                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003268                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002685                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002685                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.837838                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.837838                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003019                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.003019                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003019                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.003019                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  6639.880952                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  6639.880952                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14082.524272                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14082.524272                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  4919.354839                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  4919.354839                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data  9468.634686                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total  9468.634686                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data  9468.634686                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total  9468.634686                       # average overall mshr miss latency
system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements              551                       # number of replacements
system.cpu2.icache.tags.tagsinuse           96.895068                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs              27659                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              687                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs            40.260553                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    96.895068                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.189248                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.189248                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024          136                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.265625                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses            29161                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses           29161                       # Number of data accesses
system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu2.icache.ReadReq_hits::cpu2.inst        27659                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          27659                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        27659                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           27659                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        27659                       # number of overall hits
system.cpu2.icache.overall_hits::total          27659                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          815                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          815                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          815                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           815                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          815                       # number of overall misses
system.cpu2.icache.overall_misses::total          815                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     12882000                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     12882000                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     12882000                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     12882000                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     12882000                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     12882000                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        28474                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        28474                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        28474                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        28474                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        28474                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        28474                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.028623                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.028623                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.028623                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.028623                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.028623                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.028623                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15806.134969                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 15806.134969                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15806.134969                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 15806.134969                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15806.134969                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 15806.134969                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs           48                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs           24                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.writebacks::writebacks          551                       # number of writebacks
system.cpu2.icache.writebacks::total              551                       # number of writebacks
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst          128                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total          128                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst          128                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total          128                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst          128                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total          128                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          687                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          687                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          687                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          687                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          687                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          687                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     10903000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total     10903000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     10903000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total     10903000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     10903000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total     10903000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.024127                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.024127                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.024127                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.024127                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.024127                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.024127                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15870.451237                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15870.451237                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15870.451237                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 15870.451237                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15870.451237                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 15870.451237                       # average overall mshr miss latency
system.cpu3.branchPred.lookups                  64271                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            56758                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             2271                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               55794                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                   1884                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups          55794                       # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits             46245                       # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses            9549                       # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted         1200                       # Number of mispredicted indirect branches.
system.cpu3.pwrStateResidencyTicks::ON      125996000                       # Cumulative time (in ticks) in various power states
system.cpu3.numCycles                          194168                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             40168                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        346607                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      64271                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             48129                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       146969                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   4697                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1673                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    29039                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  911                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            191171                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.813073                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.312592                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   74400     38.92%     38.92% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   57993     30.34%     69.25% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    8887      4.65%     73.90% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3426      1.79%     75.69% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     613      0.32%     76.02% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   35081     18.35%     94.37% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1105      0.58%     94.94% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                    1253      0.66%     95.60% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    8413      4.40%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              191171                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.331007                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.785088                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   21895                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                75534                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    86562                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 4822                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2348                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                316867                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2348                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   22878                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  37474                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         13003                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    86814                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                28644                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                310654                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                 24310                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                    15                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.RenamedOperands             215725                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               585696                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          456528                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups               32                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps               188410                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   27315                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1561                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1705                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    33909                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               84645                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              39227                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            40799                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           33015                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    251387                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               9227                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   253114                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued               79                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          23294                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        18618                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved          1117                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       191171                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.324019                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.377234                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              78925     41.29%     41.29% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              29485     15.42%     56.71% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              37890     19.82%     76.53% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              37772     19.76%     96.29% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3652      1.91%     98.20% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1740      0.91%     99.11% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6               1013      0.53%     99.64% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                405      0.21%     99.85% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                289      0.15%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         191171                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                    186     40.88%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMultAcc                0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMisc                   0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     40.88% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    39      8.57%     49.45% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  230     50.55%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               123835     48.92%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMultAcc              0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMisc                 0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.92% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               91015     35.96%     84.88% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              38264     15.12%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                253114                       # Type of FU issued
system.cpu3.iq.rate                          1.303582                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        455                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001798                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            697933                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           283879                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       249400                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                64                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                253569                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           32960                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         4297                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses           40                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           35                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         2496                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2348                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   9647                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   50                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             302650                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              426                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                84645                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               39227                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1449                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    30                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            35                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           408                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         2445                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                2853                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               250680                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                83030                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             2434                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        42036                       # number of nop insts executed
system.cpu3.iew.exec_refs                      121032                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   52206                       # Number of branches executed
system.cpu3.iew.exec_stores                     38002                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.291047                       # Inst execution rate
system.cpu3.iew.wb_sent                        249859                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       249400                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   138774                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   146167                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      1.284455                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.949421                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts          24422                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           8110                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             2271                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       186514                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.491588                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.991895                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        86424     46.34%     46.34% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        48393     25.95%     72.28% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         5395      2.89%     75.18% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         8809      4.72%     79.90% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1333      0.71%     80.61% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        33156     17.78%     98.39% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          761      0.41%     98.80% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1030      0.55%     99.35% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8         1213      0.65%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       186514                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              278202                       # Number of instructions committed
system.cpu3.commit.committedOps                278202                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                        117079                       # Number of memory references committed
system.cpu3.commit.loads                        80348                       # Number of loads committed
system.cpu3.commit.membars                       7398                       # Number of memory barriers committed
system.cpu3.commit.branches                     50090                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   189293                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass        40882     14.70%     14.70% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu          112843     40.56%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult              0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMultAcc            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMisc            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.26% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead          87746     31.54%     86.80% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite         36731     13.20%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total           278202                       # Class of committed instruction
system.cpu3.commit.bw_lim_events                 1213                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                      487339                       # The number of ROB reads
system.cpu3.rob.rob_writes                     609957                       # The number of ROB writes
system.cpu3.timesIdled                            210                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           2997                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       50169                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     229922                       # Number of Instructions Simulated
system.cpu3.committedOps                       229922                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              0.844495                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.844495                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.184140                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.184140                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  426644                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 199085                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 122920                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           24.889715                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              43728                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs          1457.600000                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.889715                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.048613                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.048613                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           347346                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          347346                       # Number of data accesses
system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu3.dcache.ReadReq_hits::cpu3.data        49561                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          49561                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        36521                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         36521                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        86082                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           86082                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        86082                       # number of overall hits
system.cpu3.dcache.overall_hits::total          86082                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          482                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          482                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          144                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          144                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           52                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          626                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           626                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          626                       # number of overall misses
system.cpu3.dcache.overall_misses::total          626                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4340000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      4340000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3297000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      3297000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       320500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       320500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      7637000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      7637000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      7637000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      7637000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        50043                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        50043                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        36665                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        36665                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           66                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        86708                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        86708                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        86708                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        86708                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.009632                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.009632                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003927                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.003927                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.787879                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.787879                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007220                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.007220                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007220                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.007220                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data  9004.149378                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total  9004.149378                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22895.833333                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 22895.833333                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  6163.461538                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  6163.461538                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12199.680511                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 12199.680511                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12199.680511                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 12199.680511                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          322                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          322                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           40                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           40                       # number of WriteReq MSHR hits
system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data            1                       # number of SwapReq MSHR hits
system.cpu3.dcache.SwapReq_mshr_hits::total            1                       # number of SwapReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          362                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          362                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          362                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          362                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          160                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          160                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          104                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           51                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          264                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          264                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          264                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          264                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1241000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1241000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1631000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1631000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       268500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       268500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2872000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2872000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2872000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2872000                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003197                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003197                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002836                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002836                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.772727                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.772727                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003045                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003045                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003045                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003045                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  7756.250000                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  7756.250000                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15682.692308                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15682.692308                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  5264.705882                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  5264.705882                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10878.787879                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10878.787879                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10878.787879                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10878.787879                       # average overall mshr miss latency
system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements              575                       # number of replacements
system.cpu3.icache.tags.tagsinuse           93.289458                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs              28201                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              712                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs            39.608146                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    93.289458                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.182206                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.182206                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024          137                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1          109                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.267578                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses            29751                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses           29751                       # Number of data accesses
system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.cpu3.icache.ReadReq_hits::cpu3.inst        28201                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          28201                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        28201                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           28201                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        28201                       # number of overall hits
system.cpu3.icache.overall_hits::total          28201                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          838                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          838                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          838                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           838                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          838                       # number of overall misses
system.cpu3.icache.overall_misses::total          838                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     13273000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total     13273000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst     13273000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total     13273000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst     13273000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total     13273000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        29039                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        29039                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        29039                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        29039                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        29039                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        29039                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.028858                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.028858                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.028858                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.028858                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.028858                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.028858                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15838.902148                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 15838.902148                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15838.902148                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 15838.902148                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15838.902148                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 15838.902148                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.writebacks::writebacks          575                       # number of writebacks
system.cpu3.icache.writebacks::total              575                       # number of writebacks
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst          126                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total          126                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst          126                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total          126                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst          126                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total          126                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          712                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          712                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          712                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          712                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          712                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          712                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     11453500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total     11453500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     11453500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total     11453500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     11453500                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total     11453500                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.024519                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.024519                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.024519                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.024519                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.024519                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.024519                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 16086.376404                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 16086.376404                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 16086.376404                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 16086.376404                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 16086.376404                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 16086.376404                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  566.450222                       # Cycle average of tags in use
system.l2c.tags.total_refs                       3196                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      710                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.501408                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::cpu0.inst      300.277327                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data      144.720872                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst       69.261985                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       16.352170                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst        9.533779                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data       10.075907                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        5.908934                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data       10.319248                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::cpu0.inst       0.004582                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.002208                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.001057                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000250                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000145                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000154                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000090                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000157                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.008643                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          710                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          513                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.010834                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    32110                       # Number of tag accesses
system.l2c.tags.data_accesses                   32110                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks          757                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total             757                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              22                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              20                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              21                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data              21                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  84                       # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst           321                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst           637                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst           664                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst           699                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total              2321                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst                 321                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 637                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 664                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 699                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    2353                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                321                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                637                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                664                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                699                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   2353                       # number of overall hits
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst          376                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst           96                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst           23                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst           13                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total             508                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data           76                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data            9                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data            3                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total             90                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst               376                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               170                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                96                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                22                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                23                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                15                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   729                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              376                       # number of overall misses
system.l2c.overall_misses::cpu0.data              170                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               96                       # number of overall misses
system.l2c.overall_misses::cpu1.data               22                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               23                       # number of overall misses
system.l2c.overall_misses::cpu2.data               14                       # number of overall misses
system.l2c.overall_misses::cpu3.inst               13                       # number of overall misses
system.l2c.overall_misses::cpu3.data               15                       # number of overall misses
system.l2c.overall_misses::total                  729                       # number of overall misses
system.l2c.ReadExReq_miss_latency::cpu0.data      7962500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data      1106000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data      1022500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data      1199500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total     11290500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst     32133500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst      8531500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst      2347000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst      2460500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total     45472500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data      6902500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data       767000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data       179000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data       339000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total      8187500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     32133500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     14865000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      8531500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1873000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      2347000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1201500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst      2460500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data      1538500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        64950500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     32133500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     14865000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      8531500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1873000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      2347000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1201500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst      2460500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data      1538500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       64950500                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks          757                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total          757                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              84                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst          697                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst          733                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst          687                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst          712                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total          2829                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data           81                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data           14                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data           14                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total          122                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             697                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             175                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             733                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              27                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             687                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             712                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                3082                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            697                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            175                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            733                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             27                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            687                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            712                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               3082                       # number of overall (read+write) accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.539455                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.130969                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.033479                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.018258                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.179569                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.938272                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.642857                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.153846                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.214286                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.737705                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.539455                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971429                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.130969                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.814815                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.033479                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.560000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.018258                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.576923                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.236535                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.539455                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971429                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.130969                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.814815                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.033479                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.560000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.018258                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.576923                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.236535                       # miss rate for overall accesses
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84707.446809                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 85076.923077                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 85208.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 99958.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 86187.022901                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 85461.436170                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 88869.791667                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 102043.478261                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 189269.230769                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 89512.795276                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90822.368421                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 85222.222222                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        89500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data       113000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 90972.222222                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 85461.436170                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 87441.176471                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 88869.791667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 85136.363636                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 102043.478261                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 85821.428571                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 189269.230769                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 102566.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 89095.336077                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 85461.436170                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 87441.176471                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 88869.791667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 85136.363636                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 102043.478261                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 85821.428571                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 189269.230769                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 102566.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 89095.336077                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            2                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            9                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            3                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           18                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          374                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           92                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           14                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst           10                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total          490                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data           76                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data            9                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data            3                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total           90                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          374                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          170                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           92                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           22                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              711                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          374                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          170                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           92                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           22                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             711                       # number of overall MSHR misses
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      7022500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       976000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       902500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      1079500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      9980500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     28295000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      7392500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      1074500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst      1591500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total     38353500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      6142500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       677000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       159000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data       309000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total      7287500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     28295000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     13165000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      7392500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data      1653000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      1074500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1061500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst      1591500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data      1388500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     55621500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     28295000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     13165000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      7392500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data      1653000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      1074500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1061500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst      1591500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data      1388500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     55621500                       # number of overall MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.536585                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.125512                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.020378                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.014045                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.173206                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.938272                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.642857                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.153846                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.214286                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.737705                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.536585                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.125512                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.814815                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.020378                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.560000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.014045                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.576923                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.230694                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.536585                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971429                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.125512                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.814815                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.020378                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.560000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.014045                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.576923                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.230694                       # mshr miss rate for overall accesses
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74707.446809                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 75076.923077                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75208.333333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89958.333333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 76187.022901                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75655.080214                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80353.260870                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst        76750                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst       159150                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 78272.448980                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80822.368421                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75222.222222                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        79500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data       103000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80972.222222                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75655.080214                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77441.176471                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80353.260870                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75136.363636                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        76750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 75821.428571                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst       159150                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 92566.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 78229.957806                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75655.080214                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77441.176471                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80353.260870                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75136.363636                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        76750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 75821.428571                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst       159150                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 92566.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 78229.957806                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests           961                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests          251                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                579                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              193                       # Transaction distribution
system.membus.trans_dist::ReadExReq               189                       # Transaction distribution
system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           579                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1671                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1671                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        45440                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   45440                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              251                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               961                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     961    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 961                       # Request fanout histogram
system.membus.reqLayer0.occupancy              879000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3778500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.0                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests         6307                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests         1711                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         3247                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED    125996000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp              3510                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean         2115                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             277                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            277                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              399                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             399                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq          2829                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq          685                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1784                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          594                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         2064                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          364                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1925                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          379                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1999                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          363                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  9472                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        69568                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11264                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        85184                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1728                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        79232                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        82368                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total                 332608                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                            1024                       # Total snoops (count)
system.toL2Bus.snoopTraffic                     53184                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples             4190                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.302625                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.130775                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                   1349     32.20%     32.20% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                   1111     26.52%     58.71% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    843     20.12%     78.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                    887     21.17%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total               4190                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy            5284470                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              4.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy           1044996                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy            522995                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           1103492                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.9                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy            425474                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy           1034985                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy            441461                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           1070994                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.9                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy            421970                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------