path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000124                       # Number of seconds simulated
sim_ticks                                   123756000                       # Number of ticks simulated
final_tick                                  123756000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 286843                       # Simulator instruction rate (inst/s)
host_op_rate                                   286842                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               31050897                       # Simulator tick rate (ticks/s)
host_mem_usage                                 266468                       # Number of bytes of host memory used
host_seconds                                     3.99                       # Real time elapsed on the host
sim_insts                                     1143228                       # Number of instructions simulated
sim_ops                                       1143228                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst            23616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             6016                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              896                       # Number of bytes read from this memory
system.physmem.bytes_read::total                45248                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        23616                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         6016                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          768                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          832                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           31232                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               369                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               169                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                94                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                22                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                12                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                14                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   707                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           190827111                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            87397783                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            48611784                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            11377226                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             6205760                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7240053                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             6722906                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7240053                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               365622677                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      190827111                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       48611784                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        6205760                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        6722906                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          252367562                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          190827111                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           87397783                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           48611784                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           11377226                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            6205760                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7240053                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            6722906                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7240053                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              365622677                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           707                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         707                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    45248                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     45248                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 118                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  45                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  32                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  63                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  69                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  27                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  19                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  27                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  29                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 70                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 47                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 18                       # Per bank write bursts
system.physmem.perBankRdBursts::15                100                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                       123516000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     707                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       412                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       215                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          169                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      251.834320                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     169.411435                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     244.318432                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             58     34.32%     34.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           48     28.40%     62.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           26     15.38%     78.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           12      7.10%     85.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            7      4.14%     89.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            7      4.14%     93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            4      2.37%     95.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            1      0.59%     96.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            6      3.55%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            169                       # Bytes accessed per row activation
system.physmem.totQLat                       11450750                       # Total ticks spent queuing
system.physmem.totMemAccLat                  24707000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3535000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       16196.25                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34946.25                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         365.62                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      365.62                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.86                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.86                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.29                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        529                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.82                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       174704.38                       # Average gap between requests
system.physmem.pageHitRate                      74.82                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     835380                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     428835                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   2856000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           9219600.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy                6260880                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                 309600                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy          30851820                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy          11364960                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy            3424140                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy                 65551215                       # Total energy per rank (pJ)
system.physmem_0.averagePower              529.680036                       # Core power per rank (mW)
system.physmem_0.totalIdleTime              108655750                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE         358500                       # Time in different power states
system.physmem_0.memoryStateTime::REF         3906000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF       11965500                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN     29593750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        10265500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN     67666750                       # Time in different power states
system.physmem_1.actEnergy                     435540                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     212520                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   2191980                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           7375680.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy                4628970                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                 469440                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy          25813590                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy           8390400                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy            8693940                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy                 58212060                       # Total energy per rank (pJ)
system.physmem_1.averagePower              470.376728                       # Core power per rank (mW)
system.physmem_1.totalIdleTime              112190500                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE         843500                       # Time in different power states
system.physmem_1.memoryStateTime::REF         3126000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF       33923000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN     21849000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT         7402250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN     56612250                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu0.branchPred.lookups                  96945                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            92664                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1460                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               94281                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                   1072                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups          94281                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits             87442                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses            6839                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted          944                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.workload.numSyscalls                   89                       # Number of system calls
system.cpu0.pwrStateResidencyTicks::ON      123756000                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                          247513                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             22810                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        572402                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      96945                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             88514                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       191239                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3219                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.MiscStallCycles                   9                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         2152                       # Number of stall cycles due to pending traps
system.cpu0.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                     7601                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  796                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            217827                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.627783                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.257744                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   33416     15.34%     15.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   90280     41.45%     56.79% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     662      0.30%     57.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                    1022      0.47%     57.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     476      0.22%     57.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   86076     39.52%     97.29% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     627      0.29%     97.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     458      0.21%     97.79% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    4810      2.21%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              217827                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.391676                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.312614                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   17128                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                19348                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   178981                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  761                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  1609                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                555305                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  1609                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   17781                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   1772                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         16195                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   179089                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                 1381                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                550438                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                    11                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents                   925                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands             376177                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups              1097223                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          828510                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               359139                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   17038                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts              1047                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts          1085                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     5185                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              175971                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              88955                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            85967                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           85657                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    459427                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded               1094                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   455664                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued               95                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          15166                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        12611                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           535                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       217827                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.091862                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.108022                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              36217     16.63%     16.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4343      1.99%     18.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              87095     39.98%     58.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              86709     39.81%     98.41% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1627      0.75%     99.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                960      0.44%     99.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                547      0.25%     99.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                218      0.10%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                111      0.05%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         217827                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                    123     36.94%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMultAcc                0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMisc                   0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     36.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    85     25.53%     62.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  125     37.54%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               192140     42.17%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMultAcc              0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMisc                 0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.17% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              175355     38.48%     80.65% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              88169     19.35%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                455664                       # Type of FU issued
system.cpu0.iq.rate                          1.840970                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        333                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000731                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1129583                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           475739                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       453318                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                455997                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           85314                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2812                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1869                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           12                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  1609                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   1760                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   31                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             547045                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              114                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               175971                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               88955                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               969                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    34                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           211                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1555                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1766                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               454327                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               175012                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1337                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        86524                       # number of nop insts executed
system.cpu0.iew.exec_refs                      262985                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   90247                       # Number of branches executed
system.cpu0.iew.exec_stores                     87973                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.835568                       # Inst execution rate
system.cpu0.iew.wb_sent                        453748                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       453318                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   268984                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   272473                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      1.831492                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.987195                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts          15911                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1460                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       214699                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.473509                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.143772                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        36174     16.85%     16.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        89113     41.51%     58.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         1996      0.93%     59.28% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          609      0.28%     59.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          464      0.22%     59.78% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        85076     39.63%     99.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          476      0.22%     99.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          292      0.14%     99.77% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          499      0.23%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       214699                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              531060                       # Number of instructions committed
system.cpu0.commit.committedOps                531060                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        260245                       # Number of memory references committed
system.cpu0.commit.loads                       173159                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     88973                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   357470                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass        85705     16.14%     16.14% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu          185026     34.84%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult              0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMultAcc            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMisc            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     50.98% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead         173243     32.62%     83.60% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite         87086     16.40%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total           531060                       # Class of committed instruction
system.cpu0.commit.bw_lim_events                  499                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                      760010                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1097116                       # The number of ROB writes
system.cpu0.timesIdled                            319                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          29686                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     445271                       # Number of Instructions Simulated
system.cpu0.committedOps                       445271                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              0.555870                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.555870                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.798980                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.798980                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  812559                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 366073                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 265038                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          142.111163                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs             175455                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              171                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs          1026.052632                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.111163                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277561                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.277561                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.330078                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           707079                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          707079                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data        89048                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          89048                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        86492                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         86492                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           18                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             18                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       175540                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          175540                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       175540                       # number of overall hits
system.cpu0.dcache.overall_hits::total         175540                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          556                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          556                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          552                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          552                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           24                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           24                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1108                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1108                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1108                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1108                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     15680500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     15680500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     35675489                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     35675489                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       524500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       524500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     51355989                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     51355989                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     51355989                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     51355989                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        89604                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        89604                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        87044                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        87044                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       176648                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       176648                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       176648                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       176648                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006205                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.006205                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006342                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.006342                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.571429                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.571429                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006272                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006272                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006272                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006272                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28202.338129                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 28202.338129                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64629.509058                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 64629.509058                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 21854.166667                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 21854.166667                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46350.170578                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 46350.170578                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46350.170578                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 46350.170578                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          885                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    42.142857                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          364                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          364                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          379                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          379                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          743                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          743                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          743                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          743                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          192                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          192                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          173                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          173                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           24                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           24                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          365                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          365                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          365                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      7301500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      7301500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8155500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8155500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       500500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       500500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15457000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     15457000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15457000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     15457000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002143                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002143                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.001988                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.001988                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.571429                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.571429                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002066                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002066                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002066                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002066                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38028.645833                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38028.645833                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47141.618497                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47141.618497                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 20854.166667                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 20854.166667                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42347.945205                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42347.945205                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42347.945205                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42347.945205                       # average overall mshr miss latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements              381                       # number of replacements
system.cpu0.icache.tags.tagsinuse          247.076486                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs               6698                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              681                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             9.835536                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   247.076486                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.482571                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.482571                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          300                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          177                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.585938                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses             8282                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses            8282                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst         6698                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           6698                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         6698                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            6698                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         6698                       # number of overall hits
system.cpu0.icache.overall_hits::total           6698                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          903                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          903                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          903                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           903                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          903                       # number of overall misses
system.cpu0.icache.overall_misses::total          903                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     46390500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     46390500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     46390500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     46390500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     46390500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     46390500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         7601                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         7601                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         7601                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         7601                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         7601                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         7601                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.118800                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.118800                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.118800                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.118800                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.118800                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.118800                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51373.754153                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 51373.754153                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51373.754153                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 51373.754153                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51373.754153                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 51373.754153                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs           84                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                3                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs           28                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks          381                       # number of writebacks
system.cpu0.icache.writebacks::total              381                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          221                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          221                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          221                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          221                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          221                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          221                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          682                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          682                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          682                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          682                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          682                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          682                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     35207000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     35207000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     35207000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     35207000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     35207000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     35207000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.089725                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.089725                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.089725                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.089725                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.089725                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.089725                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51623.167155                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51623.167155                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51623.167155                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 51623.167155                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51623.167155                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 51623.167155                       # average overall mshr miss latency
system.cpu1.branchPred.lookups                  61334                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            54401                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             2004                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               54412                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                   1793                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups          54412                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits             44729                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses            9683                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted          984                       # Number of mispredicted indirect branches.
system.cpu1.pwrStateResidencyTicks::ON      123756000                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                          189559                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             38670                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        332272                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      61334                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             46522                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       140422                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   4165                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles                   6                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1456                       # Number of stall cycles due to pending traps
system.cpu1.fetch.IcacheWaitRetryStallCycles           38                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                    27652                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  879                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            182684                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.818835                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.303785                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   70336     38.50%     38.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   55803     30.55%     69.05% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    8540      4.67%     73.72% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3408      1.87%     75.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     651      0.36%     75.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   33906     18.56%     94.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                     999      0.55%     95.05% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                    1291      0.71%     95.76% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    7750      4.24%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              182684                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.323562                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.752869                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   21125                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                71097                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    83834                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 4536                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2082                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                303611                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2082                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   22030                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  34668                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         13321                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    84450                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                26123                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                298128                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                 22342                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                    13                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands             207771                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               563979                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          439786                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups               36                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps               183614                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   24157                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1533                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1680                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    31315                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               81609                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              38032                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            39208                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           31953                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    243349                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               8714                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   245236                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               76                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          21657                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        16615                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved          1128                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       182684                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.342405                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.387446                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              74656     40.87%     40.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              27751     15.19%     56.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              36635     20.05%     76.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              36634     20.05%     96.16% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3526      1.93%     98.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1704      0.93%     99.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6               1046      0.57%     99.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                443      0.24%     99.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                289      0.16%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         182684                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                    163     36.88%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMultAcc                0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMisc                   0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     36.88% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    52     11.76%     48.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  227     51.36%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               120474     49.13%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMultAcc              0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMisc                 0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.13% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               87542     35.70%     84.82% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              37220     15.18%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                245236                       # Type of FU issued
system.cpu1.iq.rate                          1.293719                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        442                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001802                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            673674                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           273687                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       241932                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                72                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                245678                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           31875                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         3921                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses           28                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         2368                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2082                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   9074                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   53                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             292335                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              184                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                81609                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               38032                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1451                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    28                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            39                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           411                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         2165                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                2576                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               243135                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                80226                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             2101                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        40272                       # number of nop insts executed
system.cpu1.iew.exec_refs                      117151                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   50431                       # Number of branches executed
system.cpu1.iew.exec_stores                     36925                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.282635                       # Inst execution rate
system.cpu1.iew.wb_sent                        242358                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       241932                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   135113                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   142615                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      1.276289                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.947397                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts          22606                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           7586                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             2004                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       178491                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.510961                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.003537                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        81773     45.81%     45.81% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        46692     26.16%     71.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         5286      2.96%     74.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         8258      4.63%     79.56% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1311      0.73%     80.30% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        32106     17.99%     98.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          812      0.45%     98.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1015      0.57%     99.31% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8         1238      0.69%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       178491                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              269693                       # Number of instructions committed
system.cpu1.commit.committedOps                269693                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        113352                       # Number of memory references committed
system.cpu1.commit.loads                        77688                       # Number of loads committed
system.cpu1.commit.membars                       6874                       # Number of memory barriers committed
system.cpu1.commit.branches                     48495                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   183974                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass        39287     14.57%     14.57% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu          110180     40.85%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMultAcc            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMisc            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.42% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead          84562     31.35%     86.78% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite         35664     13.22%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total           269693                       # Class of committed instruction
system.cpu1.commit.bw_lim_events                 1238                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                      468966                       # The number of ROB reads
system.cpu1.rob.rob_writes                     588835                       # The number of ROB writes
system.cpu1.timesIdled                            217                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           6875                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       49435                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     223532                       # Number of Instructions Simulated
system.cpu1.committedOps                       223532                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              0.848017                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.848017                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.179221                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.179221                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  414823                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 193738                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 118957                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           26.585143                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              42712                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               31                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs          1377.806452                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.585143                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.051924                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.051924                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           31                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.060547                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           336213                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          336213                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data        47868                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          47868                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        35447                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         35447                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           16                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        83315                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           83315                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        83315                       # number of overall hits
system.cpu1.dcache.overall_hits::total          83315                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          458                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          458                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          151                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          151                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           50                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           50                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          609                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           609                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          609                       # number of overall misses
system.cpu1.dcache.overall_misses::total          609                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4693000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      4693000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3635500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3635500                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       328500                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       328500                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      8328500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      8328500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      8328500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      8328500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        48326                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        48326                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        35598                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        35598                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           66                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        83924                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        83924                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        83924                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        83924                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009477                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.009477                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004242                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.004242                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.757576                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.757576                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007257                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.007257                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007257                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.007257                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10246.724891                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 10246.724891                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24076.158940                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24076.158940                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data         6570                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total         6570                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13675.697865                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 13675.697865                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13675.697865                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13675.697865                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          292                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          292                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           47                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           47                       # number of WriteReq MSHR hits
system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data            4                       # number of SwapReq MSHR hits
system.cpu1.dcache.SwapReq_mshr_hits::total            4                       # number of SwapReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          339                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          339                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          339                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          339                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          166                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          166                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          104                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           46                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           46                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          270                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          270                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1641000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1641000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1541000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1541000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       278500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       278500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3182000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      3182000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3182000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      3182000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003435                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003435                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002922                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002922                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.696970                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.696970                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003217                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.003217                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003217                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.003217                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  9885.542169                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  9885.542169                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14817.307692                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14817.307692                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  6054.347826                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  6054.347826                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11785.185185                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11785.185185                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11785.185185                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11785.185185                       # average overall mshr miss latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements              507                       # number of replacements
system.cpu1.icache.tags.tagsinuse           97.467355                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs              26848                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              643                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            41.754277                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    97.467355                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.190366                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.190366                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          136                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          114                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.265625                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses            28295                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses           28295                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst        26848                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          26848                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        26848                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           26848                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        26848                       # number of overall hits
system.cpu1.icache.overall_hits::total          26848                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          804                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          804                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          804                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           804                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          804                       # number of overall misses
system.cpu1.icache.overall_misses::total          804                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     19785000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     19785000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     19785000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     19785000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     19785000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     19785000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        27652                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        27652                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        27652                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        27652                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        27652                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        27652                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029076                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.029076                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029076                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.029076                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029076                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.029076                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24608.208955                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 24608.208955                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24608.208955                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 24608.208955                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24608.208955                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 24608.208955                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          207                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                6                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    34.500000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks          507                       # number of writebacks
system.cpu1.icache.writebacks::total              507                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst          161                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total          161                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst          161                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total          161                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst          161                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total          161                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          643                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          643                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          643                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          643                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          643                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          643                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     15397000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total     15397000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     15397000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total     15397000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     15397000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total     15397000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023253                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023253                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023253                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.023253                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023253                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.023253                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23945.567652                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23945.567652                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23945.567652                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 23945.567652                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23945.567652                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 23945.567652                       # average overall mshr miss latency
system.cpu2.branchPred.lookups                  68293                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            60753                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             2314                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               60518                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                   1899                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups          60518                       # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits             50086                       # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses           10432                       # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted         1220                       # Number of mispredicted indirect branches.
system.cpu2.pwrStateResidencyTicks::ON      123756000                       # Cumulative time (in ticks) in various power states
system.cpu2.numCycles                          189148                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             37019                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        374433                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      68293                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             51985                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       146261                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   4785                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1657                       # Number of stall cycles due to pending traps
system.cpu2.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                    25650                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  889                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            187354                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.998532                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.363195                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   64471     34.41%     34.41% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   60026     32.04%     66.45% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    7128      3.80%     70.25% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3545      1.89%     72.15% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     670      0.36%     72.50% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   40604     21.67%     94.18% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1041      0.56%     94.73% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                    1382      0.74%     95.47% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    8487      4.53%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              187354                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.361056                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.979577                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   21923                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                61377                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    97674                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 3978                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2392                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                343665                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2392                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   22954                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  28666                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         13829                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    98633                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                20870                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                337053                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                 18126                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                    18                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents               2                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands             236414                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               645955                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          501894                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               22                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps               208648                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   27766                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1626                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1738                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    26523                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               93867                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              44893                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            44587                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           38578                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    275945                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               7527                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   275850                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               71                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          23937                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        18592                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved          1173                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       187354                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.472346                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.381832                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              68951     36.80%     36.80% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              24397     13.02%     49.82% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              43633     23.29%     73.11% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              43435     23.18%     96.30% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3472      1.85%     98.15% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1779      0.95%     99.10% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6               1003      0.54%     99.63% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                391      0.21%     99.84% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                293      0.16%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         187354                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                    191     39.71%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMultAcc                0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMisc                   0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     39.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    64     13.31%     53.01% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  226     46.99%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               133523     48.40%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMultAcc              0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMisc                 0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.40% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               98433     35.68%     84.09% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              43894     15.91%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                275850                       # Type of FU issued
system.cpu2.iq.rate                          1.458382                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        481                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001744                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            739606                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           307404                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       272120                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                44                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                276331                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           38492                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         4293                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses           47                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         2655                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2392                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   7918                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             329268                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              414                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                93867                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               44893                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1518                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    38                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            39                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           443                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         2459                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                2902                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               273426                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                92301                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             2424                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        45796                       # number of nop insts executed
system.cpu2.iew.exec_refs                      135892                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   56020                       # Number of branches executed
system.cpu2.iew.exec_stores                     43591                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.445566                       # Inst execution rate
system.cpu2.iew.wb_sent                        272582                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       272120                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   153730                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   161299                       # num instructions consuming a value
system.cpu2.iew.wb_rate                      1.438662                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.953075                       # average fanout of values written-back
system.cpu2.commit.commitSquashedInsts          25088                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           6354                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             2314                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       182587                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.665803                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.057645                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        74839     40.99%     40.99% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        52317     28.65%     69.64% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         5497      3.01%     72.65% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         6991      3.83%     76.48% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1341      0.73%     77.22% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        38632     21.16%     98.37% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          681      0.37%     98.75% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1052      0.58%     99.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8         1237      0.68%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       182587                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              304154                       # Number of instructions committed
system.cpu2.commit.committedOps                304154                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        131812                       # Number of memory references committed
system.cpu2.commit.loads                        89574                       # Number of loads committed
system.cpu2.commit.membars                       5632                       # Number of memory barriers committed
system.cpu2.commit.branches                     53837                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   207761                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        44619     14.67%     14.67% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu          122091     40.14%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult              0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMultAcc            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMisc            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     54.81% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead          95206     31.30%     86.11% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite         42238     13.89%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total           304154                       # Class of committed instruction
system.cpu2.commit.bw_lim_events                 1237                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                      510006                       # The number of ROB reads
system.cpu2.rob.rob_writes                     663292                       # The number of ROB writes
system.cpu2.timesIdled                            219                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           1794                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       49847                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     253903                       # Number of Instructions Simulated
system.cpu2.committedOps                       253903                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              0.744962                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.744962                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.342351                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.342351                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  471960                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 219741                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 137767                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           25.074061                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              49166                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1695.379310                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    25.074061                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.048973                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.048973                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           384293                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          384293                       # Number of data accesses
system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu2.dcache.ReadReq_hits::cpu2.data        53240                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          53240                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        42018                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         42018                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           11                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        95258                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           95258                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        95258                       # number of overall hits
system.cpu2.dcache.overall_hits::total          95258                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          529                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          529                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          144                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          144                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           65                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           65                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          673                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           673                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          673                       # number of overall misses
system.cpu2.dcache.overall_misses::total          673                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      4007500                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      4007500                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3035500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      3035500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       419500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       419500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      7043000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      7043000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      7043000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      7043000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        53769                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        53769                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        42162                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        42162                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           76                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           76                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        95931                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        95931                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        95931                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        95931                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.009838                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.009838                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003415                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.003415                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.855263                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.855263                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007015                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.007015                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007015                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.007015                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data  7575.614367                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total  7575.614367                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21079.861111                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 21079.861111                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  6453.846154                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  6453.846154                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10465.081724                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 10465.081724                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10465.081724                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 10465.081724                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          358                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          358                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           41                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           41                       # number of WriteReq MSHR hits
system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data            1                       # number of SwapReq MSHR hits
system.cpu2.dcache.SwapReq_mshr_hits::total            1                       # number of SwapReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          399                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          399                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          399                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          399                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          171                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          171                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          103                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          103                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           64                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           64                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          274                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          274                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          274                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          274                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1122000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1122000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1473000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1473000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       354500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       354500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      2595000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      2595000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      2595000                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      2595000                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003180                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003180                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002443                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002443                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.842105                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.842105                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002856                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.002856                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002856                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.002856                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  6561.403509                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  6561.403509                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14300.970874                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14300.970874                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  5539.062500                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  5539.062500                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data  9470.802920                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total  9470.802920                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data  9470.802920                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total  9470.802920                       # average overall mshr miss latency
system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements              575                       # number of replacements
system.cpu2.icache.tags.tagsinuse           93.413944                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs              24822                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              707                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs            35.108911                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    93.413944                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.182449                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.182449                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024          132                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.257812                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses            26357                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses           26357                       # Number of data accesses
system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu2.icache.ReadReq_hits::cpu2.inst        24822                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          24822                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        24822                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           24822                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        24822                       # number of overall hits
system.cpu2.icache.overall_hits::total          24822                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          828                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          828                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          828                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           828                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          828                       # number of overall misses
system.cpu2.icache.overall_misses::total          828                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     12872000                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     12872000                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     12872000                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     12872000                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     12872000                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     12872000                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        25650                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        25650                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        25650                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        25650                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        25650                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        25650                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.032281                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.032281                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.032281                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.032281                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.032281                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.032281                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15545.893720                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 15545.893720                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15545.893720                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 15545.893720                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15545.893720                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 15545.893720                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs           69                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                3                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs           23                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.writebacks::writebacks          575                       # number of writebacks
system.cpu2.icache.writebacks::total              575                       # number of writebacks
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst          121                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total          121                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst          121                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total          121                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst          121                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total          121                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          707                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          707                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          707                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          707                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          707                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          707                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     11018000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total     11018000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     11018000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total     11018000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     11018000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total     11018000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.027563                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.027563                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.027563                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.027563                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.027563                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.027563                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15584.158416                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15584.158416                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15584.158416                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 15584.158416                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15584.158416                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 15584.158416                       # average overall mshr miss latency
system.cpu3.branchPred.lookups                  62938                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            55062                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             2421                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               53856                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                   2064                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups          53856                       # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits             44056                       # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses            9800                       # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted         1349                       # Number of mispredicted indirect branches.
system.cpu3.pwrStateResidencyTicks::ON      123756000                       # Cumulative time (in ticks) in various power states
system.cpu3.numCycles                          188742                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             40214                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        338441                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      62938                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             46120                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       142180                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   4995                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1755                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    28914                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  967                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            186659                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.813151                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.333247                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   73605     39.43%     39.43% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   55869     29.93%     69.36% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    8647      4.63%     74.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3452      1.85%     75.85% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     624      0.33%     76.18% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   33274     17.83%     94.01% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1074      0.58%     94.58% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                    1300      0.70%     95.28% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    8814      4.72%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              186659                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.333460                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.793141                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   22716                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                73421                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    83265                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 4750                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2497                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                307410                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2497                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   23704                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  36346                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         12933                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    84283                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                26886                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                301080                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                 23387                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                    16                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.RenamedOperands             210366                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               567874                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          443450                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups               24                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps               181055                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   29311                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1630                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1783                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    32120                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               81178                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              37704                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            38749                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           31258                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    243640                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               9008                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   244569                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued               85                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          25003                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        20491                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved          1173                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       186659                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.310245                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.388449                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              78461     42.03%     42.03% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              28833     15.45%     57.48% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              36126     19.35%     76.84% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              35957     19.26%     96.10% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3664      1.96%     98.06% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1804      0.97%     99.03% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6               1069      0.57%     99.60% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                437      0.23%     99.83% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                308      0.17%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         186659                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                    212     43.80%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMultAcc                0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMisc                   0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     43.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    41      8.47%     52.27% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  231     47.73%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMemRead                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMemWrite               0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               120712     49.36%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMultAcc              0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMisc                 0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.36% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               87244     35.67%     85.03% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              36613     14.97%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMemRead              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMemWrite             0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                244569                       # Type of FU issued
system.cpu3.iq.rate                          1.295785                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        484                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001979                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            676366                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           277636                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       240444                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                48                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                245053                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           31180                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         4645                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses           43                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           33                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         2744                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2497                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   9575                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   52                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             292625                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              421                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                81178                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               37704                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1504                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    32                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            33                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           434                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         2602                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                3036                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               241934                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                79457                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             2635                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        39977                       # number of nop insts executed
system.cpu3.iew.exec_refs                      115781                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   50244                       # Number of branches executed
system.cpu3.iew.exec_stores                     36324                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.281824                       # Inst execution rate
system.cpu3.iew.wb_sent                        241008                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       240444                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   133441                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   140864                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      1.273929                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.947304                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts          26116                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           7835                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             2421                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       181669                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.466860                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.985223                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        85663     47.15%     47.15% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        46447     25.57%     72.72% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         5344      2.94%     75.66% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         8472      4.66%     80.33% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1289      0.71%     81.03% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        31374     17.27%     98.30% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          856      0.47%     98.78% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1022      0.56%     99.34% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8         1202      0.66%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       181669                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              266483                       # Number of instructions committed
system.cpu3.commit.committedOps                266483                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                        111493                       # Number of memory references committed
system.cpu3.commit.loads                        76533                       # Number of loads committed
system.cpu3.commit.membars                       7123                       # Number of memory barriers committed
system.cpu3.commit.branches                     48046                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   181662                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass        38838     14.57%     14.57% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu          109029     40.91%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult              0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMultAcc            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMisc            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.49% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead          83656     31.39%     86.88% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite         34960     13.12%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total           266483                       # Class of committed instruction
system.cpu3.commit.bw_lim_events                 1202                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                      472480                       # The number of ROB reads
system.cpu3.rob.rob_writes                     590253                       # The number of ROB writes
system.cpu3.timesIdled                            225                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           2083                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       50253                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     220522                       # Number of Instructions Simulated
system.cpu3.committedOps                       220522                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              0.855887                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.855887                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.168378                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.168378                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  411294                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 192402                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 117678                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           24.245200                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              42083                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs          1451.137931                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.245200                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.047354                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.047354                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           333051                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          333051                       # Number of data accesses
system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu3.dcache.ReadReq_hits::cpu3.data        47761                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          47761                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        34756                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         34756                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           13                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        82517                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           82517                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        82517                       # number of overall hits
system.cpu3.dcache.overall_hits::total          82517                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          480                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          480                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          138                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          138                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           53                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           53                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          618                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           618                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          618                       # number of overall misses
system.cpu3.dcache.overall_misses::total          618                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4264500                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      4264500                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3342000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      3342000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       357000                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       357000                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      7606500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      7606500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      7606500                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      7606500                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        48241                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        48241                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        34894                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        34894                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           66                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        83135                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        83135                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        83135                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        83135                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.009950                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.009950                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003955                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.003955                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.803030                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.803030                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007434                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.007434                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007434                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.007434                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data  8884.375000                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total  8884.375000                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 24217.391304                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 24217.391304                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  6735.849057                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  6735.849057                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12308.252427                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 12308.252427                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12308.252427                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 12308.252427                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          324                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          324                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           31                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           31                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          355                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          355                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          355                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          355                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          156                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          156                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           53                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           53                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          263                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          263                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          263                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          263                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1092500                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1092500                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1676500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1676500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       304000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       304000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2769000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2769000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2769000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2769000                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003234                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003234                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003066                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003066                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.803030                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.803030                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003164                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003164                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003164                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003164                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  7003.205128                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  7003.205128                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15668.224299                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15668.224299                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  5735.849057                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  5735.849057                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10528.517110                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10528.517110                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10528.517110                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10528.517110                       # average overall mshr miss latency
system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements              578                       # number of replacements
system.cpu3.icache.tags.tagsinuse           92.244162                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs              28072                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              714                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs            39.316527                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    92.244162                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.180164                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.180164                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024          136                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.265625                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses            29628                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses           29628                       # Number of data accesses
system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.cpu3.icache.ReadReq_hits::cpu3.inst        28072                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          28072                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        28072                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           28072                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        28072                       # number of overall hits
system.cpu3.icache.overall_hits::total          28072                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          842                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          842                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          842                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           842                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          842                       # number of overall misses
system.cpu3.icache.overall_misses::total          842                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst     12413000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total     12413000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst     12413000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total     12413000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst     12413000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total     12413000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        28914                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        28914                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        28914                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        28914                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        28914                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        28914                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.029121                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.029121                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.029121                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.029121                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.029121                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.029121                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14742.280285                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 14742.280285                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14742.280285                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 14742.280285                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14742.280285                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 14742.280285                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.writebacks::writebacks          578                       # number of writebacks
system.cpu3.icache.writebacks::total              578                       # number of writebacks
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst          128                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total          128                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst          128                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total          128                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst          128                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total          128                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          714                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          714                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          714                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          714                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          714                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          714                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst     10783500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total     10783500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst     10783500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total     10783500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst     10783500                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total     10783500                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.024694                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.024694                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.024694                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.024694                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.024694                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.024694                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 15102.941176                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 15102.941176                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 15102.941176                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 15102.941176                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 15102.941176                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 15102.941176                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  560.431051                       # Cycle average of tags in use
system.l2c.tags.total_refs                       3109                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      707                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.397454                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::cpu0.inst      296.754574                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data      144.555076                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst       69.060046                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data       16.007345                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst        7.444463                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data        9.891084                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        6.988316                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        9.730146                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::cpu0.inst       0.004528                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.002206                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.001054                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000244                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000114                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000151                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000107                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000148                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.008551                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          707                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          189                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          463                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.010788                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    31411                       # Number of tag accesses
system.l2c.tags.data_accesses                   31411                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks          752                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total             752                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              23                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              22                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              20                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data              22                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  87                       # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst           309                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst           544                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst           685                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst           698                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total              2236                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst                 309                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 544                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 685                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 698                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    2268                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                309                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                544                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                685                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                698                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   2268                       # number of overall hits
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst          373                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst           99                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst           22                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst           16                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total             510                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data           75                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data            9                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total             88                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst               373                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               169                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                99                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                22                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                22                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                14                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   729                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              373                       # number of overall misses
system.l2c.overall_misses::cpu0.data              169                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               99                       # number of overall misses
system.l2c.overall_misses::cpu1.data               22                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               22                       # number of overall misses
system.l2c.overall_misses::cpu2.data               14                       # number of overall misses
system.l2c.overall_misses::cpu3.inst               16                       # number of overall misses
system.l2c.overall_misses::cpu3.data               14                       # number of overall misses
system.l2c.overall_misses::total                  729                       # number of overall misses
system.l2c.ReadExReq_miss_latency::cpu0.data      7939000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data      1091000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data      1053000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data      1225000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total     11308000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst     30754500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst      8285500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst      2209000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst      1811500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total     43060500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data      6607500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data       768000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data       179500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data       199500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total      7754500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     30754500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     14546500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      8285500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1859000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      2209000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1232500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst      1811500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data      1424500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        62123000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     30754500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     14546500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      8285500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1859000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      2209000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1232500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst      1811500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data      1424500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       62123000                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks          752                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total          752                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           23                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              87                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst          682                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst          643                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst          707                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst          714                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total          2746                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data           80                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data           14                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total          120                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             682                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             174                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             643                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              27                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             707                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             714                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2997                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            682                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            174                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            643                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             27                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            707                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            714                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2997                       # number of overall (read+write) accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.546921                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.153966                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.031117                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.022409                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.185725                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.937500                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.642857                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.153846                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.153846                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.733333                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.546921                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.153966                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.814815                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.031117                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.560000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.022409                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.560000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.243243                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.546921                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.153966                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.814815                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.031117                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.560000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.022409                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.560000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.243243                       # miss rate for overall accesses
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84457.446809                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83923.076923                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data        87750                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 102083.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 86320.610687                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82451.742627                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83691.919192                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 100409.090909                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 113218.750000                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 84432.352941                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data        88100                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 85333.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        89750                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        99750                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 88119.318182                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82451.742627                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 86073.964497                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 83691.919192                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        84500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 100409.090909                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 88035.714286                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 113218.750000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data       101750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 85216.735254                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82451.742627                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 86073.964497                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 83691.919192                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        84500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 100409.090909                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 88035.714286                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 113218.750000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data       101750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 85216.735254                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            3                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst           10                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            3                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           21                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 21                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                21                       # number of overall MSHR hits
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          370                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           94                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           12                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst           13                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total          489                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data           75                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data            9                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total           88                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          370                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          169                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           94                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           22                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           12                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              708                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          370                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          169                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           94                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           22                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           12                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             708                       # number of overall MSHR misses
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6999000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       961000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       933000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      1105000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      9998000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     26936000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      7072000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      1460500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst      1496500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total     36965000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5857500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       678000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       159500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data       179500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total      6874500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     26936000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     12856500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      7072000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data      1639000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      1460500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1092500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst      1496500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data      1284500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     53837500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     26936000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     12856500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      7072000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data      1639000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      1460500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1092500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst      1496500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data      1284500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     53837500                       # number of overall MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.542522                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.146190                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.016973                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.018207                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.178077                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.642857                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.153846                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.153846                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.733333                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.542522                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.146190                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.814815                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.016973                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.560000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.018207                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.560000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.236236                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.542522                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.146190                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.814815                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.016973                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.560000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.018207                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.560000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.236236                       # mshr miss rate for overall accesses
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74457.446809                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73923.076923                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data        77750                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 92083.333333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 76320.610687                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst        72800                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75234.042553                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 121708.333333                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 115115.384615                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75593.047035                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data        78100                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75333.333333                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        79750                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        89750                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78119.318182                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst        72800                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76073.964497                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75234.042553                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data        74500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 121708.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 78035.714286                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 115115.384615                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data        91750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 76041.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst        72800                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76073.964497                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75234.042553                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data        74500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 121708.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 78035.714286                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 115115.384615                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data        91750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 76041.666667                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests           958                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests          251                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                576                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              200                       # Transaction distribution
system.membus.trans_dist::ReadExReq               182                       # Transaction distribution
system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           576                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1665                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1665                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        45248                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   45248                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              251                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               958                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     958    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 958                       # Request fanout histogram
system.membus.reqLayer0.occupancy              881500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3759250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.0                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests         6160                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests         1652                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         3166                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED    123756000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp              3429                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean         2041                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             287                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            287                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              398                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             398                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq          2746                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq          686                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1744                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          595                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1793                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          369                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1989                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          384                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         2006                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          363                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  9243                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        67968                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11200                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        73600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1728                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        82048                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        82688                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total                 322432                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                            1033                       # Total snoops (count)
system.toL2Bus.snoopTraffic                     53312                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples             4117                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.305805                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.138383                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                   1342     32.60%     32.60% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                   1062     25.80%     58.39% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    825     20.04%     78.43% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                    888     21.57%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total               4117                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy            5135473                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              4.1                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy           1023494                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy            524487                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy            967494                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy            424479                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy           1065487                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.9                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy            451954                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           1072994                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.9                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy            419968                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------