path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000108                       # Number of seconds simulated
sim_ticks                                   107836000                       # Number of ticks simulated
final_tick                                  107836000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  68965                       # Simulator instruction rate (inst/s)
host_op_rate                                    68965                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                                7480497                       # Simulator tick rate (ticks/s)
host_mem_usage                                 247424                       # Number of bytes of host memory used
host_seconds                                    14.42                       # Real time elapsed on the host
sim_insts                                      994171                       # Number of instructions simulated
sim_ops                                        994171                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst            23040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             5120                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                42560                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        23040                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         5120                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          192                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          448                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           28800                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               360                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               169                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                80                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                 3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   665                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           213657777                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data           100300456                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            47479506                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            11869876                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             1780481                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7715420                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             4154457                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7715420                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               394673393                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      213657777                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       47479506                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        1780481                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        4154457                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          267072221                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          213657777                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data          100300456                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           47479506                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           11869876                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            1780481                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7715420                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            4154457                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7715420                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              394673393                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           666                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         666                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    42624                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     42624                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             89                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 114                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  42                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  30                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  60                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  66                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  27                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  18                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  24                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 61                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 38                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 18                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 97                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                       107808000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     666                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       396                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       199                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          145                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      274.537931                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     187.244268                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     251.506931                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             44     30.34%     30.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           37     25.52%     55.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           28     19.31%     75.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           11      7.59%     82.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            7      4.83%     87.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            8      5.52%     93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            2      1.38%     94.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            3      2.07%     96.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            5      3.45%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            145                       # Bytes accessed per row activation
system.physmem.totQLat                        6565250                       # Total ticks spent queuing
system.physmem.totMemAccLat                  19052750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3330000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9857.73                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28607.73                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         395.27                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      395.27                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.09                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.09                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.29                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        510                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.58                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       161873.87                       # Average gap between requests
system.physmem.pageHitRate                      76.58                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     710640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     387750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   2769000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy                6611280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy               38088540                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy               27477750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy                 76044960                       # Total energy per rank (pJ)
system.physmem_0.averagePower              749.349855                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE       47969250                       # Time in different power states
system.physmem_0.memoryStateTime::REF         3380000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT        52649750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                     355320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     193875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   2028000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy                6611280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy               32065065                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               32761500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy                 74015040                       # Total energy per rank (pJ)
system.physmem_1.averagePower              729.346948                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE       57811250                       # Time in different power states
system.physmem_1.memoryStateTime::REF         3380000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        43803750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu0.branchPred.lookups                  81652                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            79008                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1100                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               78985                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                  76270                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            96.562638                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                    645                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          215673                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             19729                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        482689                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      81652                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             76915                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       165939                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   2501                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                        96                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1994                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     6734                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  621                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples            189011                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.553761                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.213837                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   30617     16.20%     16.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   78326     41.44%     57.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     798      0.42%     58.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                    1203      0.64%     58.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     614      0.32%     59.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   73725     39.01%     98.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     672      0.36%     98.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     403      0.21%     98.60% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2653      1.40%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              189011                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.378592                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.238059                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   15475                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                18570                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   153063                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  653                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  1250                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                472193                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  1250                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   16079                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   2117                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         15116                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   153063                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                 1386                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                469016                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                    11                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents                   883                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands             320676                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups               935403                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          706479                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               307583                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   13093                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               822                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           832                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     4383                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              150037                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              75873                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            73364                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           72959                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    392343                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                889                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   388906                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued               31                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          12322                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        11733                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           330                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       189011                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.057584                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.125737                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              33687     17.82%     17.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4243      2.24%     20.07% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              74165     39.24%     59.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              73776     39.03%     98.34% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1622      0.86%     99.20% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                890      0.47%     99.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                405      0.21%     99.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                147      0.08%     99.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 76      0.04%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         189011                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     62     21.45%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     21.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                   124     42.91%     64.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  103     35.64%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               164396     42.27%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.27% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              149390     38.41%     80.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              75120     19.32%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                388906                       # Type of FU issued
system.cpu0.iq.rate                          1.803221                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        289                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000743                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads            967143                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           405616                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       387054                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                389195                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           72474                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2656                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           63                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1676                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           22                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  1250                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   2081                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   38                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             466895                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              243                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               150037                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               75873                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               770                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    46                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            63                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           318                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect          991                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1309                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               387894                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               149051                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1012                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        73663                       # number of nop insts executed
system.cpu0.iew.exec_refs                      224021                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   76988                       # Number of branches executed
system.cpu0.iew.exec_stores                     74970                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.798528                       # Inst execution rate
system.cpu0.iew.wb_sent                        387462                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       387054                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   229603                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   232649                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      1.794634                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.986907                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts          13111                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1100                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       186547                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.432234                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.149146                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        33930     18.19%     18.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        76047     40.77%     58.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         1940      1.04%     59.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          670      0.36%     60.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          524      0.28%     60.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        72154     38.68%     99.31% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          534      0.29%     99.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          265      0.14%     99.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          483      0.26%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       186547                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              453726                       # Number of instructions committed
system.cpu0.commit.committedOps                453726                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        221578                       # Number of memory references committed
system.cpu0.commit.loads                       147381                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     76084                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   305914                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass        72816     16.05%     16.05% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu          159248     35.10%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.15% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead         147465     32.50%     83.65% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite         74197     16.35%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total           453726                       # Class of committed instruction
system.cpu0.commit.bw_lim_events                  483                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                      651740                       # The number of ROB reads
system.cpu0.rob.rob_writes                     936154                       # The number of ROB writes
system.cpu0.timesIdled                            313                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          26662                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     380826                       # Number of Instructions Simulated
system.cpu0.committedOps                       380826                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              0.566330                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.566330                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.765756                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.765756                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  693989                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 312909                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 225890                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          141.137199                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs             149509                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              171                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs           874.321637                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.137199                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.275659                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.275659                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.330078                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           603167                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          603167                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data        75961                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          75961                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        73598                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         73598                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       149559                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          149559                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       149559                       # number of overall hits
system.cpu0.dcache.overall_hits::total         149559                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          557                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          557                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          557                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          557                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1114                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1114                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1114                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1114                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     17293500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     17293500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     34774980                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     34774980                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       472500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       472500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     52068480                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     52068480                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     52068480                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     52068480                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        76518                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        76518                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        74155                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        74155                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       150673                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       150673                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       150673                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       150673                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.007279                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.007279                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007511                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007511                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.007393                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.007393                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.007393                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.007393                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31047.576302                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 31047.576302                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62432.639138                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 62432.639138                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46740.107720                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 46740.107720                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46740.107720                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 46740.107720                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          891                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               27                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs           33                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          375                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          375                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          379                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          379                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          754                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          754                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          754                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          754                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          182                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          182                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          178                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          178                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          360                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          360                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          360                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          360                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6892000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6892000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8487000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8487000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       446500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       446500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15379000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     15379000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15379000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     15379000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002379                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002379                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002400                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002400                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002389                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002389                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002389                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002389                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37868.131868                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37868.131868                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47679.775281                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47679.775281                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42719.444444                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42719.444444                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42719.444444                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42719.444444                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements              315                       # number of replacements
system.cpu0.icache.tags.tagsinuse          241.200073                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs               5951                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              607                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             9.803954                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.200073                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471094                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.471094                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          292                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          173                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.570312                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses             7341                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses            7341                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst         5951                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           5951                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         5951                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            5951                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         5951                       # number of overall hits
system.cpu0.icache.overall_hits::total           5951                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          783                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          783                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          783                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           783                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          783                       # number of overall misses
system.cpu0.icache.overall_misses::total          783                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     40367500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     40367500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     40367500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     40367500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     40367500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     40367500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         6734                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         6734                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         6734                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         6734                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         6734                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         6734                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.116276                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.116276                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.116276                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.116276                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.116276                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.116276                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51554.916986                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 51554.916986                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51554.916986                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 51554.916986                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51554.916986                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 51554.916986                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            4                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks          315                       # number of writebacks
system.cpu0.icache.writebacks::total              315                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          175                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          175                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          175                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          175                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          175                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          175                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          608                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          608                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          608                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          608                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          608                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          608                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     31309500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     31309500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     31309500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     31309500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     31309500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     31309500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.090288                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.090288                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.090288                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.090288                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.090288                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.090288                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51495.888158                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51495.888158                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51495.888158                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 51495.888158                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51495.888158                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 51495.888158                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                  53782                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            50347                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             1277                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               46315                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                  45397                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            98.017921                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                    899                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu1.numCycles                          162898                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             29679                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        299544                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      53782                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             46296                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       124703                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   2711                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1084                       # Number of stall cycles due to pending traps
system.cpu1.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                    20165                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  457                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            156846                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.909797                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.217375                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   53057     33.83%     33.83% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   52143     33.24%     67.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    5878      3.75%     70.82% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3526      2.25%     73.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     939      0.60%     73.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   35272     22.49%     96.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1247      0.80%     96.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     803      0.51%     97.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3981      2.54%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              156846                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.330158                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.838844                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   17882                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                51023                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    83554                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 3022                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  1355                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                284108                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  1355                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   18601                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  22664                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         13899                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    84840                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                15477                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                280728                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                 13732                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents               6                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands             198394                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               541219                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          420944                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               184552                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   13842                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1192                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1257                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    20109                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               79403                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              38032                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            37516                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           32939                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    234221                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               5649                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   235400                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued                7                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          12841                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        10393                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           661                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       156846                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.500835                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.378978                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              56627     36.10%     36.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              19405     12.37%     48.48% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              37510     23.92%     72.39% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              37026     23.61%     96.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3380      2.15%     98.15% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1607      1.02%     99.18% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                891      0.57%     99.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                204      0.13%     99.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                196      0.12%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         156846                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     79     24.38%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     24.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    36     11.11%     35.49% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  209     64.51%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               114995     48.85%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.85% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               82971     35.25%     84.10% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              37434     15.90%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                235400                       # Type of FU issued
system.cpu1.iq.rate                          1.445076                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        324                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001376                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            627977                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           252747                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       233879                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                235724                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           32768                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2551                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           36                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1483                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  1355                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   6889                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   69                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             278263                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              133                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                79403                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               38032                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1130                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    43                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            36                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           442                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         1069                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1511                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               234388                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                78381                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1012                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        38393                       # number of nop insts executed
system.cpu1.iew.exec_refs                      115730                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   47858                       # Number of branches executed
system.cpu1.iew.exec_stores                     37349                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.438864                       # Inst execution rate
system.cpu1.iew.wb_sent                        234148                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       233879                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   133368                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   139978                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      1.435739                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.952778                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts          13605                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           4988                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1277                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       154309                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.714761                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.081585                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        61394     39.79%     39.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        44430     28.79%     68.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         5247      3.40%     71.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         5803      3.76%     75.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1533      0.99%     76.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        32828     21.27%     98.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          824      0.53%     98.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7          946      0.61%     99.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8         1304      0.85%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       154309                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              264603                       # Number of instructions committed
system.cpu1.commit.committedOps                264603                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        113401                       # Number of memory references committed
system.cpu1.commit.loads                        76852                       # Number of loads committed
system.cpu1.commit.membars                       4272                       # Number of memory barriers committed
system.cpu1.commit.branches                     46786                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   182306                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass        37574     14.20%     14.20% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu          109356     41.33%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.53% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead          81124     30.66%     86.19% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite         36549     13.81%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total           264603                       # Class of committed instruction
system.cpu1.commit.bw_lim_events                 1304                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                      430627                       # The number of ROB reads
system.cpu1.rob.rob_writes                     558953                       # The number of ROB writes
system.cpu1.timesIdled                            228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           6052                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       45271                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     222757                       # Number of Instructions Simulated
system.cpu1.committedOps                       222757                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              0.731281                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.731281                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.367463                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.367463                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  407061                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 190501                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 117378                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           25.769381                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              42560                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs                 1520                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.769381                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.050331                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.050331                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           328816                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          328816                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data        45076                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          45076                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        36319                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         36319                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        81395                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           81395                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        81395                       # number of overall hits
system.cpu1.dcache.overall_hits::total          81395                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          515                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          515                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          160                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          160                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           56                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          675                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           675                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          675                       # number of overall misses
system.cpu1.dcache.overall_misses::total          675                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     10357000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total     10357000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3384000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3384000                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       705000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       705000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data     13741000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total     13741000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data     13741000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total     13741000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        45591                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        45591                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        36479                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        36479                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        82070                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        82070                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        82070                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        82070                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011296                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.011296                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004386                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.004386                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.800000                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.800000                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.008225                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.008225                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.008225                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.008225                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20110.679612                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 20110.679612                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data        21150                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total        21150                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12589.285714                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 12589.285714                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20357.037037                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20357.037037                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20357.037037                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20357.037037                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          349                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          349                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           53                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           53                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          402                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          402                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          402                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          402                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          166                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          166                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           56                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          273                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          273                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          273                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          273                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2153500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2153500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1760500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1760500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       649000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       649000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3914000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      3914000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3914000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      3914000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003641                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003641                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002933                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002933                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003326                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.003326                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003326                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.003326                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12972.891566                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12972.891566                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16453.271028                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16453.271028                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11589.285714                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11589.285714                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14336.996337                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14336.996337                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14336.996337                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14336.996337                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements              383                       # number of replacements
system.cpu1.icache.tags.tagsinuse           84.449474                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs              19585                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              496                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            39.485887                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    84.449474                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.164940                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.164940                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          113                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.220703                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses            20661                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses           20661                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst        19585                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          19585                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        19585                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           19585                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        19585                       # number of overall hits
system.cpu1.icache.overall_hits::total          19585                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          580                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          580                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          580                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           580                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          580                       # number of overall misses
system.cpu1.icache.overall_misses::total          580                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     14033000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     14033000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     14033000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     14033000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     14033000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     14033000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        20165                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        20165                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        20165                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        20165                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        20165                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        20165                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028763                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.028763                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028763                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.028763                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028763                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.028763                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24194.827586                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 24194.827586                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24194.827586                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 24194.827586                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24194.827586                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 24194.827586                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs          128                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs           64                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks          383                       # number of writebacks
system.cpu1.icache.writebacks::total              383                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           84                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           84                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           84                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           84                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           84                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           84                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          496                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          496                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          496                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          496                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          496                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          496                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     11668000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total     11668000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     11668000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total     11668000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     11668000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total     11668000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024597                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024597                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024597                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.024597                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024597                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.024597                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23524.193548                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23524.193548                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23524.193548                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 23524.193548                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23524.193548                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 23524.193548                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.branchPred.lookups                  46151                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            42669                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             1261                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               38744                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                  37721                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            97.359591                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                    903                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                          162526                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             35053                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        247865                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      46151                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             38624                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       123337                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   2679                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1154                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    26088                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  455                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            160896                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.540529                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.092892                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   69454     43.17%     43.17% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   47444     29.49%     72.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    8853      5.50%     78.16% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3439      2.14%     80.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     969      0.60%     80.90% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   24720     15.36%     96.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1203      0.75%     97.01% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     808      0.50%     97.51% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    4006      2.49%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              160896                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.283961                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.525079                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   17877                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                74268                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    63015                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 4387                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  1339                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                232406                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  1339                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   18566                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  36272                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         13923                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    64728                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                26058                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                229231                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                 23352                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                    13                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands             159189                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               426806                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          335096                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               145681                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   13508                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1198                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1266                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    30557                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               61312                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              27565                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            29913                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           22477                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    187400                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               8554                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   191519                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               13                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          12551                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        10065                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           731                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       160896                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.190328                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.355636                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              73129     45.45%     45.45% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              27885     17.33%     62.78% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              27023     16.80%     79.58% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              26608     16.54%     96.11% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3367      2.09%     98.21% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1611      1.00%     99.21% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                866      0.54%     99.75% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                211      0.13%     99.88% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                196      0.12%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         160896                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     80     24.02%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     24.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    44     13.21%     37.24% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  209     62.76%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu                96792     50.54%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.54% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               67722     35.36%     85.90% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              27005     14.10%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                191519                       # Type of FU issued
system.cpu2.iq.rate                          1.178390                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        333                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001739                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            544280                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           208542                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       190032                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                191852                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           22329                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         2475                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1441                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  1339                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   9482                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   66                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             226726                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              191                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                61312                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               27565                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1142                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    36                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            37                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           430                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         1052                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1482                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               190532                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                60316                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts              987                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        30772                       # number of nop insts executed
system.cpu2.iew.exec_refs                       87235                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   40210                       # Number of branches executed
system.cpu2.iew.exec_stores                     26919                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.172317                       # Inst execution rate
system.cpu2.iew.wb_sent                        190296                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       190032                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   104798                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   111375                       # num instructions consuming a value
system.cpu2.iew.wb_rate                      1.169241                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.940947                       # average fanout of values written-back
system.cpu2.commit.commitSquashedInsts          13298                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           7823                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1261                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       158397                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.347140                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.933730                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        80708     50.95%     50.95% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        36780     23.22%     74.17% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         5258      3.32%     77.49% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         8633      5.45%     82.94% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1531      0.97%     83.91% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        22393     14.14%     98.05% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          849      0.54%     98.58% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7          955      0.60%     99.19% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8         1290      0.81%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       158397                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              213383                       # Number of instructions committed
system.cpu2.commit.committedOps                213383                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                         84961                       # Number of memory references committed
system.cpu2.commit.loads                        58837                       # Number of loads committed
system.cpu2.commit.membars                       7109                       # Number of memory barriers committed
system.cpu2.commit.branches                     39190                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   146276                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        29980     14.05%     14.05% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu           91333     42.80%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult              0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.85% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead          65946     30.90%     87.76% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite         26124     12.24%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total           213383                       # Class of committed instruction
system.cpu2.commit.bw_lim_events                 1290                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                      383202                       # The number of ROB reads
system.cpu2.rob.rob_writes                     455861                       # The number of ROB writes
system.cpu2.timesIdled                            213                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           1630                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       45643                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     176294                       # Number of Instructions Simulated
system.cpu2.committedOps                       176294                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              0.921903                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.921903                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.084713                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.084713                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  321409                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 151400                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                  88848                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           23.120660                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              32242                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1111.793103                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    23.120660                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.045158                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.045158                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           256599                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          256599                       # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data        37491                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          37491                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        25903                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         25903                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           19                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             19                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        63394                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           63394                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        63394                       # number of overall hits
system.cpu2.dcache.overall_hits::total          63394                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          473                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          473                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          153                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          153                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           49                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           49                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          626                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           626                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          626                       # number of overall misses
system.cpu2.dcache.overall_misses::total          626                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      7957500                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      7957500                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3701500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      3701500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       605000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       605000                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data     11659000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total     11659000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data     11659000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total     11659000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        37964                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        37964                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        26056                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        26056                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        64020                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        64020                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        64020                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        64020                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.012459                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.012459                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.005872                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.005872                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.720588                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.720588                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.009778                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.009778                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.009778                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.009778                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16823.467230                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 16823.467230                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24192.810458                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 24192.810458                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12346.938776                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 12346.938776                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18624.600639                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 18624.600639                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18624.600639                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 18624.600639                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          311                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          311                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           50                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           50                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          361                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          361                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          361                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          361                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          162                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          103                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          103                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           49                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           49                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          265                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          265                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          265                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          265                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1647500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1647500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1967500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1967500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       556000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       556000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3615000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      3615000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3615000                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      3615000                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.004267                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.004267                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003953                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003953                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.720588                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.720588                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004139                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.004139                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004139                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.004139                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10169.753086                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10169.753086                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19101.941748                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19101.941748                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11346.938776                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11346.938776                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13641.509434                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13641.509434                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13641.509434                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13641.509434                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.icache.tags.replacements              386                       # number of replacements
system.cpu2.icache.tags.tagsinuse           77.580266                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs              25515                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              500                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs            51.030000                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    77.580266                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.151524                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.151524                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024          114                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.222656                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses            26588                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses           26588                       # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst        25515                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          25515                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        25515                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           25515                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        25515                       # number of overall hits
system.cpu2.icache.overall_hits::total          25515                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          573                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          573                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          573                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           573                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          573                       # number of overall misses
system.cpu2.icache.overall_misses::total          573                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7955500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      7955500                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      7955500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      7955500                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      7955500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      7955500                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        26088                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        26088                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        26088                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        26088                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        26088                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        26088                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.021964                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.021964                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.021964                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.021964                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.021964                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.021964                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13883.944154                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 13883.944154                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13883.944154                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 13883.944154                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13883.944154                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 13883.944154                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            5                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.writebacks::writebacks          386                       # number of writebacks
system.cpu2.icache.writebacks::total              386                       # number of writebacks
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           73                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           73                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           73                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           73                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           73                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           73                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          500                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          500                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          500                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          500                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          500                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          500                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      6895000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      6895000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      6895000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      6895000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      6895000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      6895000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.019166                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.019166                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.019166                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.019166                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.019166                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.019166                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst        13790                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total        13790                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst        13790                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total        13790                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst        13790                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total        13790                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.branchPred.lookups                  52678                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            49211                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             1284                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               45275                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                  44303                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            97.853120                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                    906                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu3.numCycles                          162161                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             30846                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        291154                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      52678                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             45209                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       126827                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   2723                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1166                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    21882                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  451                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            160213                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.817293                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.188011                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   57700     36.01%     36.01% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   51927     32.41%     68.43% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    6814      4.25%     72.68% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3535      2.21%     74.89% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     932      0.58%     75.47% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   33301     20.79%     96.25% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1242      0.78%     97.03% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     787      0.49%     97.52% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3975      2.48%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              160213                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.324850                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.795463                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   17433                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                58368                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    79576                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 3465                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  1361                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                275763                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  1361                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   18155                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  26788                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         14101                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    81078                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                18720                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                272367                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                 16743                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands             191251                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               520897                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          405695                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               177247                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   14004                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1196                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1267                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    23402                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               76309                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              36069                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            36463                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           30962                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    226032                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               6585                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   227862                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued               13                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          13164                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        10986                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           709                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       160213                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.422244                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.377526                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              61467     38.37%     38.37% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              22016     13.74%     52.11% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              35438     22.12%     74.23% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              35000     21.85%     96.07% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3395      2.12%     98.19% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1603      1.00%     99.19% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                883      0.55%     99.74% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                211      0.13%     99.88% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                200      0.12%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         160213                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     82     24.12%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     24.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    49     14.41%     38.53% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  209     61.47%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               111773     49.05%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.05% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               80677     35.41%     84.46% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              35412     15.54%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                227862                       # Type of FU issued
system.cpu3.iq.rate                          1.405159                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        340                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001492                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            616290                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           245818                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       226322                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                228202                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           30727                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2667                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1566                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  1361                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   7576                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   66                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             269910                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              166                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                76309                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               36069                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1148                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    41                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            37                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           452                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         1067                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1519                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               226838                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                75201                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1024                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        37293                       # number of nop insts executed
system.cpu3.iew.exec_refs                      110524                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   46686                       # Number of branches executed
system.cpu3.iew.exec_stores                     35323                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.398844                       # Inst execution rate
system.cpu3.iew.wb_sent                        226605                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       226322                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   128132                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   134738                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      1.395662                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.950972                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts          13998                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           5876                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1284                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       157615                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.623367                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     2.050526                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        67043     42.54%     42.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        43238     27.43%     69.97% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         5262      3.34%     73.31% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         6673      4.23%     77.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1534      0.97%     78.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        30788     19.53%     98.05% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          827      0.52%     98.57% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7          952      0.60%     99.18% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8         1298      0.82%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       157615                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              255867                       # Number of instructions committed
system.cpu3.commit.committedOps                255867                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                        108145                       # Number of memory references committed
system.cpu3.commit.loads                        73642                       # Number of loads committed
system.cpu3.commit.membars                       5159                       # Number of memory barriers committed
system.cpu3.commit.branches                     45627                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   175889                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass        36414     14.23%     14.23% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu          106149     41.49%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult              0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.72% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead          78801     30.80%     86.52% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite         34503     13.48%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total           255867                       # Class of committed instruction
system.cpu3.commit.bw_lim_events                 1298                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                      425596                       # The number of ROB reads
system.cpu3.rob.rob_writes                     542328                       # The number of ROB writes
system.cpu3.timesIdled                            209                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1948                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       46007                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     214294                       # Number of Instructions Simulated
system.cpu3.committedOps                       214294                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              0.756722                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.756722                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.321489                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.321489                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  391365                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 183208                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 112150                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           24.277315                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              40522                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs          1447.214286                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.277315                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.047417                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.047417                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           316074                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          316074                       # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data        43937                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          43937                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        34273                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         34273                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        78210                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           78210                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        78210                       # number of overall hits
system.cpu3.dcache.overall_hits::total          78210                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          514                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          514                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          159                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          159                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           57                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          673                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           673                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          673                       # number of overall misses
system.cpu3.dcache.overall_misses::total          673                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      9349000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      9349000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3790500                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      3790500                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       680500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       680500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data     13139500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total     13139500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data     13139500                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total     13139500                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        44451                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        44451                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        34432                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        34432                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        78883                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        78883                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        78883                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        78883                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.011563                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.011563                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004618                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.004618                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.802817                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.802817                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008532                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.008532                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008532                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.008532                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 18188.715953                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 18188.715953                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23839.622642                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 23839.622642                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11938.596491                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 11938.596491                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19523.774146                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 19523.774146                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19523.774146                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 19523.774146                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          347                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          347                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           52                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          399                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          399                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          399                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          399                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          167                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          167                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          274                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          274                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          274                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          274                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1719000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1719000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      2129500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      2129500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       623500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       623500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3848500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      3848500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3848500                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      3848500                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003757                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003757                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003108                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003108                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.802817                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.802817                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003473                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003473                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003473                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003473                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10293.413174                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10293.413174                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19901.869159                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19901.869159                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10938.596491                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10938.596491                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14045.620438                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14045.620438                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14045.620438                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14045.620438                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.icache.tags.replacements              384                       # number of replacements
system.cpu3.icache.tags.tagsinuse           81.046367                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs              21310                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              498                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs            42.791165                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    81.046367                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.158294                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.158294                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024          114                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.222656                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses            22380                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses           22380                       # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst        21310                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          21310                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        21310                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           21310                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        21310                       # number of overall hits
system.cpu3.icache.overall_hits::total          21310                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          572                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          572                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          572                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           572                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          572                       # number of overall misses
system.cpu3.icache.overall_misses::total          572                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      8104500                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      8104500                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      8104500                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      8104500                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      8104500                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      8104500                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        21882                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        21882                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        21882                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        21882                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        21882                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        21882                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.026140                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.026140                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.026140                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.026140                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.026140                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.026140                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14168.706294                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 14168.706294                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14168.706294                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 14168.706294                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14168.706294                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 14168.706294                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.writebacks::writebacks          384                       # number of writebacks
system.cpu3.icache.writebacks::total              384                       # number of writebacks
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           74                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           74                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           74                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           74                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          498                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          498                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          498                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          498                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          498                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          498                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      6912000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      6912000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      6912000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      6912000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      6912000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      6912000                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.022758                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.022758                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.022758                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.022758                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.022758                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.022758                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13879.518072                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13879.518072                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13879.518072                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 13879.518072                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13879.518072                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 13879.518072                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  419.218954                       # Cycle average of tags in use
system.l2c.tags.total_refs                       2347                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      532                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.411654                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks       0.788461                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      288.048945                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data       58.083381                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst       60.484959                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data        5.324168                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst        2.350458                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data        0.677584                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        2.742702                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        0.718294                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.004395                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.000886                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.000923                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000081                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000036                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000010                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000042                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000011                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.006397                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          532                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          141                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.008118                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    25618                       # Number of tag accesses
system.l2c.tags.data_accesses                   25618                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks          676                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total             676                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst           246                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst           412                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst           491                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst           489                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total              1638                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data           11                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst                 246                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 412                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 491                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 489                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1670                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                246                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                412                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                491                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                489                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   1670                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data            27                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                89                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst          362                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst           84                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst            9                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst            9                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total             464                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data           75                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data            7                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total             84                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst               362                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               169                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                84                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                 9                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   679                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              362                       # number of overall misses
system.l2c.overall_misses::cpu0.data              169                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               84                       # number of overall misses
system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
system.l2c.overall_misses::cpu2.inst                9                       # number of overall misses
system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  679                       # number of overall misses
system.l2c.ReadExReq_miss_latency::cpu0.data      7611000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data      1059000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data      1210500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data      1399000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total     11279500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst     27676500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst      6293000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst       614000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst       660000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total     35243500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data      5981500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data       540000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data        82500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data        96500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total      6700500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     27676500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     13592500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      6293000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1599000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst       614000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1293000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       660000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data      1495500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        53223500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     27676500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     13592500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      6293000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1599000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst       614000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1293000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       660000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data      1495500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       53223500                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks          676                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total          676                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              92                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst          608                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst          496                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst          500                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst          498                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total          2102                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data           80                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data           12                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data           12                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data           12                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total          116                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             608                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             174                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             496                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             500                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             498                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2349                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            608                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            174                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            496                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            500                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            498                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2349                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.900000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.967391                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.595395                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.169355                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.018000                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.018072                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.220742                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.937500                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.583333                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.083333                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.083333                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.724138                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.595395                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.169355                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.018000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.018072                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.289059                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.595395                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.169355                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.018000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.018072                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.289059                       # miss rate for overall accesses
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80968.085106                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data       100875                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 116583.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 86103.053435                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76454.419890                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74916.666667                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 68222.222222                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 73333.333333                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 75955.818966                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79753.333333                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77142.857143                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        82500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        96500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 79767.857143                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 76454.419890                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 80428.994083                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74916.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        79950                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 68222.222222                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 99461.538462                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 73333.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 115038.461538                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 78385.125184                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 76454.419890                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 80428.994083                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74916.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        79950                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 68222.222222                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 99461.538462                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 73333.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 115038.461538                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 78385.125184                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            2                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 13                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                13                       # number of overall MSHR hits
system.l2c.UpgradeReq_mshr_misses::cpu0.data           27                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           21                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           21                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           89                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          361                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           80                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst            3                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            7                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total          451                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data           75                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data            7                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total           84                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          361                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          169                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           80                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              666                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          361                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          169                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           80                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             666                       # number of overall MSHR misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       587000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       437000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       459996                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       457500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      1941496                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6671000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       929000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      1090500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      1279000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      9969500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     23889000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      5285500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst       219000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       495500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total     29889000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5231500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       470000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data        72500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data        86500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total      5860500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     23889000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     11902500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      5285500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data      1399000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst       219000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1163000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       495500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data      1365500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     45719000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     23889000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     11902500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      5285500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data      1399000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst       219000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1163000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       495500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data      1365500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     45719000                       # number of overall MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.900000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.967391                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.593750                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.161290                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006000                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.014056                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.214558                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.724138                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.593750                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.161290                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.014056                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.283525                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.593750                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.161290                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.014056                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.283525                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21740.740741                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        21850                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21904.571429                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21785.714286                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21814.561798                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70968.085106                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data        90875                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 106583.333333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 76103.053435                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66174.515235                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66068.750000                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst        73000                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 70785.714286                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66272.727273                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        72500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        86500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70428.994083                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66068.750000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data        69950                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        73000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89461.538462                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 70785.714286                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105038.461538                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 68647.147147                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70428.994083                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66068.750000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data        69950                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        73000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89461.538462                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 70785.714286                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105038.461538                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 68647.147147                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp                534                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              290                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              89                       # Transaction distribution
system.membus.trans_dist::ReadExReq               162                       # Transaction distribution
system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           535                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1741                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1741                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        42560                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   42560                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              232                       # Total snoops (count)
system.membus.snoop_fanout::samples               987                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     987    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 987                       # Request fanout histogram
system.membus.reqLayer0.occupancy              936504                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3712661                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.4                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests         4933                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests         1339                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         2364                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadResp              2778                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean          676                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             293                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            293                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              391                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             391                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq          2102                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq          677                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1448                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          592                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1140                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          374                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1151                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          360                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1140                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          376                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  6581                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        53760                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11200                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        41216                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        41664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        41088                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total                 193600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                            1022                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples             3463                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.289633                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.182691                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                   1230     35.52%     35.52% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                    835     24.11%     59.63% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    563     16.26%     75.89% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                    835     24.11%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total               3463                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy            3953462                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              3.7                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy            911498                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy            505495                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.5                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy            746495                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.7                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy            439455                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy            752991                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.7                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy            419474                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy            747998                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.7                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy            434475                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.4                       # Layer utilization (%)

---------- End Simulation Statistics   ----------