path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000109                       # Number of seconds simulated
sim_ticks                                   108678000                       # Number of ticks simulated
final_tick                                  108678000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  97735                       # Simulator instruction rate (inst/s)
host_op_rate                                    97735                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                                9914053                       # Simulator tick rate (ticks/s)
host_mem_usage                                 237564                       # Number of bytes of host memory used
host_seconds                                    10.96                       # Real time elapsed on the host
sim_insts                                     1071369                       # Number of instructions simulated
sim_ops                                       1071369                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst            23040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             5504                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                42752                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        23040                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         5504                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          384                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           29056                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               360                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                86                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                 6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   668                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           212002429                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            98934467                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            50645025                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            11777913                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             3533374                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7655643                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             1177791                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7655643                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               393382285                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      212002429                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       50645025                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        3533374                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        1177791                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          267358619                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          212002429                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           98934467                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           50645025                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           11777913                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            3533374                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7655643                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            1177791                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7655643                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              393382285                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           669                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                            993                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                        42752                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                  42752                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                 76                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                    50                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                    71                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                    36                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                    31                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                    29                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                    23                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                    21                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                    54                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                    56                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                    73                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                   61                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                    5                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                   15                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                   21                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                   79                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                   44                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                       108650000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                     669                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                      0                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                   76                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                       401                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       192                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        62                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                        3390669                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                  18414669                       # Sum of mem lat for all requests
system.physmem.totBusLat                      2676000                       # Total cycles spent in databus access
system.physmem.totBankLat                    12348000                       # Total cycles spent in bank access
system.physmem.avgQLat                        5068.26                       # Average queueing delay per request
system.physmem.avgBankLat                    18457.40                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  27525.66                       # Average memory access latency
system.physmem.avgRdBW                         393.38                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                 393.38                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           2.46                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.17                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                        513                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.68                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       162406.58                       # Average gap between requests
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          217357                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                   85486                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted             83146                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect              1297                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups                83094                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                   80730                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                     510                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles             17254                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        507547                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      85486                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             81240                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       166653                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3954                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 12694                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1571                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     6105                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  500                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            200686                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.529060                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.210670                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   34033     16.96%     16.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   82572     41.14%     58.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     593      0.30%     58.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     970      0.48%     58.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     529      0.26%     59.15% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   78464     39.10%     98.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     697      0.35%     98.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     363      0.18%     98.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2465      1.23%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              200686                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.393298                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.335085                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   18097                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                14161                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   165636                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  283                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2509                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                504485                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2509                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18775                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                    695                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         12879                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   165279                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  549                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                501228                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents                  155                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands             342771                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups               999720                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          999720                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               329211                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   13560                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               922                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           944                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     3899                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              160553                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              81037                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            78269                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           78067                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    419118                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                951                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   416267                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              155                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          11107                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        10171                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           392                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       200686                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.074220                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.084012                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              33200     16.54%     16.54% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               5091      2.54%     19.08% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              80178     39.95%     59.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              79595     39.66%     98.69% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1563      0.78%     99.47% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                681      0.34%     99.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                279      0.14%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 88      0.04%     99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 11      0.01%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         200686                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     45     20.36%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     20.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    64     28.96%     49.32% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  112     50.68%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               175769     42.23%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              160047     38.45%     80.67% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              80451     19.33%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                416267                       # Type of FU issued
system.cpu0.iq.rate                          1.915130                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        221                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000531                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1033596                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           431231                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       414361                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                416488                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           77814                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2358                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           55                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1433                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked            4                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2509                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                    439                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   34                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             498940                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              337                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               160553                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               81037                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               840                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    37                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            55                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           377                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1128                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1505                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               415155                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               159727                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1112                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        78871                       # number of nop insts executed
system.cpu0.iew.exec_refs                      240043                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   82509                       # Number of branches executed
system.cpu0.iew.exec_stores                     80316                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.910014                       # Inst execution rate
system.cpu0.iew.wb_sent                        414703                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       414361                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   245547                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   248019                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.906361                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.990033                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts          12749                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1297                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       198194                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.452991                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.132633                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        33728     17.02%     17.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        82160     41.45%     58.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2430      1.23%     59.70% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          731      0.37%     60.07% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          570      0.29%     60.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        77594     39.15%     99.51% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          452      0.23%     99.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          239      0.12%     99.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          290      0.15%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       198194                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              486168                       # Number of instructions committed
system.cpu0.commit.committedOps                486168                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        237799                       # Number of memory references committed
system.cpu0.commit.loads                       158195                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     81491                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   327542                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events                  290                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      695660                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1000360                       # The number of ROB writes
system.cpu0.timesIdled                            319                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          16671                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     407861                       # Number of Instructions Simulated
system.cpu0.committedOps                       407861                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total               407861                       # Number of Instructions Simulated
system.cpu0.cpi                              0.532919                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.532919                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.876457                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.876457                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  742624                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 334702                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 241901                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.replacements                   305                       # number of replacements
system.cpu0.icache.tagsinuse               247.227558                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    5357                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   596                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  8.988255                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   247.227558                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.482866                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.482866                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst         5357                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           5357                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         5357                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            5357                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         5357                       # number of overall hits
system.cpu0.icache.overall_hits::total           5357                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          748                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          748                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          748                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           748                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          748                       # number of overall misses
system.cpu0.icache.overall_misses::total          748                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     25787000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     25787000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     25787000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     25787000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     25787000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     25787000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         6105                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         6105                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         6105                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         6105                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         6105                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         6105                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.122523                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.122523                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.122523                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.122523                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.122523                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.122523                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34474.598930                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 34474.598930                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34474.598930                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 34474.598930                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34474.598930                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 34474.598930                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          151                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          151                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          151                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          151                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          151                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          151                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          597                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          597                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          597                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          597                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          597                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          597                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     20662500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     20662500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     20662500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     20662500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     20662500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     20662500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.097789                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.097789                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.097789                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.097789                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.097789                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.097789                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34610.552764                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34610.552764                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34610.552764                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 34610.552764                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34610.552764                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 34610.552764                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     2                       # number of replacements
system.cpu0.dcache.tagsinuse               144.093465                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  160308                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                942.988235                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   144.093465                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.281433                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.281433                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        81376                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          81376                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        79021                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         79021                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           22                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             22                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       160397                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          160397                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       160397                       # number of overall hits
system.cpu0.dcache.overall_hits::total         160397                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          473                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          473                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          541                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          541                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           20                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           20                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1014                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1014                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1014                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1014                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     11124000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     11124000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     22939498                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     22939498                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       377000                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       377000                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     34063498                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     34063498                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     34063498                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     34063498                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        81849                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        81849                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        79562                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        79562                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       161411                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       161411                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       161411                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       161411                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005779                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.005779                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006800                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.006800                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.476190                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.476190                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006282                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006282                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006282                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006282                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23517.970402                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 23517.970402                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42402.029575                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42402.029575                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        18850                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total        18850                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33593.193294                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33593.193294                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33593.193294                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33593.193294                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          196                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               14                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs           14                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          282                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          282                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          370                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          370                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          652                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          652                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          652                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          652                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          191                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          191                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          171                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          171                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           20                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           20                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          362                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          362                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4857000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4857000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      5583500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      5583500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       337000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       337000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     10440500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     10440500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     10440500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     10440500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002334                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002334                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002149                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002149                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.476190                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.476190                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002243                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002243                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002243                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002243                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25429.319372                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25429.319372                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32652.046784                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32652.046784                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        16850                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        16850                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28841.160221                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28841.160221                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28841.160221                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28841.160221                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          181799                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                   59567                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted             56529                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect              1500                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups                52860                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                   52019                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                     823                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles             25837                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        338154                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      59567                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             52842                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       115388                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   4298                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 25769                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         6220                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1046                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    17180                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  322                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            176992                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.910561                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.213171                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   61604     34.81%     34.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   57789     32.65%     67.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    4656      2.63%     70.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3206      1.81%     71.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     672      0.38%     72.28% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   43499     24.58%     96.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1205      0.68%     97.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     866      0.49%     98.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3495      1.97%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              176992                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.327653                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.860043                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   29997                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                23620                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                   110723                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 3705                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2727                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                334194                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2727                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   30767                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  10715                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         12086                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                   107285                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                 7192                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                331783                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                     3                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                   53                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands             234003                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               646246                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          646246                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               218850                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   15153                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1212                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1340                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                     9848                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               96301                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              46898                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            45474                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           41683                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    277198                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               4877                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   277583                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued              147                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          12330                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        11288                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           591                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       176992                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.568336                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.306945                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              58949     33.31%     33.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              18466     10.43%     43.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              46965     26.54%     70.27% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              47589     26.89%     97.16% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3312      1.87%     99.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1274      0.72%     99.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                318      0.18%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 58      0.03%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         176992                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     20      6.43%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    81     26.05%     32.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  210     67.52%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               132190     47.62%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.62% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               99212     35.74%     83.36% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              46181     16.64%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                277583                       # Type of FU issued
system.cpu1.iq.rate                          1.526868                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        311                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001120                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            732616                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           294445                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       275571                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                277894                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           41481                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2645                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            7                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1604                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2727                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                    837                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   60                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             328541                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              420                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                96301                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               46898                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1140                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    60                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            40                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           494                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         1175                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1669                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               276246                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                95320                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1337                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        46466                       # number of nop insts executed
system.cpu1.iew.exec_refs                      141403                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   55896                       # Number of branches executed
system.cpu1.iew.exec_stores                     46083                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.519513                       # Inst execution rate
system.cpu1.iew.wb_sent                        275857                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       275571                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   158251                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   163120                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.515800                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.970151                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts          14237                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           4286                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1500                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       168046                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.870327                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.085151                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        57008     33.92%     33.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        53849     32.04%     65.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         6186      3.68%     69.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         5193      3.09%     72.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1537      0.91%     73.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        41906     24.94%     98.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          558      0.33%     98.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7          997      0.59%     99.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          812      0.48%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       168046                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              314301                       # Number of instructions committed
system.cpu1.commit.committedOps                314301                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        138950                       # Number of memory references committed
system.cpu1.commit.loads                        93656                       # Number of loads committed
system.cpu1.commit.membars                       3574                       # Number of memory barriers committed
system.cpu1.commit.branches                     54833                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   215906                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events                  812                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      495185                       # The number of ROB reads
system.cpu1.rob.rob_writes                     659817                       # The number of ROB writes
system.cpu1.timesIdled                            221                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           4807                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       35556                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     265102                       # Number of Instructions Simulated
system.cpu1.committedOps                       265102                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total               265102                       # Number of Instructions Simulated
system.cpu1.cpi                              0.685770                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.685770                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.458215                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.458215                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  483798                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 224930                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 143054                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu1.icache.replacements                   321                       # number of replacements
system.cpu1.icache.tagsinuse                91.372145                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   16670                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   436                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 38.233945                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst    91.372145                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.178461                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.178461                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst        16670                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          16670                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        16670                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           16670                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        16670                       # number of overall hits
system.cpu1.icache.overall_hits::total          16670                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          510                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          510                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          510                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           510                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          510                       # number of overall misses
system.cpu1.icache.overall_misses::total          510                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     10781500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     10781500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     10781500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     10781500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     10781500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     10781500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        17180                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        17180                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        17180                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        17180                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        17180                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        17180                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029686                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.029686                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029686                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.029686                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029686                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.029686                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21140.196078                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 21140.196078                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21140.196078                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 21140.196078                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21140.196078                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 21140.196078                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs           44                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs           44                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           74                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           74                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           74                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           74                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          436                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          436                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          436                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          436                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          436                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          436                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      8808000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      8808000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      8808000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      8808000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      8808000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      8808000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.025378                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.025378                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.025378                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.025378                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.025378                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.025378                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20201.834862                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20201.834862                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20201.834862                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 20201.834862                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20201.834862                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 20201.834862                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     0                       # number of replacements
system.cpu1.dcache.tagsinuse                27.445610                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   51579                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs               1778.586207                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data    27.445610                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.053605                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.053605                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        53407                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          53407                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        45083                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         45083                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           12                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        98490                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           98490                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        98490                       # number of overall hits
system.cpu1.dcache.overall_hits::total          98490                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          415                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          415                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          145                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          145                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           54                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          560                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           560                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          560                       # number of overall misses
system.cpu1.dcache.overall_misses::total          560                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      6026000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      6026000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3157000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3157000                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       555500                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       555500                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      9183000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      9183000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      9183000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      9183000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        53822                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        53822                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        45228                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        45228                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           66                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        99050                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        99050                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        99050                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        99050                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.007711                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.007711                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003206                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.003206                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.818182                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.818182                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005654                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.005654                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005654                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.005654                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14520.481928                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14520.481928                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21772.413793                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21772.413793                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 10287.037037                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 10287.037037                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16398.214286                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16398.214286                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16398.214286                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16398.214286                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          257                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          257                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           37                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           37                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          294                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          294                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          294                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          294                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          158                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          108                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           54                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          266                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          266                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          266                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          266                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1540500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1540500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1377000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1377000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       447500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       447500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2917500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      2917500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2917500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      2917500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002936                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002936                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002388                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002388                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.818182                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.818182                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002686                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.002686                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002686                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.002686                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data         9750                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total         9750                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data        12750                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total        12750                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  8287.037037                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  8287.037037                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10968.045113                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10968.045113                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10968.045113                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10968.045113                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          181474                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.BPredUnit.lookups                   55930                       # Number of BP lookups
system.cpu2.BPredUnit.condPredicted             52799                       # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect              1548                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups                49143                       # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits                   48122                       # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS                     857                       # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles             28647                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        313051                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      55930                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             48979                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       109339                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   4440                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 31939                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         6238                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1022                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    20302                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  327                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            180005                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.739124                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.167787                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   70666     39.26%     39.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   55453     30.81%     70.06% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    6160      3.42%     73.49% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3207      1.78%     75.27% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     684      0.38%     75.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   38160     21.20%     96.85% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1206      0.67%     97.52% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     867      0.48%     98.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    3602      2.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              180005                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.308198                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.725046                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   34354                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                28279                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                   103112                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 5207                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2815                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                308841                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2815                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   35130                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  15148                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         12314                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    98150                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                10210                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                306064                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents                   44                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands             214486                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               588858                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          588858                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               198873                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   15613                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1249                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1373                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    13264                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               87101                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              41559                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            41593                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           36327                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    253620                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               6426                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   255375                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               71                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          12537                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        11608                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           622                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       180005                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.418711                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.312032                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              68069     37.82%     37.82% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              23048     12.80%     50.62% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              41620     23.12%     73.74% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              42277     23.49%     97.23% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3294      1.83%     99.06% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1277      0.71%     99.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                306      0.17%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         180005                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     21      7.02%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      7.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    68     22.74%     29.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  210     70.23%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               123049     48.18%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.18% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               91506     35.83%     84.02% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              40820     15.98%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                255375                       # Type of FU issued
system.cpu2.iq.rate                          1.407226                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        299                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001171                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            691125                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           272626                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       253322                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                255674                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           36105                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         2679                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            7                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           43                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1636                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2815                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                    752                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   48                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             302670                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              388                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                87101                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               41559                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1159                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    48                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            43                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           509                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         1214                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1723                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               254008                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                86102                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             1367                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        42624                       # number of nop insts executed
system.cpu2.iew.exec_refs                      126828                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   52054                       # Number of branches executed
system.cpu2.iew.exec_stores                     40726                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.399694                       # Inst execution rate
system.cpu2.iew.wb_sent                        253605                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       253322                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   143679                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   148564                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.395913                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.967119                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts          14523                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           5804                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1548                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       170953                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.685416                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.035354                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        67602     39.54%     39.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        50009     29.25%     68.80% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         6225      3.64%     72.44% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         6684      3.91%     76.35% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1541      0.90%     77.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        36526     21.37%     98.62% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          553      0.32%     98.94% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1000      0.58%     99.52% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          813      0.48%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       170953                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              288127                       # Number of instructions committed
system.cpu2.commit.committedOps                288127                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        124345                       # Number of memory references committed
system.cpu2.commit.loads                        84422                       # Number of loads committed
system.cpu2.commit.membars                       5089                       # Number of memory barriers committed
system.cpu2.commit.branches                     50979                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   197443                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events                  813                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      472203                       # The number of ROB reads
system.cpu2.rob.rob_writes                     608127                       # The number of ROB writes
system.cpu2.timesIdled                            210                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           1469                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       35881                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     241270                       # Number of Instructions Simulated
system.cpu2.committedOps                       241270                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total               241270                       # Number of Instructions Simulated
system.cpu2.cpi                              0.752161                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.752161                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.329502                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.329502                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  440107                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 204983                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 128465                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu2.icache.replacements                   323                       # number of replacements
system.cpu2.icache.tagsinuse                83.164978                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   19795                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   438                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                 45.194064                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst    83.164978                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.162432                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.162432                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst        19795                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          19795                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        19795                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           19795                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        19795                       # number of overall hits
system.cpu2.icache.overall_hits::total          19795                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          507                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          507                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          507                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           507                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          507                       # number of overall misses
system.cpu2.icache.overall_misses::total          507                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      6587500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      6587500                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      6587500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      6587500                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      6587500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      6587500                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        20302                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        20302                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        20302                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        20302                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        20302                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        20302                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024973                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.024973                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024973                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.024973                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024973                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.024973                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 12993.096647                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 12993.096647                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 12993.096647                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 12993.096647                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 12993.096647                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 12993.096647                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           69                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           69                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           69                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           69                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           69                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           69                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          438                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          438                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          438                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          438                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          438                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          438                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      5265000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      5265000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      5265000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      5265000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      5265000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      5265000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021574                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021574                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021574                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.021574                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021574                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.021574                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12020.547945                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12020.547945                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12020.547945                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12020.547945                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12020.547945                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12020.547945                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     0                       # number of replacements
system.cpu2.dcache.tagsinuse                24.743159                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   46094                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs               1646.214286                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data    24.743159                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.048326                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.048326                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        49553                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          49553                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        39712                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         39712                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           11                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        89265                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           89265                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        89265                       # number of overall hits
system.cpu2.dcache.overall_hits::total          89265                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          426                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          426                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          142                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          142                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           58                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          568                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           568                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          568                       # number of overall misses
system.cpu2.dcache.overall_misses::total          568                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5684000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      5684000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2389500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2389500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       598500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       598500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      8073500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      8073500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      8073500                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      8073500                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        49979                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        49979                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        39854                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        39854                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        89833                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        89833                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        89833                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        89833                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.008524                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.008524                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003563                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.003563                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.840580                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.840580                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.006323                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.006323                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.006323                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.006323                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13342.723005                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 13342.723005                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 16827.464789                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 16827.464789                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10318.965517                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 10318.965517                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14213.908451                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 14213.908451                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14213.908451                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 14213.908451                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          266                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          266                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           35                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          301                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          301                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          301                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          301                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          160                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          160                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          107                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           58                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          267                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1316000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1316000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1150500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1150500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       482500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       482500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      2466500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      2466500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      2466500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      2466500                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003201                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003201                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002685                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002685                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.840580                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.840580                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002972                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.002972                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002972                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.002972                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data         8225                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total         8225                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 10752.336449                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 10752.336449                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  8318.965517                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  8318.965517                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data  9237.827715                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total  9237.827715                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data  9237.827715                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total  9237.827715                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          181164                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.BPredUnit.lookups                   41552                       # Number of BP lookups
system.cpu3.BPredUnit.condPredicted             38392                       # Number of conditional branches predicted
system.cpu3.BPredUnit.condIncorrect              1515                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.BTBLookups                34829                       # Number of BTB lookups
system.cpu3.BPredUnit.BTBHits                   33780                       # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.usedRAS                     860                       # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles             36927                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        218203                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      41552                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             34640                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                        84802                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   4380                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 47727                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         6229                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles          974                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    28719                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  307                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            179453                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.215934                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            1.926514                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   94651     52.74%     52.74% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   45326     25.26%     78.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                   10365      5.78%     83.78% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3238      1.80%     85.58% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     710      0.40%     85.98% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   19490     10.86%     96.84% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1177      0.66%     97.49% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     887      0.49%     97.99% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3609      2.01%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              179453                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.229361                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.204450                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   46454                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                40187                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    74815                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 8979                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2789                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                213927                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2789                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   47212                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  26606                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         12751                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    66126                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                17740                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                211407                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents                   35                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands             144414                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               382760                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          382760                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               129180                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   15234                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1257                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1396                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    20650                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               54196                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              23010                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            27226                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           17768                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    169289                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded              10641                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   175038                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued               41                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          12721                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        11252                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           865                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       179453                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        0.975397                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.233089                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              92486     51.54%     51.54% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              34868     19.43%     70.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              23272     12.97%     83.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              23945     13.34%     97.28% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3213      1.79%     99.07% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1245      0.69%     99.76% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                315      0.18%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 48      0.03%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         179453                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     20      6.92%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      6.92% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    59     20.42%     27.34% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  210     72.66%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu                90201     51.53%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     51.53% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               62467     35.69%     87.22% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              22370     12.78%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                175038                       # Type of FU issued
system.cpu3.iq.rate                          0.966185                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        289                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001651                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            529859                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           192688                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       173081                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                175327                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           17671                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2642                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1490                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2789                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                    857                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   46                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             208183                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              370                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                54196                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               23010                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1178                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    46                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            37                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           501                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         1172                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1673                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               173760                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                53123                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1278                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        28253                       # number of nop insts executed
system.cpu3.iew.exec_refs                       75420                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   37599                       # Number of branches executed
system.cpu3.iew.exec_stores                     22297                       # Number of stores executed
system.cpu3.iew.exec_rate                    0.959131                       # Inst execution rate
system.cpu3.iew.wb_sent                        173368                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       173081                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                    92251                       # num instructions producing a value
system.cpu3.iew.wb_consumers                    97140                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      0.955383                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.949671                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts          14656                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           9776                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1515                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       170436                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.135365                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.770418                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        95921     56.28%     56.28% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        35624     20.90%     77.18% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6200      3.64%     80.82% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3        10664      6.26%     87.08% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1534      0.90%     87.98% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        18221     10.69%     98.67% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          461      0.27%     98.94% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1004      0.59%     99.53% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          807      0.47%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       170436                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              193507                       # Number of instructions committed
system.cpu3.commit.committedOps                193507                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                         73074                       # Number of memory references committed
system.cpu3.commit.loads                        51554                       # Number of loads committed
system.cpu3.commit.membars                       9056                       # Number of memory barriers committed
system.cpu3.commit.branches                     36531                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   131724                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.bw_lim_events                  807                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      377205                       # The number of ROB reads
system.cpu3.rob.rob_writes                     419128                       # The number of ROB writes
system.cpu3.timesIdled                            218                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1711                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       36191                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     157136                       # Number of Instructions Simulated
system.cpu3.committedOps                       157136                       # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total               157136                       # Number of Instructions Simulated
system.cpu3.cpi                              1.152912                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.152912                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.867369                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.867369                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  286066                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 135262                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                  77098                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu3.icache.replacements                   322                       # number of replacements
system.cpu3.icache.tagsinuse                86.042865                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   28227                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   436                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                 64.740826                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst    86.042865                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.168052                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.168052                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst        28227                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          28227                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        28227                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           28227                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        28227                       # number of overall hits
system.cpu3.icache.overall_hits::total          28227                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          492                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          492                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          492                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           492                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          492                       # number of overall misses
system.cpu3.icache.overall_misses::total          492                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6235000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      6235000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      6235000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      6235000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      6235000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      6235000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        28719                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        28719                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        28719                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        28719                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        28719                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        28719                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.017132                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.017132                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.017132                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.017132                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.017132                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.017132                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12672.764228                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 12672.764228                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12672.764228                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 12672.764228                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12672.764228                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 12672.764228                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           56                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           56                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           56                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           56                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           56                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          436                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          436                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          436                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          436                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          436                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          436                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4972000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      4972000                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4972000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      4972000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4972000                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      4972000                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.015182                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.015182                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.015182                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.015182                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.015182                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.015182                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11403.669725                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11403.669725                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11403.669725                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 11403.669725                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11403.669725                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 11403.669725                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     0                       # number of replacements
system.cpu3.dcache.tagsinuse                25.903799                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   27667                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs                988.107143                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data    25.903799                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.050593                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.050593                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        35065                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          35065                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        21307                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         21307                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           17                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             17                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        56372                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           56372                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        56372                       # number of overall hits
system.cpu3.dcache.overall_hits::total          56372                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          369                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          369                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           57                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          508                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           508                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          508                       # number of overall misses
system.cpu3.dcache.overall_misses::total          508                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4880000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      4880000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2424000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2424000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       623500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       623500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      7304000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      7304000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      7304000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      7304000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        35434                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        35434                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        21446                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        21446                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           74                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           74                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        56880                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        56880                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        56880                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        56880                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.010414                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.010414                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.006481                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.006481                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.770270                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.770270                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008931                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.008931                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008931                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.008931                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13224.932249                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 13224.932249                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17438.848921                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 17438.848921                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10938.596491                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 10938.596491                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14377.952756                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 14377.952756                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14377.952756                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 14377.952756                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          204                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          204                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           34                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          238                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          238                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          238                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          238                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          165                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          165                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          270                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          270                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1399500                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1399500                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1252500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1252500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       509500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       509500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2652000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2652000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2652000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2652000                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004657                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004657                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.004896                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.004896                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.770270                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.770270                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004747                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.004747                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004747                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.004747                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  8481.818182                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  8481.818182                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 11928.571429                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 11928.571429                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  8938.596491                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  8938.596491                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9822.222222                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9822.222222                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9822.222222                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9822.222222                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       434.763271                       # Cycle average of tags in use
system.l2c.total_refs                            1477                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           535                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.760748                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks            0.835045                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           293.557210                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data            59.439095                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst            69.391444                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data             5.684600                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst             3.455152                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data             0.725294                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst             0.907046                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data             0.768385                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.004479                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.000907                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.001059                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000087                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.000053                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.000011                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.000014                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.000012                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.006634                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                236                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                348                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                428                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                433                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1477                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 236                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 348                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 428                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 433                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1477                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                236                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                348                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                428                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                433                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   1477                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              361                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               88                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               10                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  545                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            19                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            18                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            19                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                76                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               361                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                88                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   676                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              361                       # number of overall misses
system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               88                       # number of overall misses
system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               10                       # number of overall misses
system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                3                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  676                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     17680000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      4074500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      4823500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data       381000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst       461000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data        68500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       144000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        68500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       27701000                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      5009000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       896000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       701499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       662000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      7268499                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     17680000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      9083500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      4823500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1277000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst       461000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data       769999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       144000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       730500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        34969499                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     17680000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      9083500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      4823500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1277000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst       461000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data       769999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       144000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       730500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       34969499                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            597                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            436                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            438                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            436                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               2022                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           18                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           19                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             597                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             436                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             438                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             436                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2153                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            597                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            436                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            438                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            436                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2153                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.604690                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.201835                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.583333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.022831                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.006881                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.269535                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.863636                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.962025                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.604690                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.201835                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.022831                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.006881                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.313980                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.604690                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.201835                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.022831                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.006881                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.313980                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48975.069252                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 55060.810811                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54812.500000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 54428.571429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst        46100                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        68500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst        48000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        68500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 50827.522936                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53287.234043                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68923.076923                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58458.250000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55166.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 55484.725191                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 48975.069252                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 54068.452381                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 54812.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        63850                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst        46100                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 59230.692308                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst        48000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 56192.307692                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51730.028107                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 48975.069252                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 54068.452381                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 54812.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        63850                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst        46100                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 59230.692308                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst        48000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 56192.307692                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51730.028107                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 7                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  7                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 7                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          361                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           86                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst            6                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             538                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           19                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           18                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           19                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           76                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          361                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           86                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              669                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          361                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           86                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             669                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     13144576                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3156576                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      3651132                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data       293010                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst       201008                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data        56002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst        56004                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        56002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     20614310                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       194011                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       181016                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       190518                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       204511                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       770056                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3841108                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       734514                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       550017                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       511018                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      5636657                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     13144576                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      6997684                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      3651132                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data      1027524                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst       201008                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       606019                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst        56004                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       567020                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     26250967                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     13144576                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      6997684                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      3651132                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data      1027524                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst       201008                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       606019                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst        56004                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       567020                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     26250967                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.604690                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.197248                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.013699                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.004587                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.266073                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.863636                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.962025                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.604690                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.197248                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.013699                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.004587                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.310729                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.604690                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.197248                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.013699                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.004587                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.310729                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36411.567867                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42656.432432                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42455.023256                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 33501.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        56002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        28002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        56002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 38316.561338                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10211.105263                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10056.444444                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10027.263158                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10225.550000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10132.315789                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40862.851064                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56501.076923                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45834.750000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42584.833333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 43027.916031                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36411.567867                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41652.880952                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42455.023256                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51376.200000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 33501.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46616.846154                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        28002                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43616.923077                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39239.113602                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36411.567867                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41652.880952                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42455.023256                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51376.200000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 33501.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46616.846154                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        28002                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43616.923077                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39239.113602                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------