path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000105                       # Number of seconds simulated
sim_ticks                                   104830500                       # Number of ticks simulated
final_tick                                  104830500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 100032                       # Simulator instruction rate (inst/s)
host_op_rate                                   100032                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               10132772                       # Simulator tick rate (ticks/s)
host_mem_usage                                 236868                       # Number of bytes of host memory used
host_seconds                                    10.35                       # Real time elapsed on the host
sim_insts                                     1034897                       # Number of instructions simulated
sim_ops                                       1034897                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst            22784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             5184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                42112                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        22784                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         5184                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          192                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           28416                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               356                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                81                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                 3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   658                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           217341327                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data           102565570                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            49451257                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            12210187                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             1831528                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7936621                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             2442037                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7936621                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               401715150                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      217341327                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       49451257                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        1831528                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        2442037                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          271066150                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          217341327                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data          102565570                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           49451257                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           12210187                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            1831528                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7936621                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            2442037                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7936621                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              401715150                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           659                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                            980                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                        42112                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                  42112                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                 72                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                    50                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                    71                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                    36                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                    31                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                    29                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                    23                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                    19                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                    53                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                    54                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                    71                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                   60                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                    5                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                   15                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                   20                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                   78                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                   44                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                       104802500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                     659                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                      0                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                   72                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                       390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       195                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                        2987155                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                  17761155                       # Sum of mem lat for all requests
system.physmem.totBusLat                      2636000                       # Total cycles spent in databus access
system.physmem.totBankLat                    12138000                       # Total cycles spent in bank access
system.physmem.avgQLat                        4532.86                       # Average queueing delay per request
system.physmem.avgBankLat                    18418.82                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  26951.68                       # Average memory access latency
system.physmem.avgRdBW                         401.72                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                 401.72                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           2.51                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.17                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                        506                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.78                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       159032.63                       # Average gap between requests
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          209662                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                   82004                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted             79765                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect              1218                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups                79291                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                   77227                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                     516                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles             16907                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        486703                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      82004                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             77743                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       159637                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3804                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 12545                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1361                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     5871                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  484                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            192893                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.523176                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.215866                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   33256     17.24%     17.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   79042     40.98%     58.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     584      0.30%     58.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     987      0.51%     59.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     454      0.24%     59.27% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   75108     38.94%     98.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     578      0.30%     98.50% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     364      0.19%     98.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2520      1.31%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              192893                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.391125                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.321370                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   17503                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                14000                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   158668                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  284                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2438                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                483730                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2438                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18159                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                    648                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         12765                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   158332                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  551                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                480873                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents                  153                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands             329027                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups               958899                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          958899                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               315995                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   13032                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               877                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           903                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     3587                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              153720                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              77689                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            74928                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           74758                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    402151                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                922                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   399521                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              164                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          10786                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined         9496                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           363                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       192893                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.071205                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.088777                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              32269     16.73%     16.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4844      2.51%     19.24% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              76822     39.83%     59.07% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              76327     39.57%     98.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1582      0.82%     99.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                687      0.36%     99.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                263      0.14%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 81      0.04%     99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 18      0.01%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         192893                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     57     25.45%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    53     23.66%     49.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  114     50.89%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               169105     42.33%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.33% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              153283     38.37%     80.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              77133     19.31%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                399521                       # Type of FU issued
system.cpu0.iq.rate                          1.905548                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        224                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000561                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads            992323                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           413903                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       397700                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                399745                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           74515                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2133                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           44                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1389                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked            4                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2438                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                    389                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   34                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             478542                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              300                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               153720                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               77689                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               806                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    35                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            44                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           327                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1115                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1442                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               398429                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               152970                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1092                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        75469                       # number of nop insts executed
system.cpu0.iew.exec_refs                      229968                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   79152                       # Number of branches executed
system.cpu0.iew.exec_stores                     76998                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.900340                       # Inst execution rate
system.cpu0.iew.wb_sent                        398024                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       397700                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   235727                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   238246                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.896863                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.989427                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts          12164                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1218                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       190472                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.448360                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.135276                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        32802     17.22%     17.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        78740     41.34%     58.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2340      1.23%     59.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          693      0.36%     60.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          545      0.29%     60.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        74330     39.02%     99.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          456      0.24%     99.70% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          249      0.13%     99.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          317      0.17%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       190472                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              466344                       # Number of instructions committed
system.cpu0.commit.committedOps                466344                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        227887                       # Number of memory references committed
system.cpu0.commit.loads                       151587                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     78187                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   314326                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events                  317                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      667502                       # The number of ROB reads
system.cpu0.rob.rob_writes                     959472                       # The number of ROB writes
system.cpu0.timesIdled                            316                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          16769                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     391341                       # Number of Instructions Simulated
system.cpu0.committedOps                       391341                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total               391341                       # Number of Instructions Simulated
system.cpu0.cpi                              0.535753                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.535753                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.866533                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.866533                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  712669                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 321346                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 231752                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.replacements                   297                       # number of replacements
system.cpu0.icache.tagsinuse               245.466325                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    5129                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   587                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  8.737649                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   245.466325                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.479426                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.479426                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst         5129                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           5129                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         5129                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            5129                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         5129                       # number of overall hits
system.cpu0.icache.overall_hits::total           5129                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          742                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          742                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          742                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           742                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          742                       # number of overall misses
system.cpu0.icache.overall_misses::total          742                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     25612000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     25612000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     25612000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     25612000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     25612000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     25612000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         5871                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         5871                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         5871                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         5871                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         5871                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         5871                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.126384                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.126384                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.126384                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.126384                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.126384                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.126384                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34517.520216                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 34517.520216                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34517.520216                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 34517.520216                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34517.520216                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 34517.520216                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          154                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          154                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          154                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          154                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          154                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          154                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          588                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          588                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          588                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          588                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          588                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          588                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     20478500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     20478500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     20478500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     20478500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     20478500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     20478500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.100153                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.100153                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.100153                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.100153                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.100153                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.100153                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34827.380952                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34827.380952                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34827.380952                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 34827.380952                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34827.380952                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 34827.380952                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     2                       # number of replacements
system.cpu0.dcache.tagsinuse               143.868426                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  153554                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                903.258824                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   143.868426                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.280993                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.280993                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        77923                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          77923                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        75708                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         75708                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           22                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             22                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       153631                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          153631                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       153631                       # number of overall hits
system.cpu0.dcache.overall_hits::total         153631                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          471                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          471                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          550                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          550                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           20                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           20                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1021                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1021                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1021                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1021                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     11085500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     11085500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     22991498                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     22991498                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       390000                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       390000                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     34076998                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     34076998                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     34076998                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     34076998                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        78394                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        78394                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        76258                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        76258                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       154652                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       154652                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       154652                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       154652                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006008                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.006008                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007212                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007212                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.476190                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.476190                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006602                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006602                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006602                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006602                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41802.723636                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 41802.723636                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        19500                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total        19500                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33376.099902                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33376.099902                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33376.099902                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33376.099902                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          196                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               14                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs           14                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          277                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          277                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          384                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          384                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          661                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          661                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          661                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          661                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          194                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          194                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          166                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          166                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           20                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           20                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          360                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          360                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          360                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          360                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4894000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4894000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      5605500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      5605500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       350000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       350000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     10499500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     10499500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     10499500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     10499500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002475                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002475                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002177                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002177                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.476190                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.476190                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002328                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002328                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002328                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002328                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33768.072289                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33768.072289                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        17500                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        17500                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29165.277778                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29165.277778                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29165.277778                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29165.277778                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          174084                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                   52904                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted             50238                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect              1268                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups                46828                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                   46138                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                     659                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles             27344                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        297398                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      52904                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             46797                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       103835                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   3694                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 29305                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         6116                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles          727                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    18660                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  267                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            169680                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.752699                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.165176                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   65845     38.81%     38.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   52566     30.98%     69.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    5632      3.32%     73.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3204      1.89%     74.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     655      0.39%     75.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   36566     21.55%     96.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1212      0.71%     97.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     766      0.45%     98.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3234      1.91%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              169680                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.303899                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.708359                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   31981                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                26240                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    98388                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 4607                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2348                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                293925                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2348                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   32683                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  13600                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         11858                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    94082                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                 8993                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                291891                       # Number of instructions processed by rename
system.cpu1.rename.LSQFullEvents                   40                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands             205019                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               562522                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          562522                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               192184                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   12835                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1091                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1214                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    11554                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               83196                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              39822                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            39557                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           34785                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    242788                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               5818                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   244431                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               88                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          10770                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        10393                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           573                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       169680                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.440541                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.314007                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              63213     37.25%     37.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              21011     12.38%     49.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              39930     23.53%     73.17% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              40650     23.96%     97.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3306      1.95%     99.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1205      0.71%     99.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                253      0.15%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 59      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         169680                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     17      5.76%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      5.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    68     23.05%     28.81% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  210     71.19%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               118248     48.38%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.38% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               87044     35.61%     83.99% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              39139     16.01%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                244431                       # Type of FU issued
system.cpu1.iq.rate                          1.404098                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        295                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001207                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            658925                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           259421                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       242675                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                244726                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           34549                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2395                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           45                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1432                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2348                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                    954                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   69                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             289058                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              345                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                83196                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               39822                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1054                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    70                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            45                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           455                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect          930                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1385                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               243269                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                82226                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1162                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        40452                       # number of nop insts executed
system.cpu1.iew.exec_refs                      121286                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   49717                       # Number of branches executed
system.cpu1.iew.exec_stores                     39060                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.397423                       # Inst execution rate
system.cpu1.iew.wb_sent                        242942                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       242675                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   138073                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   142763                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.394011                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.967148                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts          12362                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           5245                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1268                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       161217                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.716302                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.045846                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        62248     38.61%     38.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        47764     29.63%     68.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         6052      3.75%     71.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         6179      3.83%     75.83% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1571      0.97%     76.80% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        35062     21.75%     98.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          510      0.32%     98.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1010      0.63%     99.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          821      0.51%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       161217                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              276697                       # Number of instructions committed
system.cpu1.commit.committedOps                276697                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        119191                       # Number of memory references committed
system.cpu1.commit.loads                        80801                       # Number of loads committed
system.cpu1.commit.membars                       4532                       # Number of memory barriers committed
system.cpu1.commit.branches                     48885                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   190199                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events                  821                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      448868                       # The number of ROB reads
system.cpu1.rob.rob_writes                     580470                       # The number of ROB writes
system.cpu1.timesIdled                            225                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           4404                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       35576                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     232489                       # Number of Instructions Simulated
system.cpu1.committedOps                       232489                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total               232489                       # Number of Instructions Simulated
system.cpu1.cpi                              0.748784                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.748784                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.335499                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.335499                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  422509                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 197149                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 122869                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu1.icache.replacements                   317                       # number of replacements
system.cpu1.icache.tagsinuse                85.783317                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   18178                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   425                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 42.771765                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst    85.783317                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.167546                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.167546                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst        18178                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          18178                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        18178                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           18178                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        18178                       # number of overall hits
system.cpu1.icache.overall_hits::total          18178                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          482                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          482                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          482                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           482                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          482                       # number of overall misses
system.cpu1.icache.overall_misses::total          482                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      9898500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      9898500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      9898500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      9898500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      9898500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      9898500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        18660                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        18660                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        18660                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        18660                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        18660                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        18660                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.025831                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.025831                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.025831                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.025831                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.025831                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.025831                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20536.307054                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 20536.307054                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20536.307054                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 20536.307054                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20536.307054                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 20536.307054                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs           44                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs           44                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           57                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           57                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           57                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           57                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           57                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           57                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          425                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          425                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          425                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          425                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          425                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          425                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      8055000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      8055000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      8055000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      8055000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      8055000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      8055000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.022776                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.022776                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.022776                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.022776                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.022776                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.022776                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18952.941176                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18952.941176                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18952.941176                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 18952.941176                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18952.941176                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 18952.941176                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     0                       # number of replacements
system.cpu1.dcache.tagsinuse                27.224773                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   44406                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs               1585.928571                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data    27.224773                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.053173                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.053173                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        47254                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          47254                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        38186                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         38186                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        85440                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           85440                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        85440                       # number of overall hits
system.cpu1.dcache.overall_hits::total          85440                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          407                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          407                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          137                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          137                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           53                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           53                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          544                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           544                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          544                       # number of overall misses
system.cpu1.dcache.overall_misses::total          544                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      6159500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      6159500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2649500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      2649500                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       528500                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       528500                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      8809000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      8809000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      8809000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      8809000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        47661                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        47661                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        38323                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        38323                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           67                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           67                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        85984                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        85984                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        85984                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        85984                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008539                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.008539                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003575                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.003575                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.791045                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.791045                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006327                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.006327                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006327                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.006327                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19339.416058                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 19339.416058                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  9971.698113                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  9971.698113                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16193.014706                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16193.014706                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16193.014706                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16193.014706                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          252                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          252                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           32                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           32                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          284                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          284                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          284                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          284                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          155                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          155                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          105                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           53                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           53                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          260                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          260                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          260                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          260                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1530000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1530000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1383500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1383500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       422500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       422500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2913500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      2913500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2913500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      2913500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003252                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003252                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002740                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002740                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.791045                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.791045                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003024                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.003024                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003024                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.003024                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  9870.967742                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  9870.967742                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13176.190476                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13176.190476                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  7971.698113                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  7971.698113                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11205.769231                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11205.769231                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11205.769231                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11205.769231                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          173759                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.BPredUnit.lookups                   43658                       # Number of BP lookups
system.cpu2.BPredUnit.condPredicted             40905                       # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect              1282                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups                37514                       # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits                   36718                       # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS                     654                       # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles             33388                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        235313                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      43658                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             37372                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                        88227                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   3786                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 41179                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         6107                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles          690                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    25041                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  268                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            172022                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.367924                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.005612                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   83795     48.71%     48.71% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   46271     26.90%     75.61% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    8744      5.08%     80.69% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3171      1.84%     82.54% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     732      0.43%     82.96% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   24119     14.02%     96.98% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1119      0.65%     97.63% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     764      0.44%     98.08% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    3307      1.92%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              172022                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.251256                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.354249                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   40935                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                35177                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    79843                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 7534                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2426                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                231751                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2426                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   41648                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  22387                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         11999                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    72579                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                14876                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                229374                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents                   35                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands             158064                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               425055                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          425055                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               145196                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   12868                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1106                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1225                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    17601                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               61347                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              27349                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            30218                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           22307                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    186544                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               8963                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   190992                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued              109                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          11074                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        10969                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           650                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       172022                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.110277                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.273783                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              81441     47.34%     47.34% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              30126     17.51%     64.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              27409     15.93%     80.79% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              28202     16.39%     97.18% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3303      1.92%     99.10% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1178      0.68%     99.79% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                256      0.15%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 52      0.03%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 55      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         172022                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     11      3.83%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      3.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    66     23.00%     26.83% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  210     73.17%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu                96218     50.38%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.38% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               68109     35.66%     86.04% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              26665     13.96%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                190992                       # Type of FU issued
system.cpu2.iq.rate                          1.099178                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        287                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001503                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            554402                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           206628                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       189208                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                191279                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           22028                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         2518                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           47                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1460                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2426                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                    904                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   54                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             226591                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              328                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                61347                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               27349                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1066                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    54                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            47                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           465                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect          929                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1394                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               189816                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                60231                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             1176                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        31084                       # number of nop insts executed
system.cpu2.iew.exec_refs                       86812                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   40244                       # Number of branches executed
system.cpu2.iew.exec_stores                     26581                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.092410                       # Inst execution rate
system.cpu2.iew.wb_sent                        189478                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       189208                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   103581                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   108246                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.088911                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.956904                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts          12701                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           8313                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1282                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       163490                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.308153                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.875243                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        83402     51.01%     51.01% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        38322     23.44%     74.45% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         6091      3.73%     78.18% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         9201      5.63%     83.81% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1555      0.95%     84.76% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        22612     13.83%     98.59% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          481      0.29%     98.88% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1011      0.62%     99.50% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          815      0.50%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       163490                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              213870                       # Number of instructions committed
system.cpu2.commit.committedOps                213870                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                         84718                       # Number of memory references committed
system.cpu2.commit.loads                        58829                       # Number of loads committed
system.cpu2.commit.membars                       7592                       # Number of memory barriers committed
system.cpu2.commit.branches                     39438                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   146274                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events                  815                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      388659                       # The number of ROB reads
system.cpu2.rob.rob_writes                     455572                       # The number of ROB writes
system.cpu2.timesIdled                            220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           1737                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       35901                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     176057                       # Number of Instructions Simulated
system.cpu2.committedOps                       176057                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total               176057                       # Number of Instructions Simulated
system.cpu2.cpi                              0.986947                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.986947                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.013225                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.013225                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  319017                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 150022                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                  88362                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu2.icache.replacements                   319                       # number of replacements
system.cpu2.icache.tagsinuse                80.119670                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   24566                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   429                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                 57.263403                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst    80.119670                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.156484                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.156484                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst        24566                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          24566                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        24566                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           24566                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        24566                       # number of overall hits
system.cpu2.icache.overall_hits::total          24566                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          475                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          475                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          475                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           475                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          475                       # number of overall misses
system.cpu2.icache.overall_misses::total          475                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      6356500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      6356500                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      6356500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      6356500                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      6356500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      6356500                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        25041                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        25041                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        25041                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        25041                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        25041                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        25041                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.018969                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.018969                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.018969                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.018969                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.018969                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.018969                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13382.105263                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 13382.105263                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13382.105263                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 13382.105263                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13382.105263                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 13382.105263                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           46                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           46                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           46                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           46                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           46                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           46                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          429                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          429                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          429                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          429                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          429                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          429                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      5130000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      5130000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      5130000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      5130000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      5130000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      5130000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.017132                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.017132                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.017132                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.017132                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.017132                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.017132                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11958.041958                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11958.041958                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11958.041958                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 11958.041958                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11958.041958                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 11958.041958                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     0                       # number of replacements
system.cpu2.dcache.tagsinuse                24.750979                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   32016                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs                      1104                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data    24.750979                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.048342                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.048342                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        37788                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          37788                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        25681                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         25681                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           16                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        63469                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           63469                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        63469                       # number of overall hits
system.cpu2.dcache.overall_hits::total          63469                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          397                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          397                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          133                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          133                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           59                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           59                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          530                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           530                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          530                       # number of overall misses
system.cpu2.dcache.overall_misses::total          530                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5135500                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      5135500                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2343500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2343500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       565000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       565000                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      7479000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      7479000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      7479000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      7479000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        38185                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        38185                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        25814                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        25814                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           75                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           75                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        63999                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        63999                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        63999                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        63999                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.010397                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.010397                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.005152                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.005152                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.786667                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.786667                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.008281                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.008281                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.008281                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.008281                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12935.768262                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 12935.768262                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17620.300752                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 17620.300752                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  9576.271186                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  9576.271186                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14111.320755                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 14111.320755                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14111.320755                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 14111.320755                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          227                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          227                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           32                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           32                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          259                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          259                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          259                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          259                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          170                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          101                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          101                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           59                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           59                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          271                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          271                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          271                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          271                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1409000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1409000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1142500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1142500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       447000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       447000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      2551500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      2551500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      2551500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      2551500                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.004452                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.004452                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003913                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003913                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.786667                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.786667                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004234                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.004234                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004234                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.004234                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  8288.235294                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  8288.235294                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11311.881188                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11311.881188                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  7576.271186                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  7576.271186                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data  9415.129151                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total  9415.129151                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data  9415.129151                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total  9415.129151                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          173449                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.BPredUnit.lookups                   53688                       # Number of BP lookups
system.cpu3.BPredUnit.condPredicted             50962                       # Number of conditional branches predicted
system.cpu3.BPredUnit.condIncorrect              1276                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.BTBLookups                47521                       # Number of BTB lookups
system.cpu3.BPredUnit.BTBHits                   46771                       # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.usedRAS                     661                       # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles             27478                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        301358                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      53688                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             47432                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       105431                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   3739                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 29902                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         6125                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles          699                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    19205                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  263                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            172027                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.751806                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.162661                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   66596     38.71%     38.71% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   53420     31.05%     69.77% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    5840      3.39%     73.16% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3208      1.86%     75.03% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     724      0.42%     75.45% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   37059     21.54%     96.99% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1114      0.65%     97.64% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     769      0.45%     98.08% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3297      1.92%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              172027                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.309532                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.737444                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   32330                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                26595                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    99738                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 4852                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2387                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                297869                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2387                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   33042                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  14161                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         11648                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    95158                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                 9506                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                295495                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                     6                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents                   42                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands             206972                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               568769                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          568769                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               194051                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   12921                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1094                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1213                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    12164                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               84321                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              40263                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            40233                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           35230                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    245462                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               6061                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   247263                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued               84                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          10948                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        10583                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           569                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       172027                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.437350                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.311410                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              63993     37.20%     37.20% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              21775     12.66%     49.86% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              40281     23.42%     73.27% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              41063     23.87%     97.14% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3352      1.95%     99.09% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1207      0.70%     99.79% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                253      0.15%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 48      0.03%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 55      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         172027                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     11      3.83%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      3.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    66     23.00%     26.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  210     73.17%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               119304     48.25%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.25% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               88373     35.74%     83.99% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              39586     16.01%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                247263                       # Type of FU issued
system.cpu3.iq.rate                          1.425566                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        287                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001161                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            666924                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           262516                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       245480                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                247550                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           34961                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2463                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           45                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1469                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2387                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                    786                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   47                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             292666                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              339                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                84321                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               40263                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1055                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    46                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            45                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           463                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect          932                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1395                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               246084                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                83306                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1179                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        41143                       # number of nop insts executed
system.cpu3.iew.exec_refs                      122808                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   50377                       # Number of branches executed
system.cpu3.iew.exec_stores                     39502                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.418769                       # Inst execution rate
system.cpu3.iew.wb_sent                        245746                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       245480                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   139608                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   144273                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.415286                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.967665                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts          12526                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           5492                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1276                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       163516                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.713105                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     2.043722                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        63247     38.68%     38.68% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        48404     29.60%     68.28% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6092      3.73%     72.01% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         6399      3.91%     75.92% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1556      0.95%     76.87% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        35437     21.67%     98.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          553      0.34%     98.88% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1016      0.62%     99.50% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          812      0.50%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       163516                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              280120                       # Number of instructions committed
system.cpu3.commit.committedOps                280120                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                        120652                       # Number of memory references committed
system.cpu3.commit.loads                        81858                       # Number of loads committed
system.cpu3.commit.membars                       4779                       # Number of memory barriers committed
system.cpu3.commit.branches                     49540                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   192312                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.bw_lim_events                  812                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      454763                       # The number of ROB reads
system.cpu3.rob.rob_writes                     587684                       # The number of ROB writes
system.cpu3.timesIdled                            212                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1422                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       36211                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     235010                       # Number of Instructions Simulated
system.cpu3.committedOps                       235010                       # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total               235010                       # Number of Instructions Simulated
system.cpu3.cpi                              0.738049                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.738049                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.354923                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.354923                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  427031                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 198982                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 124365                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu3.icache.replacements                   318                       # number of replacements
system.cpu3.icache.tagsinuse                83.493816                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   18731                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   428                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                 43.764019                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst    83.493816                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.163074                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.163074                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst        18731                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          18731                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        18731                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           18731                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        18731                       # number of overall hits
system.cpu3.icache.overall_hits::total          18731                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          474                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          474                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          474                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           474                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          474                       # number of overall misses
system.cpu3.icache.overall_misses::total          474                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6191000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      6191000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      6191000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      6191000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      6191000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      6191000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        19205                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        19205                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        19205                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        19205                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        19205                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        19205                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.024681                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.024681                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.024681                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.024681                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.024681                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.024681                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13061.181435                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13061.181435                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13061.181435                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13061.181435                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13061.181435                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13061.181435                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           46                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           46                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           46                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           46                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           46                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           46                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          428                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          428                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          428                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          428                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          428                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          428                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4970500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      4970500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4970500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      4970500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4970500                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      4970500                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.022286                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.022286                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.022286                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.022286                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.022286                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.022286                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11613.317757                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11613.317757                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11613.317757                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 11613.317757                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11613.317757                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 11613.317757                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     0                       # number of replacements
system.cpu3.dcache.tagsinuse                25.854093                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   44811                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs               1600.392857                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data    25.854093                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.050496                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.050496                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        47901                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          47901                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        38585                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         38585                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           11                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        86486                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           86486                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        86486                       # number of overall hits
system.cpu3.dcache.overall_hits::total          86486                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          426                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          426                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          142                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          142                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           56                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          568                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           568                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          568                       # number of overall misses
system.cpu3.dcache.overall_misses::total          568                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      5342000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      5342000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2332500                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2332500                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       555000                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       555000                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      7674500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      7674500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      7674500                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      7674500                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        48327                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        48327                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        38727                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        38727                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           67                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           67                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        87054                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        87054                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        87054                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        87054                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.008815                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.008815                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003667                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.003667                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.835821                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.835821                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.006525                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.006525                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.006525                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.006525                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12539.906103                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 12539.906103                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16426.056338                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 16426.056338                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9910.714286                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  9910.714286                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13511.443662                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 13511.443662                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13511.443662                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 13511.443662                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          273                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          273                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           33                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          306                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          306                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          306                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          306                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          153                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          153                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          109                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           56                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          262                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          262                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          262                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          262                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1265000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1265000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1159500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1159500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       443000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       443000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2424500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2424500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2424500                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2424500                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003166                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003166                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002815                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002815                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.835821                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.835821                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003010                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003010                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003010                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003010                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  8267.973856                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  8267.973856                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10637.614679                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10637.614679                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  7910.714286                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  7910.714286                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9253.816794                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9253.816794                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9253.816794                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9253.816794                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       425.296596                       # Cycle average of tags in use
system.l2c.total_refs                            1448                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           525                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.758095                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks            0.828895                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           289.891501                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data            59.268437                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst            63.508816                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data             5.639642                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst             2.310248                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data             0.728233                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst             2.354110                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data             0.766714                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.004423                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.000904                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.000969                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000086                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.000035                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.000011                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.000036                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.000012                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.006490                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                229                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                342                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                421                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                424                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1448                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 229                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 342                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 421                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 424                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1448                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                229                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                342                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                421                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                424                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   1448                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              359                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               83                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst                8                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  537                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            19                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            18                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            15                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                72                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               359                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                83                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                 8                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   668                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              359                       # number of overall misses
system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               83                       # number of overall misses
system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
system.l2c.overall_misses::cpu2.inst                8                       # number of overall misses
system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                4                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  668                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     17565000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      4069000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      4146500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data       381000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst       396000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data        68500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       233000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        68500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       26927500                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      5000500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       881000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       699500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       661500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      7242500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     17565000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      9069500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      4146500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1262000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst       396000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data       768000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       233000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       730000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        34170000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     17565000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      9069500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      4146500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1262000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst       396000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data       768000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       233000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       730000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       34170000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            588                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            425                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            429                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            428                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               1985                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           18                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           15                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              75                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             588                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             425                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             429                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             428                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2116                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            588                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            425                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            429                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            428                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2116                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.610544                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.195294                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.583333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.018648                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.009346                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.270529                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.863636                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.960000                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.610544                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.195294                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.018648                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.009346                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.315690                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.610544                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.195294                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.018648                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.009346                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.315690                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48927.576602                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 54986.486486                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49957.831325                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 54428.571429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst        49500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        68500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst        58250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        68500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 50144.320298                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53196.808511                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67769.230769                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58291.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data        55125                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 55286.259542                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 48927.576602                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 53985.119048                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 49957.831325                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        63100                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst        49500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 59076.923077                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst        58250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 56153.846154                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51152.694611                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 48927.576602                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 53985.119048                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 49957.831325                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        63100                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst        49500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 59076.923077                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst        58250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 56153.846154                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51152.694611                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu0.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 9                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          357                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           81                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             528                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           19                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           18                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           15                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           72                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          357                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           81                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              659                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          357                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           81                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             659                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     13017059                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3150576                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      3026126                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data       293010                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst       103002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data        56002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       181507                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        56002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     19883284                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       193013                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       181515                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       153009                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       200519                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       728056                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3829610                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       719513                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       549018                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       511018                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      5609159                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     13017059                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      6980186                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      3026126                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data      1012523                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst       103002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       605020                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       181507                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       567020                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     25492443                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     13017059                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      6980186                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      3026126                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data      1012523                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst       103002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       605020                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       181507                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       567020                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     25492443                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.190588                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.006993                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.009346                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.265995                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.863636                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.960000                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.190588                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006993                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.009346                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.311437                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.190588                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006993                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.009346                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.311437                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36462.350140                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42575.351351                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 37359.580247                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41858.571429                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        34334                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        56002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 45376.750000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        56002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 37657.734848                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.578947                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10084.166667                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10200.600000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10025.950000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.888889                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40740.531915                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55347.153846                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45751.500000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42584.833333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 42818.007634                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36462.350140                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41548.726190                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 37359.580247                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50626.150000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        34334                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data        46540                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 45376.750000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43616.923077                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 38683.525038                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36462.350140                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41548.726190                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37359.580247                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50626.150000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        34334                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data        46540                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45376.750000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43616.923077                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 38683.525038                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------