path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000104                       # Number of seconds simulated
sim_ticks                                   104317500                       # Number of ticks simulated
final_tick                                  104317500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 190796                       # Simulator instruction rate (inst/s)
host_op_rate                                   190795                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               19532213                       # Simulator tick rate (ticks/s)
host_mem_usage                                 225896                       # Number of bytes of host memory used
host_seconds                                     5.34                       # Real time elapsed on the host
sim_insts                                     1018993                       # Number of instructions simulated
sim_ops                                       1018993                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                       41984                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                  28224                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                        0                       # Number of bytes written to this memory
system.physmem.num_reads                          656                       # Number of read requests responded to by this memory
system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                      402463633                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                 270558631                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total                     402463633                       # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          208636                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                   80640                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted             78657                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect              1043                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups                79781                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                   77332                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                     408                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles             16565                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        478922                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      80640                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             77740                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       158137                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3216                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 12889                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1227                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     5515                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  447                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            190846                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.509468                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.192643                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   32709     17.14%     17.14% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   78517     41.14%     58.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     548      0.29%     58.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     994      0.52%     59.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     666      0.35%     59.44% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   74596     39.09%     98.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     801      0.42%     98.94% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     243      0.13%     99.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    1772      0.93%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              190846                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.386510                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.295491                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   16943                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                14345                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   157232                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  303                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2023                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                476750                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2023                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   17547                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   1397                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         12300                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   156956                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  623                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                474177                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents                  220                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands             323986                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups               945682                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          945682                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               313636                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   10350                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               803                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           824                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     3595                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              152097                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              76745                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            74317                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           74189                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    396725                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                846                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   395036                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued               98                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined           8285                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined         7136                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           287                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       190846                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.069920                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.087146                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              31787     16.66%     16.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               5152      2.70%     19.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              75953     39.80%     59.15% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              75299     39.46%     98.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1582      0.83%     99.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                772      0.40%     99.84% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                222      0.12%     99.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 71      0.04%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  8      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         190846                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     35     14.96%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     14.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    80     34.19%     49.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  119     50.85%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               166893     42.25%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.25% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              151805     38.43%     80.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              76338     19.32%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                395036                       # Type of FU issued
system.cpu0.iq.rate                          1.893422                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        234                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000592                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads            981250                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           405901                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       393576                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                395270                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           73924                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         1695                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           45                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1038                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2023                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   1027                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   29                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             472373                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              357                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               152097                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               76745                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               745                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    27                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            45                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           467                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect          734                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1201                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               394155                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               151500                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts              881                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        74802                       # number of nop insts executed
system.cpu0.iew.exec_refs                      227728                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   78432                       # Number of branches executed
system.cpu0.iew.exec_stores                     76228                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.889199                       # Inst execution rate
system.cpu0.iew.wb_sent                        393836                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       393576                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   233255                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   235364                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.886424                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.991039                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts        462799                       # The number of committed instructions
system.cpu0.commit.commitCommittedOps          462799                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts           9535                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1043                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       188840                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.450747                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.135046                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        32333     17.12%     17.12% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        78258     41.44%     58.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2188      1.16%     59.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          719      0.38%     60.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          659      0.35%     60.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        73614     38.98%     99.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          485      0.26%     99.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          280      0.15%     99.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          304      0.16%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       188840                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              462799                       # Number of instructions committed
system.cpu0.commit.committedOps                462799                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        226109                       # Number of memory references committed
system.cpu0.commit.loads                       150402                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     77595                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   311966                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events                  304                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      659709                       # The number of ROB reads
system.cpu0.rob.rob_writes                     946703                       # The number of ROB writes
system.cpu0.timesIdled                            320                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          17790                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     388389                       # Number of Instructions Simulated
system.cpu0.committedOps                       388389                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total               388389                       # Number of Instructions Simulated
system.cpu0.cpi                              0.537183                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.537183                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.861563                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.861563                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  705230                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 317935                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 229503                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.replacements                   294                       # number of replacements
system.cpu0.icache.tagsinuse               244.353680                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    4810                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   581                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  8.278830                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   244.353680                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.477253                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.477253                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst         4810                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           4810                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         4810                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            4810                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         4810                       # number of overall hits
system.cpu0.icache.overall_hits::total           4810                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          705                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          705                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          705                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           705                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          705                       # number of overall misses
system.cpu0.icache.overall_misses::total          705                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     27622000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     27622000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     27622000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     27622000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     27622000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     27622000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         5515                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         5515                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         5515                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         5515                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         5515                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         5515                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.127833                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.127833                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.127833                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39180.141844                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39180.141844                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39180.141844                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        15500                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs        15500                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          123                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          123                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          123                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          123                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          123                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          123                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          582                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          582                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          582                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          582                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          582                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          582                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     21369000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     21369000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     21369000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     21369000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     21369000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     21369000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105530                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105530                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105530                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36716.494845                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36716.494845                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36716.494845                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     9                       # number of replacements
system.cpu0.dcache.tagsinuse               140.432794                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                   97328                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   174                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                559.356322                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   140.432794                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.274283                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.274283                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        77005                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          77005                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        75125                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         75125                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           23                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             23                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       152130                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          152130                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       152130                       # number of overall hits
system.cpu0.dcache.overall_hits::total         152130                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          517                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          517                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          540                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          540                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           19                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           19                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1057                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1057                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1057                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1057                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     14734500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     14734500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     24692984                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     24692984                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       371000                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       371000                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     39427484                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     39427484                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     39427484                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     39427484                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        77522                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        77522                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        75665                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        75665                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       153187                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       153187                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       153187                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       153187                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006669                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007137                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.452381                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006900                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006900                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data        28500                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45727.748148                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19526.315789                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37301.309366                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37301.309366                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       180500                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8595.238095                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            6                       # number of writebacks
system.cpu0.dcache.writebacks::total                6                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          327                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          327                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          368                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          368                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          695                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          695                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          695                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          695                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          190                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          190                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          172                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          172                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           19                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           19                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          362                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          362                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      5255000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      5255000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6251500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6251500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       314000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       314000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11506500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     11506500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11506500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     11506500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002451                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002273                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.452381                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002363                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002363                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27657.894737                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36345.930233                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16526.315789                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31785.911602                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31785.911602                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          174305                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                   52112                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted             49475                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect              1085                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups                48064                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                   46080                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                     697                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles             26834                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        291745                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      52112                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             46777                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       102740                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   3160                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 32953                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         6397                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles          670                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    18341                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  181                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            171598                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.700166                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.136223                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   68858     40.13%     40.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   52177     30.41%     70.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    5705      3.32%     73.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3354      1.95%     75.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     589      0.34%     76.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   36153     21.07%     97.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1352      0.79%     98.01% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     417      0.24%     98.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    2993      1.74%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              171598                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.298970                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.673762                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   31662                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                29517                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    97194                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 4829                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  1999                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                288983                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  1999                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   32299                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  14957                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         13738                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    92834                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                 9374                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                287085                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                    26                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                   60                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands             200836                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               551958                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          551958                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               191192                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                    9644                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1080                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1209                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    11997                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               82183                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              38955                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            39306                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           34408                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    238857                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               6064                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   241490                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined           8361                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined         7490                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           637                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       171598                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.407301                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.310079                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              65840     38.37%     38.37% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              21732     12.66%     51.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              38892     22.66%     73.70% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              40381     23.53%     97.23% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3339      1.95%     99.18% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1157      0.67%     99.85% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                163      0.09%     99.95% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 40      0.02%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 54      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         171598                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     12      4.55%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    62     23.48%     28.03% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  190     71.97%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               116592     48.28%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.28% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               86338     35.75%     84.03% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              38560     15.97%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                241490                       # Type of FU issued
system.cpu1.iq.rate                          1.385445                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        264                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001093                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            654845                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           253312                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       240391                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                241754                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           34276                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         1784                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           30                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores          861                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  1999                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   1765                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   48                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             285210                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              302                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                82183                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               38955                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1043                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    45                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            30                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           599                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect          655                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1254                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               240751                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                81429                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts              739                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        40289                       # number of nop insts executed
system.cpu1.iew.exec_refs                      119949                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   49362                       # Number of branches executed
system.cpu1.iew.exec_stores                     38520                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.381205                       # Inst execution rate
system.cpu1.iew.wb_sent                        240558                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       240391                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   136702                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   141193                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.379140                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.968192                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts        275667                       # The number of committed instructions
system.cpu1.commit.commitCommittedOps          275667                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts           9533                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           5427                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1085                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       163203                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.689105                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.043033                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        64641     39.61%     39.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        47587     29.16%     68.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         5957      3.65%     72.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         6309      3.87%     76.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1571      0.96%     77.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        34602     21.20%     98.45% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          646      0.40%     98.84% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1051      0.64%     99.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          839      0.51%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       163203                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              275667                       # Number of instructions committed
system.cpu1.commit.committedOps                275667                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        118493                       # Number of memory references committed
system.cpu1.commit.loads                        80399                       # Number of loads committed
system.cpu1.commit.membars                       4716                       # Number of memory barriers committed
system.cpu1.commit.branches                     48773                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   189391                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events                  839                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      446977                       # The number of ROB reads
system.cpu1.rob.rob_writes                     572400                       # The number of ROB writes
system.cpu1.timesIdled                            225                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           2707                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       34329                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     231385                       # Number of Instructions Simulated
system.cpu1.committedOps                       231385                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total               231385                       # Number of Instructions Simulated
system.cpu1.cpi                              0.753312                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.753312                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.327472                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.327472                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  418065                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 194844                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 121500                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu1.icache.replacements                   317                       # number of replacements
system.cpu1.icache.tagsinuse                84.541118                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   17870                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   427                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 41.850117                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst    84.541118                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.165119                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.165119                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst        17870                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          17870                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        17870                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           17870                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        17870                       # number of overall hits
system.cpu1.icache.overall_hits::total          17870                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          471                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          471                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          471                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           471                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          471                       # number of overall misses
system.cpu1.icache.overall_misses::total          471                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7203000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      7203000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      7203000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      7203000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      7203000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      7203000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        18341                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        18341                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        18341                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        18341                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        18341                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        18341                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.025680                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.025680                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.025680                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15292.993631                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15292.993631                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15292.993631                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           44                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           44                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           44                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           44                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           44                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           44                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          427                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          427                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          427                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          427                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          427                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          427                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5374000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      5374000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5374000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      5374000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5374000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      5374000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023281                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023281                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023281                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.480094                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.480094                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.480094                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     2                       # number of replacements
system.cpu1.dcache.tagsinuse                24.401572                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   44082                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs               1469.400000                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data    24.401572                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.047659                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.047659                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        46660                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          46660                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        37905                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         37905                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        84565                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           84565                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        84565                       # number of overall hits
system.cpu1.dcache.overall_hits::total          84565                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          478                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          478                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          124                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          124                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           52                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          602                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           602                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          602                       # number of overall misses
system.cpu1.dcache.overall_misses::total          602                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     10261500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total     10261500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2943000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      2943000                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data      1149500                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total      1149500                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data     13204500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total     13204500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data     13204500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total     13204500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        47138                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        47138                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        38029                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        38029                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           65                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           65                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        85167                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        85167                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        85167                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        85167                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.010140                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003261                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.800000                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007068                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007068                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21467.573222                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23733.870968                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 22105.769231                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21934.385382                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21934.385382                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu1.dcache.writebacks::total                1                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          323                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          323                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           18                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           18                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          341                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          341                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          341                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          341                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          155                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          155                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          106                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           52                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          261                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          261                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          261                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          261                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2079000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2079000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1617000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1617000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       993500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       993500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3696000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      3696000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3696000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      3696000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003288                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002787                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003065                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003065                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13412.903226                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15254.716981                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 19105.769231                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14160.919540                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14160.919540                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          174018                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.BPredUnit.lookups                   49365                       # Number of BP lookups
system.cpu2.BPredUnit.condPredicted             46733                       # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect              1149                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups                45641                       # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits                   43566                       # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS                     657                       # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles             27807                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        273933                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      49365                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             44223                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                        97490                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   3286                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 34440                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         6393                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles          776                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    19059                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  204                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            168970                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.621193                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.105353                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   71480     42.30%     42.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   49528     29.31%     71.62% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    6067      3.59%     75.21% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3620      2.14%     77.35% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     727      0.43%     77.78% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   32913     19.48%     97.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1356      0.80%     98.06% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     430      0.25%     98.31% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    2849      1.69%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              168970                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.283678                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.574165                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   32851                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                30938                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    91697                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 5032                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2059                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                271122                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2059                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   33552                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  15710                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         14412                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    87163                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                 9681                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                268918                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                    31                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents                   44                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands             188425                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               514118                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          514118                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               178130                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   10295                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1067                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1200                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    12339                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               75827                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              35627                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            36245                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           31070                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    223191                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               6330                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   225872                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined           8710                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined         8050                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           644                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       168970                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.336758                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.306399                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              68735     40.68%     40.68% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              22585     13.37%     54.05% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              35942     21.27%     75.32% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              37104     21.96%     97.28% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3355      1.99%     99.26% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5                981      0.58%     99.84% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                168      0.10%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 42      0.02%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 58      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         168970                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     19      7.04%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      7.04% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    61     22.59%     29.63% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  190     70.37%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               110495     48.92%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.92% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               80157     35.49%     84.41% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              35220     15.59%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                225872                       # Type of FU issued
system.cpu2.iq.rate                          1.297981                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        270                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001195                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            620987                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           238263                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       224632                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                226142                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           30940                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         1843                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           32                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores          852                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2059                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   1941                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   63                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             266786                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              354                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                75827                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               35627                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1018                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    57                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            32                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           683                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect          611                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1294                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               225039                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                74986                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts              833                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        37265                       # number of nop insts executed
system.cpu2.iew.exec_refs                      110171                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   46373                       # Number of branches executed
system.cpu2.iew.exec_stores                     35185                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.293194                       # Inst execution rate
system.cpu2.iew.wb_sent                        224805                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       224632                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   127007                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   131418                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.290855                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.966435                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitCommittedInsts        256708                       # The number of committed instructions
system.cpu2.commit.commitCommittedOps          256708                       # The number of committed instructions
system.cpu2.commit.commitSquashedInsts          10074                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           5686                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1149                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       160519                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.599237                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.012927                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        67924     42.32%     42.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        44668     27.83%     70.14% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         6005      3.74%     73.88% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         6542      4.08%     77.96% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1606      1.00%     78.96% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        31385     19.55%     98.51% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          504      0.31%     98.83% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1049      0.65%     99.48% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          836      0.52%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       160519                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              256708                       # Number of instructions committed
system.cpu2.commit.committedOps                256708                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        108759                       # Number of memory references committed
system.cpu2.commit.loads                        73984                       # Number of loads committed
system.cpu2.commit.membars                       4966                       # Number of memory barriers committed
system.cpu2.commit.branches                     45704                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   176579                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events                  836                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      425878                       # The number of ROB reads
system.cpu2.rob.rob_writes                     535627                       # The number of ROB writes
system.cpu2.timesIdled                            232                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           5048                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       34616                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     215254                       # Number of Instructions Simulated
system.cpu2.committedOps                       215254                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total               215254                       # Number of Instructions Simulated
system.cpu2.cpi                              0.808431                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.808431                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.236964                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.236964                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  389052                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 181919                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 111746                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu2.icache.replacements                   321                       # number of replacements
system.cpu2.icache.tagsinuse                85.227474                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   18578                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   427                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                 43.508197                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst    85.227474                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.166460                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.166460                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst        18578                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          18578                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        18578                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           18578                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        18578                       # number of overall hits
system.cpu2.icache.overall_hits::total          18578                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          481                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          481                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          481                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           481                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          481                       # number of overall misses
system.cpu2.icache.overall_misses::total          481                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     10446500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     10446500                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     10446500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     10446500                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     10446500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     10446500                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        19059                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        19059                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        19059                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        19059                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        19059                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        19059                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.025237                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.025237                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.025237                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21718.295218                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21718.295218                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21718.295218                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs        33000                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs        33000                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           54                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           54                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           54                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           54                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           54                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           54                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          427                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          427                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          427                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          427                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          427                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          427                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      8026500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      8026500                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      8026500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      8026500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      8026500                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      8026500                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.022404                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.022404                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.022404                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18797.423888                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18797.423888                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18797.423888                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     2                       # number of replacements
system.cpu2.dcache.tagsinuse                26.582846                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   40686                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs               1356.200000                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data    26.582846                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.051920                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.051920                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        43569                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          43569                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        34581                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         34581                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        78150                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           78150                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        78150                       # number of overall hits
system.cpu2.dcache.overall_hits::total          78150                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          459                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          459                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          120                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          120                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           61                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           61                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          579                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           579                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          579                       # number of overall misses
system.cpu2.dcache.overall_misses::total          579                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     10999500                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total     10999500                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2980500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2980500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data      1343500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total      1343500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data     13980000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total     13980000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data     13980000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total     13980000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        44028                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        44028                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        34701                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        34701                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           74                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           74                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        78729                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        78729                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        78729                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        78729                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.010425                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003458                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.824324                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007354                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007354                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23964.052288                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24837.500000                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 22024.590164                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 24145.077720                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 24145.077720                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu2.dcache.writebacks::total                1                       # number of writebacks
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          297                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          297                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           18                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           18                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          315                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          315                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          315                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          315                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          162                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          102                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          102                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           61                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           61                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          264                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          264                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          264                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          264                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2380000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2380000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1660000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1660000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data      1160500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total      1160500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      4040000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      4040000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      4040000                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      4040000                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003679                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002939                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.824324                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003353                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003353                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14691.358025                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16274.509804                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 19024.590164                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15303.030303                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15303.030303                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          173752                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.BPredUnit.lookups                   43974                       # Number of BP lookups
system.cpu3.BPredUnit.condPredicted             41362                       # Number of conditional branches predicted
system.cpu3.BPredUnit.condIncorrect              1065                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.BTBLookups                40218                       # Number of BTB lookups
system.cpu3.BPredUnit.BTBHits                   38243                       # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.usedRAS                     627                       # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles             31228                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        238342                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      43974                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             38870                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                        88902                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   3085                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 41810                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         6387                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles          706                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    22959                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  173                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            170982                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.393960                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.002021                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   82080     48.01%     48.01% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   46273     27.06%     75.07% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    8028      4.70%     79.76% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3581      2.09%     81.86% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     661      0.39%     82.24% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   25734     15.05%     97.30% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1333      0.78%     98.07% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     378      0.22%     98.30% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    2914      1.70%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              170982                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.253085                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.371737                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   38250                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                36210                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    81249                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 6942                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  1944                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                235582                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  1944                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   38898                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  21197                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         14171                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    74841                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                13544                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                233650                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                    34                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents                   44                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands             161376                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               435940                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          435940                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               151925                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                    9451                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1060                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1201                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    16222                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               63593                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              28573                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            31152                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           24018                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    191280                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               8270                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   196054                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined           8200                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined         7610                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           629                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       170982                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.146635                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.276395                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              79237     46.34%     46.34% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              28336     16.57%     62.91% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              28717     16.80%     79.71% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              30135     17.62%     97.33% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3289      1.92%     99.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1034      0.60%     99.86% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                139      0.08%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 41      0.02%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 54      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         170982                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     11      4.49%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      4.49% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    44     17.96%     22.45% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  190     77.55%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu                97962     49.97%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.97% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               69919     35.66%     85.63% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              28173     14.37%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                196054                       # Type of FU issued
system.cpu3.iq.rate                          1.128355                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        245                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001250                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            563338                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           207780                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       194934                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                196299                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           23899                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         1728                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           30                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores          841                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  1944                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   1688                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   45                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             231715                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              366                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                63593                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               28573                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts               992                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            30                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           631                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect          549                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1180                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               195273                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                62778                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts              781                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        32165                       # number of nop insts executed
system.cpu3.iew.exec_refs                       90920                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   41191                       # Number of branches executed
system.cpu3.iew.exec_stores                     28142                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.123860                       # Inst execution rate
system.cpu3.iew.wb_sent                        195091                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       194934                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   107675                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   111992                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.121909                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.961453                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitCommittedInsts        222296                       # The number of committed instructions
system.cpu3.commit.commitCommittedOps          222296                       # The number of committed instructions
system.cpu3.commit.commitSquashedInsts           9409                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           7641                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1065                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       162652                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.366697                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.912123                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        80351     49.40%     49.40% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        39430     24.24%     73.64% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6019      3.70%     77.34% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         8502      5.23%     82.57% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1632      1.00%     83.57% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        24257     14.91%     98.49% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          559      0.34%     98.83% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1061      0.65%     99.48% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          841      0.52%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       162652                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              222296                       # Number of instructions committed
system.cpu3.commit.committedOps                222296                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                         89597                       # Number of memory references committed
system.cpu3.commit.loads                        61865                       # Number of loads committed
system.cpu3.commit.membars                       6925                       # Number of memory barriers committed
system.cpu3.commit.branches                     40618                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   152335                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.bw_lim_events                  841                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      392929                       # The number of ROB reads
system.cpu3.rob.rob_writes                     465356                       # The number of ROB writes
system.cpu3.timesIdled                            234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           2770                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       34882                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     183965                       # Number of Instructions Simulated
system.cpu3.committedOps                       183965                       # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total               183965                       # Number of Instructions Simulated
system.cpu3.cpi                              0.944484                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.944484                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.058779                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.058779                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  330929                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 155348                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                  92475                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu3.icache.replacements                   318                       # number of replacements
system.cpu3.icache.tagsinuse                80.006059                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   22493                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   426                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                 52.800469                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst    80.006059                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.156262                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.156262                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst        22493                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          22493                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        22493                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           22493                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        22493                       # number of overall hits
system.cpu3.icache.overall_hits::total          22493                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          466                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          466                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          466                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           466                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          466                       # number of overall misses
system.cpu3.icache.overall_misses::total          466                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6527000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      6527000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      6527000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      6527000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      6527000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      6527000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        22959                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        22959                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        22959                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        22959                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        22959                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        22959                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.020297                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.020297                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.020297                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14006.437768                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14006.437768                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14006.437768                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           40                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           40                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           40                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           40                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           40                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           40                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          426                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          426                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          426                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          426                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          426                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          426                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4833500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      4833500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4833500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      4833500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4833500                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      4833500                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.018555                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.018555                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.018555                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11346.244131                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11346.244131                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11346.244131                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     2                       # number of replacements
system.cpu3.dcache.tagsinuse                23.407477                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   33584                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs               1158.068966                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data    23.407477                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.045718                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.045718                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        38412                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          38412                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        27537                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         27537                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        65949                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           65949                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        65949                       # number of overall hits
system.cpu3.dcache.overall_hits::total          65949                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          448                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          448                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          125                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           56                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          573                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           573                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          573                       # number of overall misses
system.cpu3.dcache.overall_misses::total          573                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      9358000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      9358000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2911000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2911000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data      1350500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total      1350500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data     12269000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total     12269000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data     12269000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total     12269000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        38860                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        38860                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        27662                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        27662                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        66522                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        66522                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        66522                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        66522                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.011529                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004519                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.800000                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008614                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008614                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20888.392857                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data        23288                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 24116.071429                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 21411.867365                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 21411.867365                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu3.dcache.writebacks::total                1                       # number of writebacks
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          279                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          279                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           17                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           17                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          296                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          296                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          296                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          296                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          169                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          169                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          108                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           56                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          277                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          277                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          277                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          277                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2218000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2218000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1624500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1624500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data      1182500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total      1182500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3842500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      3842500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3842500                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      3842500                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004349                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003904                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.800000                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004164                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004164                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13124.260355                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15041.666667                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 21116.071429                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13871.841155                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13871.841155                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       428.231635                       # Cycle average of tags in use
system.l2c.total_refs                            1446                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           527                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.743833                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks            4.965624                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           287.776309                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data            59.398265                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst            10.494682                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data             0.774865                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst            57.571117                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data             5.683514                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst             0.828706                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data             0.738553                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000076                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.004391                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.000906                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.000160                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000012                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.000878                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.000087                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.000011                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.006534                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                228                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                412                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                 12                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                349                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                  7                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                424                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 12                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1449                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               9                       # number of Writeback hits
system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 228                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 412                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                  12                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 349                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   7                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 424                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  12                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1449                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                228                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                412                       # number of overall hits
system.l2c.overall_hits::cpu1.data                 12                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                349                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  7                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                424                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 12                       # number of overall hits
system.l2c.overall_hits::total                   1449                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              354                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               75                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               15                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               78                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  533                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            22                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            22                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            22                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                87                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               354                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               169                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                15                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                78                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   664                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              354                       # number of overall misses
system.l2c.overall_misses::cpu0.data              169                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               15                       # number of overall misses
system.l2c.overall_misses::cpu1.data               13                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               78                       # number of overall misses
system.l2c.overall_misses::cpu2.data               20                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                2                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  664                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     18441500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      3931500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst       745000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data        52500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst      4016500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data       365500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst        96000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        52500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       27701000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data        52500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data        52500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data        52500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       157500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      4940000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       627500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       683000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       627500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      6878000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     18441500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      8871500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst       745000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data       680000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      4016500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1048500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst        96000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       680000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        34579000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     18441500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      8871500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst       745000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data       680000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      4016500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1048500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst        96000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       680000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       34579000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            582                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             80                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            427                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             13                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            427                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             14                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            426                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             13                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               1982                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            9                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           24                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           22                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              90                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             582                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             174                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             427                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             427                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              27                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             426                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2113                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            582                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            174                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            427                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            427                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             27                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            426                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2113                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.608247                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.937500                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.035129                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.076923                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.182670                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.500000                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.004695                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.076923                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.875000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.608247                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.035129                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.520000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.182670                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.740741                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.004695                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.520000                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.608247                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.035129                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.520000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.182670                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.740741                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.004695                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.520000                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52094.632768                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data        52420                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49666.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data        52500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51493.589744                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 52214.285714                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst        48000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        52500                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2386.363636                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data  2386.363636                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data  2386.363636                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52553.191489                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52538.461538                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52094.632768                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52494.082840                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 49666.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 51493.589744                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data        52425                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst        48000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52094.632768                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52494.082840                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 49666.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 51493.589744                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data        52425                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst        48000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 8                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  8                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 8                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          353                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           75                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           14                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst           73                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             525                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           21                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           22                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           22                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           22                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           87                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          353                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          169                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           14                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           73                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              656                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          353                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          169                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           14                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           73                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             656                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     14091500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3019000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       561000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      2922000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data       280000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     20993500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       840000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       880000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       880000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       880000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      3480000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3792000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       481000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       524500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       481500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      5279000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     14091500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      6811000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst       561000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       521000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      2922000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       804500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst        40000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       521500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     26272500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     14091500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      6811000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst       561000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       521000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      2922000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       804500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst        40000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       521500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     26272500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.606529                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.032787                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.076923                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.170960                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.500000                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.002347                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.076923                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.875000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.606529                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.032787                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.520000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.170960                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.740741                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.002347                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.520000                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.606529                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.032787                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.520000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.170960                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.740741                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.002347                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.520000                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39919.263456                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40253.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40071.428571                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40027.397260                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40340.425532                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40083.333333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40346.153846                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40125                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39919.263456                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40301.775148                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40071.428571                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40076.923077                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40027.397260                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data        40225                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39919.263456                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40301.775148                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40071.428571                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40076.923077                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40027.397260                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data        40225                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------