path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000112                       # Number of seconds simulated
sim_ticks                                   111594500                       # Number of ticks simulated
final_tick                                  111594500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 200629                       # Simulator instruction rate (inst/s)
host_op_rate                                   200629                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               20568067                       # Simulator tick rate (ticks/s)
host_mem_usage                                 235024                       # Number of bytes of host memory used
host_seconds                                     5.43                       # Real time elapsed on the host
sim_insts                                     1088531                       # Number of instructions simulated
sim_ops                                       1088531                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst            23104                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             5632                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                42880                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        23104                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         5632                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           29120                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               361                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               169                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                88                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                 2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   670                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           207035293                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            96922339                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            50468437                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            11470099                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             1147010                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7455565                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             2294020                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7455565                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               384248328                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      207035293                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       50468437                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        1147010                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        2294020                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          260944760                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          207035293                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           96922339                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           50468437                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           11470099                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            1147010                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7455565                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            2294020                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7455565                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              384248328                       # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          223190                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                   87370                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted             85036                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect              1313                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups                84895                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                   82517                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                     514                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles             17415                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        518858                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      87370                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             83031                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       170328                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   4037                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 13330                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1404                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     6152                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  508                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            205057                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.530311                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.210840                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   34729     16.94%     16.94% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   84380     41.15%     58.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     595      0.29%     58.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     973      0.47%     58.85% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     523      0.26%     59.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   80298     39.16%     98.26% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     656      0.32%     98.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     373      0.18%     98.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2530      1.23%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              205057                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.391460                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.324737                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   18107                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                14779                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   169274                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  322                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2575                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                515764                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2575                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18814                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   1415                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         12654                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   168925                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  674                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                512400                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents                  252                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands             350257                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups              1022076                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups         1022076                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               336320                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   13937                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               921                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           951                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     4116                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              164196                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              82879                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            80125                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           79869                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    428350                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                958                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   425359                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              176                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          11411                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        10569                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           399                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       205057                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.074345                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.084750                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              33897     16.53%     16.53% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               5266      2.57%     19.10% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              81920     39.95%     59.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              81274     39.63%     98.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1599      0.78%     99.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                693      0.34%     99.80% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                302      0.15%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 90      0.04%     99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 16      0.01%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         205057                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     54     22.69%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     22.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    72     30.25%     52.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  112     47.06%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               179447     42.19%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.19% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              163633     38.47%     80.66% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              82279     19.34%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                425359                       # Type of FU issued
system.cpu0.iq.rate                          1.905816                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        238                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000560                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1056189                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           440777                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       423418                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                425597                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           79599                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2452                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           58                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1501                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           16                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2575                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   1020                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   41                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             509980                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              329                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               164196                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               82879                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               846                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    43                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            58                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           368                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1157                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1525                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               424238                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               163317                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1121                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        80672                       # number of nop insts executed
system.cpu0.iew.exec_refs                      245449                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   84313                       # Number of branches executed
system.cpu0.iew.exec_stores                     82132                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.900793                       # Inst execution rate
system.cpu0.iew.wb_sent                        423777                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       423418                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   250898                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   253433                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.897119                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.989997                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts        496825                       # The number of committed instructions
system.cpu0.commit.commitCommittedOps          496825                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts          13135                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1313                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       202499                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.453469                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.133222                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        34446     17.01%     17.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        84010     41.49%     58.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2422      1.20%     59.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          711      0.35%     60.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          562      0.28%     60.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        79343     39.18%     99.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          465      0.23%     99.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          235      0.12%     99.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          305      0.15%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       202499                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              496825                       # Number of instructions committed
system.cpu0.commit.committedOps                496825                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        243122                       # Number of memory references committed
system.cpu0.commit.loads                       161744                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     83266                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   334650                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events                  305                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      710993                       # The number of ROB reads
system.cpu0.rob.rob_writes                    1022511                       # The number of ROB writes
system.cpu0.timesIdled                            324                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          18133                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     416744                       # Number of Instructions Simulated
system.cpu0.committedOps                       416744                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total               416744                       # Number of Instructions Simulated
system.cpu0.cpi                              0.535557                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.535557                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.867216                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.867216                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  758967                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 341941                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 247293                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.replacements                   307                       # number of replacements
system.cpu0.icache.tagsinuse               248.147409                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    5393                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   598                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  9.018395                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   248.147409                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.484663                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.484663                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst         5393                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           5393                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         5393                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            5393                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         5393                       # number of overall hits
system.cpu0.icache.overall_hits::total           5393                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          759                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          759                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          759                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           759                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          759                       # number of overall misses
system.cpu0.icache.overall_misses::total          759                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     28913000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     28913000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     28913000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     28913000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     28913000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     28913000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         6152                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         6152                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         6152                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         6152                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         6152                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         6152                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.123375                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.123375                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.123375                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.123375                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.123375                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.123375                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38093.544137                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 38093.544137                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38093.544137                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 38093.544137                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38093.544137                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 38093.544137                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        15500                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs        15500                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          160                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          160                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          160                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          160                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          160                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          160                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          599                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          599                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          599                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          599                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     21855500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     21855500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     21855500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     21855500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     21855500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     21855500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.097367                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.097367                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.097367                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.097367                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.097367                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.097367                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36486.644407                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36486.644407                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36486.644407                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 36486.644407                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36486.644407                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 36486.644407                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     2                       # number of replacements
system.cpu0.dcache.tagsinuse               144.541703                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  163878                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   171                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                958.350877                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   144.541703                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.282308                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.282308                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        83150                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          83150                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        80790                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         80790                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       163940                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          163940                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       163940                       # number of overall hits
system.cpu0.dcache.overall_hits::total         163940                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          500                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          500                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          546                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          546                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1046                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1046                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1046                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1046                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     13780500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     13780500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     24368986                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     24368986                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       390500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       390500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     38149486                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     38149486                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     38149486                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     38149486                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        83650                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        83650                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        81336                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        81336                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       164986                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       164986                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       164986                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       164986                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005977                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.005977                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006713                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.006713                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006340                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006340                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006340                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006340                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data        27561                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total        27561                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44631.842491                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44631.842491                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18595.238095                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 18595.238095                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36471.783939                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 36471.783939                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36471.783939                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 36471.783939                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       194000                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          320                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          320                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          371                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          371                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          691                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          691                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          691                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          691                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          180                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          180                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          175                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          175                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          355                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          355                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          355                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          355                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4933000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4933000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6275500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6275500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       327500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       327500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11208500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     11208500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11208500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     11208500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002152                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002152                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002152                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002152                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002152                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002152                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002152                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002152                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27405.555556                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27405.555556                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data        35860                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total        35860                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15595.238095                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15595.238095                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31573.239437                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31573.239437                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31573.239437                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31573.239437                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          187839                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                   50940                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted             47890                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect              1510                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups                44289                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                   43310                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                     829                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles             31688                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        280910                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      50940                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             44139                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       100869                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   4392                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 39081                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         6575                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1045                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    22757                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  318                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            182067                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.542894                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.098462                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   81198     44.60%     44.60% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   51887     28.50%     73.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    7438      4.09%     77.18% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3280      1.80%     78.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     684      0.38%     79.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   31924     17.53%     96.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1209      0.66%     97.56% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     879      0.48%     98.04% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3568      1.96%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              182067                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.271190                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.495483                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   38413                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                34373                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    93637                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 6265                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2804                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                276803                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2804                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   39183                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  19194                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         14318                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    87661                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                12332                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                274424                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                    18                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                   52                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands             191179                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               520245                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          520245                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               175779                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   15400                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1221                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1348                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    15085                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               76182                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              35431                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            36807                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           30214                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    225638                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               7711                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   228522                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               80                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          12774                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        11561                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           762                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       182067                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.255153                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.306407                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              78861     43.31%     43.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              26436     14.52%     57.83% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              35607     19.56%     77.39% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              36159     19.86%     97.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3279      1.80%     99.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1252      0.69%     99.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                353      0.19%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 59      0.03%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         182067                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     20      6.62%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    72     23.84%     30.46% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  210     69.54%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               112122     49.06%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.06% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               81642     35.73%     84.79% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              34758     15.21%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                228522                       # Type of FU issued
system.cpu1.iq.rate                          1.216584                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        302                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001322                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            639493                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           246163                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       226488                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                228824                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           30049                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2733                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1566                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2804                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   1582                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   60                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             271136                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              377                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                76182                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               35431                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1144                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    55                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            40                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           494                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         1182                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1676                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               227186                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                75112                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1336                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        37787                       # number of nop insts executed
system.cpu1.iew.exec_refs                      109780                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   47145                       # Number of branches executed
system.cpu1.iew.exec_stores                     34668                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.209472                       # Inst execution rate
system.cpu1.iew.wb_sent                        226789                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       226488                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   126631                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   131515                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.205756                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.962864                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts        256347                       # The number of committed instructions
system.cpu1.commit.commitCommittedOps          256347                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts          14788                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           6949                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1510                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       172689                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.484443                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.966336                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        79222     45.88%     45.88% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        45065     26.10%     71.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         6173      3.57%     75.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         7849      4.55%     80.09% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1517      0.88%     80.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        30495     17.66%     98.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          550      0.32%     98.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7          998      0.58%     99.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          820      0.47%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       172689                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              256347                       # Number of instructions committed
system.cpu1.commit.committedOps                256347                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        107314                       # Number of memory references committed
system.cpu1.commit.loads                        73449                       # Number of loads committed
system.cpu1.commit.membars                       6235                       # Number of memory barriers committed
system.cpu1.commit.branches                     46061                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   175498                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events                  820                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      442417                       # The number of ROB reads
system.cpu1.rob.rob_writes                     545088                       # The number of ROB writes
system.cpu1.timesIdled                            232                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           5772                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       35349                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     213261                       # Number of Instructions Simulated
system.cpu1.committedOps                       213261                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total               213261                       # Number of Instructions Simulated
system.cpu1.cpi                              0.880794                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.880794                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.135339                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.135339                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  389025                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 181950                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 111436                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu1.icache.replacements                   321                       # number of replacements
system.cpu1.icache.tagsinuse                92.166456                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   22247                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   436                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 51.025229                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst    92.166456                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.180013                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.180013                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst        22247                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          22247                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        22247                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           22247                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        22247                       # number of overall hits
system.cpu1.icache.overall_hits::total          22247                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          510                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          510                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          510                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           510                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          510                       # number of overall misses
system.cpu1.icache.overall_misses::total          510                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     11347500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     11347500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     11347500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     11347500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     11347500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     11347500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        22757                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        22757                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        22757                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        22757                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        22757                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        22757                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.022411                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.022411                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.022411                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.022411                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.022411                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.022411                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst        22250                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total        22250                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst        22250                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total        22250                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst        22250                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total        22250                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs        33000                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs        33000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           74                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           74                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           74                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           74                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          436                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          436                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          436                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          436                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          436                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          436                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      8591500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      8591500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      8591500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      8591500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      8591500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      8591500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.019159                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.019159                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.019159                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.019159                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.019159                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.019159                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19705.275229                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19705.275229                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19705.275229                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 19705.275229                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19705.275229                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 19705.275229                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     0                       # number of replacements
system.cpu1.dcache.tagsinuse                27.650583                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   40148                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs               1384.413793                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data    27.650583                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.054005                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.054005                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        44622                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          44622                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        33643                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         33643                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           16                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        78265                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           78265                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        78265                       # number of overall hits
system.cpu1.dcache.overall_hits::total          78265                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          425                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          425                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          154                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          154                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           52                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          579                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           579                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          579                       # number of overall misses
system.cpu1.dcache.overall_misses::total          579                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      9294500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      9294500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3142500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3142500                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data      1219000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total      1219000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data     12437000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total     12437000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data     12437000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total     12437000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        45047                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        45047                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        33797                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        33797                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        78844                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        78844                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        78844                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        78844                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009435                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.009435                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004557                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.004557                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.764706                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.764706                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007344                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.007344                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007344                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.007344                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21869.411765                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 21869.411765                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20405.844156                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20405.844156                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23442.307692                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 23442.307692                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21480.138169                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 21480.138169                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21480.138169                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 21480.138169                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          266                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          266                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           47                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           47                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          313                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          313                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          313                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          313                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          159                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          159                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           52                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          266                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          266                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          266                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          266                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2405000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2405000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1693500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1693500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data      1063000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total      1063000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4098500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      4098500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4098500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      4098500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003530                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003530                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003166                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003166                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.764706                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003374                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.003374                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003374                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.003374                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15125.786164                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15125.786164                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15827.102804                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15827.102804                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20442.307692                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20442.307692                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15407.894737                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15407.894737                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15407.894737                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15407.894737                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          187552                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.BPredUnit.lookups                   49236                       # Number of BP lookups
system.cpu2.BPredUnit.condPredicted             46105                       # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect              1532                       # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups                42466                       # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits                   41429                       # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS                     825                       # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles             33274                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        268508                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      49236                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             42254                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                        98143                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   4464                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 42536                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         6571                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1082                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    24716                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  294                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            184466                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.455596                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.059567                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   86323     46.80%     46.80% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   50944     27.62%     74.41% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    8337      4.52%     78.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3301      1.79%     80.72% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     755      0.41%     81.13% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   29086     15.77%     96.90% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1170      0.63%     97.53% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     883      0.48%     98.01% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    3667      1.99%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              184466                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.262519                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.431646                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   41063                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                36807                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    89946                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 7224                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2855                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                264281                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2855                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   41843                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  22202                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         13743                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    82992                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                14260                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                261668                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                    19                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents                   57                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands             181221                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               490993                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          490993                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               165322                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   15899                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1233                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1350                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    17036                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               71489                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              32632                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            34884                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           27362                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    213682                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               8649                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   217360                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               54                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          13263                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        11908                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           765                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       184466                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.178320                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.292872                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              84063     45.57%     45.57% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              29277     15.87%     61.44% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              32764     17.76%     79.20% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              33297     18.05%     97.25% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3312      1.80%     99.05% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1277      0.69%     99.74% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                362      0.20%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         184466                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     20      6.64%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    71     23.59%     30.23% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  210     69.77%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               107542     49.48%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.48% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               77871     35.83%     85.30% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              31947     14.70%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                217360                       # Type of FU issued
system.cpu2.iq.rate                          1.158932                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        301                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001385                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            619541                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           235636                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       215243                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                217661                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           27206                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         2801                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           42                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1615                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2855                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   1726                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   52                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             258195                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              386                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                71489                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               32632                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1140                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    46                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            42                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           513                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         1199                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1712                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               215982                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                70400                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             1378                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        35864                       # number of nop insts executed
system.cpu2.iew.exec_refs                      102255                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   45260                       # Number of branches executed
system.cpu2.iew.exec_stores                     31855                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.151585                       # Inst execution rate
system.cpu2.iew.wb_sent                        215555                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       215243                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   119078                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   124002                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.147644                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.960291                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitCommittedInsts        242999                       # The number of committed instructions
system.cpu2.commit.commitCommittedOps          242999                       # The number of committed instructions
system.cpu2.commit.commitSquashedInsts          15188                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           7884                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1532                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       175041                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.388240                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.921152                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        85384     48.78%     48.78% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        43145     24.65%     73.43% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         6226      3.56%     76.98% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         8763      5.01%     81.99% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1523      0.87%     82.86% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        27601     15.77%     98.63% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          589      0.34%     98.97% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7          998      0.57%     99.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          812      0.46%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       175041                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              242999                       # Number of instructions committed
system.cpu2.commit.committedOps                242999                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                         99705                       # Number of memory references committed
system.cpu2.commit.loads                        68688                       # Number of loads committed
system.cpu2.commit.membars                       7170                       # Number of memory barriers committed
system.cpu2.commit.branches                     44148                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   165976                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events                  812                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      431829                       # The number of ROB reads
system.cpu2.rob.rob_writes                     519243                       # The number of ROB writes
system.cpu2.timesIdled                            226                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           3086                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       35636                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     200891                       # Number of Instructions Simulated
system.cpu2.committedOps                       200891                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total               200891                       # Number of Instructions Simulated
system.cpu2.cpi                              0.933601                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.933601                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.071122                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.071122                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  366578                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 171642                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 103931                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu2.icache.replacements                   324                       # number of replacements
system.cpu2.icache.tagsinuse                83.306019                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   24210                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   438                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                 55.273973                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst    83.306019                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.162707                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.162707                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst        24210                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          24210                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        24210                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           24210                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        24210                       # number of overall hits
system.cpu2.icache.overall_hits::total          24210                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          506                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          506                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          506                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           506                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          506                       # number of overall misses
system.cpu2.icache.overall_misses::total          506                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7060500                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      7060500                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      7060500                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      7060500                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      7060500                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      7060500                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        24716                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        24716                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        24716                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        24716                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        24716                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        24716                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.020473                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.020473                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.020473                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.020473                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.020473                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.020473                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13953.557312                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 13953.557312                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13953.557312                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 13953.557312                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13953.557312                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 13953.557312                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           68                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           68                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           68                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          438                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          438                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          438                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          438                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          438                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          438                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      5136000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      5136000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      5136000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      5136000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      5136000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      5136000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.017721                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.017721                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.017721                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.017721                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.017721                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.017721                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11726.027397                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11726.027397                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11726.027397                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 11726.027397                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11726.027397                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 11726.027397                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     0                       # number of replacements
system.cpu2.dcache.tagsinuse                24.973314                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   37203                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs               1328.678571                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data    24.973314                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.048776                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.048776                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        42731                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          42731                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        30798                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         30798                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           14                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        73529                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           73529                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        73529                       # number of overall hits
system.cpu2.dcache.overall_hits::total          73529                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          443                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          443                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          151                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          151                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           54                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          594                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           594                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          594                       # number of overall misses
system.cpu2.dcache.overall_misses::total          594                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      9862000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      9862000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2806000                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2806000                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data      1173500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total      1173500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data     12668000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total     12668000                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data     12668000                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total     12668000                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        43174                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        43174                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        30949                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        30949                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        74123                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        74123                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        74123                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        74123                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.010261                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.010261                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004879                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.004879                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.794118                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.794118                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.008014                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.008014                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.008014                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.008014                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22261.851016                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 22261.851016                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18582.781457                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 18582.781457                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21731.481481                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 21731.481481                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 21326.599327                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 21326.599327                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 21326.599327                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 21326.599327                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          279                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          279                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           47                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           47                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          326                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          326                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          326                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          326                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          164                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          164                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          104                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           54                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          268                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          268                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2336000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2336000                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1419000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1419000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data      1011500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total      1011500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3755000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      3755000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3755000                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      3755000                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003799                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003799                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003360                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003360                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.794118                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.794118                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003616                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.003616                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003616                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.003616                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14243.902439                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14243.902439                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13644.230769                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13644.230769                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18731.481481                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18731.481481                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14011.194030                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14011.194030                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14011.194030                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14011.194030                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          187286                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.BPredUnit.lookups                   59110                       # Number of BP lookups
system.cpu3.BPredUnit.condPredicted             55955                       # Number of conditional branches predicted
system.cpu3.BPredUnit.condIncorrect              1573                       # Number of conditional branches incorrect
system.cpu3.BPredUnit.BTBLookups                52456                       # Number of BTB lookups
system.cpu3.BPredUnit.BTBHits                   51388                       # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.usedRAS                     831                       # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles             27555                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        332776                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      59110                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             52219                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       115081                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   4575                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 31846                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         6567                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1060                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    19062                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  312                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            185045                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.798352                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.183167                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   69964     37.81%     37.81% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   58012     31.35%     69.16% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    5498      2.97%     72.13% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3553      1.92%     74.05% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     717      0.39%     74.44% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   41629     22.50%     96.93% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1211      0.65%     97.59% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     858      0.46%     98.05% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3603      1.95%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              185045                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.315614                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.776833                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   32638                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                28853                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                   109537                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 4519                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2931                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                328437                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2931                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   33475                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  14026                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         13970                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                   105232                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                 8844                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                325744                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                    27                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents                   59                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands             228226                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               629601                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          629601                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               212325                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   15901                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1261                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1383                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    11670                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               93735                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              45116                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            44692                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           39822                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    270564                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               6038                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   271349                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued              117                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          13410                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        12382                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           838                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       185045                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.466395                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.313251                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              67828     36.65%     36.65% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              21223     11.47%     48.12% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              45218     24.44%     72.56% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              45760     24.73%     97.29% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3300      1.78%     99.07% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1261      0.68%     99.75% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                341      0.18%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         185045                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     21      6.80%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      6.80% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    78     25.24%     32.04% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  210     67.96%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               129621     47.77%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.77% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               97351     35.88%     83.65% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              44377     16.35%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                271349                       # Type of FU issued
system.cpu3.iq.rate                          1.448848                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        309                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001139                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            728169                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           290051                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       269261                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                271658                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           39639                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2895                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1672                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2931                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   1690                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   60                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             322365                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              383                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                93735                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               45116                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1181                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    62                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            39                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           528                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         1218                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1746                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               269989                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                92559                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1360                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        45763                       # number of nop insts executed
system.cpu3.iew.exec_refs                      136843                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   55022                       # Number of branches executed
system.cpu3.iew.exec_stores                     44284                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.441587                       # Inst execution rate
system.cpu3.iew.wb_sent                        269584                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       269261                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   153664                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   158539                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.437700                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.969250                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitCommittedInsts        306791                       # The number of committed instructions
system.cpu3.commit.commitCommittedOps          306791                       # The number of committed instructions
system.cpu3.commit.commitSquashedInsts          15574                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           5200                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1573                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       175548                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.747619                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     2.056560                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        66312     37.77%     37.77% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        53003     30.19%     67.97% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6220      3.54%     71.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         6065      3.45%     74.97% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1526      0.87%     75.83% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        40098     22.84%     98.68% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          522      0.30%     98.97% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7          989      0.56%     99.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          813      0.46%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       175548                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              306791                       # Number of instructions committed
system.cpu3.commit.committedOps                306791                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                        134284                       # Number of memory references committed
system.cpu3.commit.loads                        90840                       # Number of loads committed
system.cpu3.commit.membars                       4481                       # Number of memory barriers committed
system.cpu3.commit.branches                     53890                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   210289                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.bw_lim_events                  813                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      496513                       # The number of ROB reads
system.cpu3.rob.rob_writes                     647676                       # The number of ROB writes
system.cpu3.timesIdled                            218                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           2241                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       35902                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     257635                       # Number of Instructions Simulated
system.cpu3.committedOps                       257635                       # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total               257635                       # Number of Instructions Simulated
system.cpu3.cpi                              0.726943                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.726943                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.375623                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.375623                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  470214                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 218594                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 138505                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
system.cpu3.icache.replacements                   322                       # number of replacements
system.cpu3.icache.tagsinuse                87.207959                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   18566                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   436                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                 42.582569                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst    87.207959                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.170328                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.170328                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst        18566                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          18566                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        18566                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           18566                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        18566                       # number of overall hits
system.cpu3.icache.overall_hits::total          18566                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          496                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          496                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          496                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           496                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          496                       # number of overall misses
system.cpu3.icache.overall_misses::total          496                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6966500                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      6966500                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      6966500                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      6966500                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      6966500                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      6966500                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        19062                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        19062                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        19062                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        19062                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        19062                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        19062                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.026020                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.026020                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.026020                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.026020                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.026020                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.026020                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14045.362903                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 14045.362903                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14045.362903                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 14045.362903                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14045.362903                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 14045.362903                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           60                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           60                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           60                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           60                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           60                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           60                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          436                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          436                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          436                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          436                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          436                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          436                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5084500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      5084500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5084500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      5084500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5084500                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      5084500                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.022873                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.022873                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.022873                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.022873                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.022873                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.022873                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11661.697248                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11661.697248                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11661.697248                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 11661.697248                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11661.697248                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 11661.697248                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     0                       # number of replacements
system.cpu3.dcache.tagsinuse                26.205436                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   49620                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs               1772.142857                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data    26.205436                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.051182                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.051182                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        52477                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          52477                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        43221                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         43221                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        95698                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           95698                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        95698                       # number of overall hits
system.cpu3.dcache.overall_hits::total          95698                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          424                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          424                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          150                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          150                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           61                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           61                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          574                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           574                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          574                       # number of overall misses
system.cpu3.dcache.overall_misses::total          574                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      8617000                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      8617000                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2850000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2850000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data      1161500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total      1161500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data     11467000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total     11467000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data     11467000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total     11467000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        52901                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        52901                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        43371                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        43371                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           73                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           73                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        96272                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        96272                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        96272                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        96272                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.008015                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.008015                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003459                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.003459                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.835616                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.835616                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005962                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.005962                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005962                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.005962                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20323.113208                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 20323.113208                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data        19000                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total        19000                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 19040.983607                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 19040.983607                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19977.351916                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 19977.351916                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19977.351916                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 19977.351916                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          264                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          264                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           46                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           46                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          310                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          310                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          310                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          310                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          160                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          160                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          104                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           61                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           61                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          264                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          264                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          264                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          264                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1797000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1797000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1508500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1508500                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       978500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       978500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3305500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      3305500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3305500                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      3305500                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003025                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003025                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002398                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002398                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.835616                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.835616                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002742                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.002742                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002742                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.002742                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 11231.250000                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 11231.250000                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14504.807692                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14504.807692                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 16040.983607                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 16040.983607                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12520.833333                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12520.833333                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12520.833333                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12520.833333                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       436.530480                       # Cycle average of tags in use
system.l2c.total_refs                            1479                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           536                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.759328                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks            0.840422                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           294.533073                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data            59.606311                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst            70.480803                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data             5.728880                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst             1.673039                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data             0.734409                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst             2.156423                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data             0.777117                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.004494                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.000910                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.001075                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000087                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.000026                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.000011                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.000033                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.000012                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.006661                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                238                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                347                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                431                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                431                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1479                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 238                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 347                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 431                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 431                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1479                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                238                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                347                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                431                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                431                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   1479                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              361                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               75                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               89                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  546                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            23                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            19                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                81                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               361                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               169                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                89                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                 7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   677                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              361                       # number of overall misses
system.l2c.overall_misses::cpu0.data              169                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               89                       # number of overall misses
system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
system.l2c.overall_misses::cpu2.inst                7                       # number of overall misses
system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                5                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  677                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     18817000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      3930500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      4612000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data       366000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst       304000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data        52500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       254000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        52500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       28388500                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      4938500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       681500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       629500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       628000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      6877500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     18817000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      8869000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      4612000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1047500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst       304000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data       682000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       254000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       680500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        35266000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     18817000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      8869000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      4612000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1047500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst       304000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data       682000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       254000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       680500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       35266000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            599                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             80                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            436                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            438                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            436                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               2025                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           26                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           19                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              84                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             599                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             174                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             436                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             438                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             436                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2156                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            599                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            174                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            436                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            438                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            436                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2156                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.602671                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.937500                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.204128                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.583333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.015982                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.011468                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.269630                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.884615                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.964286                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.602671                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.204128                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.015982                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.011468                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.314007                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.602671                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.204128                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.015982                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.011468                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.314007                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52124.653740                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52406.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51820.224719                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52285.714286                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 43428.571429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        52500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst        50800                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        52500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 51993.589744                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52537.234043                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52423.076923                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52458.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52333.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52124.653740                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 51820.224719                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        52375                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 43428.571429                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 52461.538462                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst        50800                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 52346.153846                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52091.580502                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52124.653740                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 51820.224719                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        52375                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 43428.571429                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 52461.538462                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst        50800                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 52346.153846                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52091.580502                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 7                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  7                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 7                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          361                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           75                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           88                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             539                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           23                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           19                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           19                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           81                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          361                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          169                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           88                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              670                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          361                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          169                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           88                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             670                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     14412000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3017000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      3521000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data       280000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst        80000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       160000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     21550000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       920000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       800000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       760000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       760500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      3240500                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3791500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       522500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       483500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       481500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      5279000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     14412000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      6808500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      3521000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       802500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst        80000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       523500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       160000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       521500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     26829000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     14412000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      6808500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      3521000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       802500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst        80000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       523500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       160000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       521500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     26829000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.602671                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.201835                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.004566                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.009174                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.266173                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.884615                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.964286                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.602671                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.201835                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.004566                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.009174                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.310761                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.602671                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.201835                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.004566                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.009174                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.310761                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39922.437673                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40226.666667                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40011.363636                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 39981.447124                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40026.315789                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40006.172840                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40335.106383                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40192.307692                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40291.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40125                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40297.709924                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39922.437673                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40286.982249                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40011.363636                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data        40125                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40269.230769                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40043.283582                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39922.437673                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40286.982249                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40011.363636                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data        40125                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40269.230769                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40043.283582                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------