1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000114 # Number of seconds simulated
sim_ticks 113910500 # Number of ticks simulated
final_tick 113910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 141669 # Simulator instruction rate (inst/s)
host_op_rate 141669 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 14682125 # Simulator tick rate (ticks/s)
host_mem_usage 244464 # Number of bytes of host memory used
host_seconds 7.76 # Real time elapsed on the host
sim_insts 1099129 # Number of instructions simulated
sim_ops 1099129 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 42944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 29248 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 671 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 203387747 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 94389894 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 47194947 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 11236892 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 2809223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 7303980 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 3371068 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 7303980 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 376997731 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 203387747 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 47194947 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 2809223 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 3371068 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 256762985 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 203387747 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 94389894 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 47194947 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 11236892 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 2809223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 7303980 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 3371068 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 7303980 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 376997731 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 227822 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.BPredUnit.lookups 88179 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 85929 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 1290 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 85894 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 83486 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 17727 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 523680 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 88179 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 84003 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 172095 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 4009 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 15408 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 1281 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 6036 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 519 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 209087 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 2.504603 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.209881 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 36992 17.69% 17.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 85294 40.79% 58.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 585 0.28% 58.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 1000 0.48% 59.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 484 0.23% 59.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 81297 38.88% 98.36% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 665 0.32% 98.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 355 0.17% 98.84% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 2415 1.16% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 209087 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.387052 # Number of branch fetches per cycle
system.cpu0.fetch.rate 2.298637 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 18268 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 16880 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 171017 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 351 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2571 # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts 520658 # Number of instructions handled by decode
system.cpu0.rename.SquashCycles 2571 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 18993 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 2288 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 13870 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 170679 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 686 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 517484 # Number of instructions processed by rename
system.cpu0.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 353459 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 1032335 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 1032335 # Number of integer rename lookups
system.cpu0.rename.CommittedMaps 339779 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 13680 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 4009 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 165974 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 83785 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 81138 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 80830 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 432592 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 429324 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 270 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 11361 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 11323 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 209087 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 2.053327 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.097112 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 36280 17.35% 17.35% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 5325 2.55% 19.90% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 82668 39.54% 59.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 82134 39.28% 98.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1638 0.78% 99.50% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 661 0.32% 99.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 275 0.13% 99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 12 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 209087 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 52 18.77% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 113 40.79% 59.57% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 112 40.43% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 180924 42.14% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.14% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 165296 38.50% 80.64% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 83104 19.36% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 429324 # Type of FU issued
system.cpu0.iq.rate 1.884471 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 277 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.000645 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1068282 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 444960 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 427393 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 429601 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 80458 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1539 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 2571 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1789 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 515149 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 291 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 165974 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 83785 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 95 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 1496 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 428216 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 164977 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 81606 # number of nop insts executed
system.cpu0.iew.exec_refs 247935 # number of memory reference insts executed
system.cpu0.iew.exec_branches 85106 # Number of branches executed
system.cpu0.iew.exec_stores 82958 # Number of stores executed
system.cpu0.iew.exec_rate 1.879608 # Inst execution rate
system.cpu0.iew.wb_sent 427739 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 427393 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 253334 # num instructions producing a value
system.cpu0.iew.wb_consumers 255736 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 1.875995 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.990608 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts 502020 # The number of committed instructions
system.cpu0.commit.commitCommittedOps 502020 # The number of committed instructions
system.cpu0.commit.commitSquashedInsts 13085 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1290 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 206533 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 2.430701 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 2.136521 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 36757 17.80% 17.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 84830 41.07% 58.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2489 1.21% 60.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 701 0.34% 60.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 579 0.28% 60.70% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 80093 38.78% 99.48% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 561 0.27% 99.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 222 0.11% 99.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 206533 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 502020 # Number of instructions committed
system.cpu0.commit.committedOps 502020 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 245725 # Number of memory references committed
system.cpu0.commit.loads 163479 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
system.cpu0.commit.branches 84133 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 338110 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 720176 # The number of ROB reads
system.cpu0.rob.rob_writes 1032801 # The number of ROB writes
system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 18735 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 421071 # Number of Instructions Simulated
system.cpu0.committedOps 421071 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 421071 # Number of Instructions Simulated
system.cpu0.cpi 0.541054 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 0.541054 # CPI: Total CPI of All Threads
system.cpu0.ipc 1.848246 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 1.848246 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 766308 # number of integer regfile reads
system.cpu0.int_regfile_writes 345106 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
system.cpu0.misc_regfile_reads 249733 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
system.cpu0.icache.replacements 302 # number of replacements
system.cpu0.icache.tagsinuse 247.706871 # Cycle average of tags in use
system.cpu0.icache.total_refs 5276 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 594 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 8.882155 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 247.706871 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.483802 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.483802 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5276 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 5276 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5276 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 5276 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5276 # number of overall hits
system.cpu0.icache.overall_hits::total 5276 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 760 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 760 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 760 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 760 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 760 # number of overall misses
system.cpu0.icache.overall_misses::total 760 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29374500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 29374500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 29374500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 29374500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 29374500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 29374500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6036 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 6036 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6036 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 6036 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 6036 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 6036 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125911 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.125911 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125911 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.125911 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125911 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.125911 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38650.657895 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 38650.657895 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 38650.657895 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38650.657895 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 38650.657895 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 13500 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 13500 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 595 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 595 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 595 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 595 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 595 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 595 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22317000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 22317000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22317000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 22317000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22317000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 22317000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098575 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.098575 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098575 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.098575 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37507.563025 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37507.563025 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 37507.563025 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 2 # number of replacements
system.cpu0.dcache.tagsinuse 144.389455 # Cycle average of tags in use
system.cpu0.dcache.total_refs 165484 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 973.435294 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 144.389455 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.282011 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.282011 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 83924 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 83924 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 81641 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 81641 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 17 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 17 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 165565 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 165565 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 165565 # number of overall hits
system.cpu0.dcache.overall_hits::total 165565 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 532 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 532 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 563 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 563 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 25 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 25 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1095 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1095 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1095 # number of overall misses
system.cpu0.dcache.overall_misses::total 1095 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16935000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 16935000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28694494 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 28694494 # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 516500 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 516500 # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 45629494 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 45629494 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 45629494 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 45629494 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 84456 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 84456 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 82204 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 82204 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 166660 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 166660 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 166660 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 166660 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006299 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.006299 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006849 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.006849 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.595238 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.595238 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006570 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.006570 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006570 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.006570 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31832.706767 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 31832.706767 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50967.129663 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50967.129663 # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20660 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 20660 # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 41670.770776 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41670.770776 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 41670.770776 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 112000 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6222.222222 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 351 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 394 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 394 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 169 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 169 # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 25 # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total 25 # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 350 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 350 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5844010 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5844010 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6652500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6652500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 438500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 438500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12496510 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 12496510 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12496510 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 12496510 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002143 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002056 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002056 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.595238 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.595238 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002100 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002100 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32287.348066 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32287.348066 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39363.905325 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39363.905325 # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17540 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17540 # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 191317 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.BPredUnit.lookups 53059 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 50011 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 46382 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 45427 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS 803 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 31318 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 294530 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 53059 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 46230 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 104588 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 4407 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 38684 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles 6733 # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines 21833 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 185209 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.590257 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.119058 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 80621 43.53% 43.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 53529 28.90% 72.43% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 6903 3.73% 76.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 3276 1.77% 77.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 732 0.40% 78.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 34514 18.64% 96.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1160 0.63% 97.58% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 883 0.48% 98.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 3591 1.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 185209 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.277336 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.539487 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 37437 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 34588 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 97784 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 5856 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 2811 # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts 290465 # Number of instructions handled by decode
system.cpu1.rename.SquashCycles 2811 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 38251 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 18737 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 14962 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 92242 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 11473 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 288015 # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 201252 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 549512 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 549512 # Number of integer rename lookups
system.cpu1.rename.CommittedMaps 185544 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 15708 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1231 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 14237 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 80834 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 37999 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 38862 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 32764 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 237666 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 7151 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 239902 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 12973 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 11962 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 719 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 185209 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 1.295304 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.311031 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 78322 42.29% 42.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 24974 13.48% 55.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 38132 20.59% 76.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 38761 20.93% 97.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 3339 1.80% 99.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1231 0.66% 99.76% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 185209 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 21 6.44% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 95 29.14% 35.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 210 64.42% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 116849 48.71% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 85748 35.74% 84.45% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 37305 15.55% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 239902 # Type of FU issued
system.cpu1.iq.rate 1.253950 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 326 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.001359 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 665467 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 257831 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 237819 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 240228 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 32613 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 2758 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1567 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 2811 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 2340 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 107 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 284663 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 80834 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 37999 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 1185 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 1694 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 238552 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 79712 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 39846 # number of nop insts executed
system.cpu1.iew.exec_refs 116931 # number of memory reference insts executed
system.cpu1.iew.exec_branches 49232 # Number of branches executed
system.cpu1.iew.exec_stores 37219 # Number of stores executed
system.cpu1.iew.exec_rate 1.246894 # Inst execution rate
system.cpu1.iew.wb_sent 238105 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 237819 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 133762 # num instructions producing a value
system.cpu1.iew.wb_consumers 138617 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 1.243063 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.964975 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts 269706 # The number of committed instructions
system.cpu1.commit.commitCommittedOps 269706 # The number of committed instructions
system.cpu1.commit.commitSquashedInsts 14936 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 6432 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 1521 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 175666 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 1.535334 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.989786 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 78046 44.43% 44.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 47129 26.83% 71.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6230 3.55% 74.80% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 7351 4.18% 78.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1552 0.88% 79.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 32915 18.74% 98.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 634 0.36% 98.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 175666 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 269706 # Number of instructions committed
system.cpu1.commit.committedOps 269706 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 114508 # Number of memory references committed
system.cpu1.commit.loads 78076 # Number of loads committed
system.cpu1.commit.membars 5720 # Number of memory barriers committed
system.cpu1.commit.branches 48115 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 184747 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 458907 # The number of ROB reads
system.cpu1.rob.rob_writes 572109 # The number of ROB writes
system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 6108 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 36503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 225079 # Number of Instructions Simulated
system.cpu1.committedOps 225079 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 225079 # Number of Instructions Simulated
system.cpu1.cpi 0.849999 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 0.849999 # CPI: Total CPI of All Threads
system.cpu1.ipc 1.176472 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 1.176472 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 410678 # number of integer regfile reads
system.cpu1.int_regfile_writes 191757 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
system.cpu1.misc_regfile_reads 118640 # number of misc regfile reads
system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
system.cpu1.icache.replacements 322 # number of replacements
system.cpu1.icache.tagsinuse 90.918932 # Cycle average of tags in use
system.cpu1.icache.total_refs 21316 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 48.889908 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 90.918932 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.177576 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.177576 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 21316 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 21316 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 21316 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 21316 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 21316 # number of overall hits
system.cpu1.icache.overall_hits::total 21316 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses
system.cpu1.icache.overall_misses::total 517 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11871000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 11871000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 11871000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 11871000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 11871000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 11871000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 21833 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 21833 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 21833 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 21833 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 21833 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 21833 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023680 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.023680 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023680 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.023680 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023680 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.023680 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22961.315280 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 22961.315280 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 22961.315280 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 22961.315280 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 32000 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 8857500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 8857500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019970 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.019970 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.019970 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20315.366972 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 0 # number of replacements
system.cpu1.dcache.tagsinuse 27.526466 # Cycle average of tags in use
system.cpu1.dcache.total_refs 42609 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 1521.750000 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 27.526466 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.053763 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.053763 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 46637 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 46637 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 36226 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 36226 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 82863 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 82863 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 82863 # number of overall hits
system.cpu1.dcache.overall_hits::total 82863 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 446 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 446 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 586 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 586 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 586 # number of overall misses
system.cpu1.dcache.overall_misses::total 586 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 12735500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 12735500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3574500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 3574500 # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1329500 # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total 1329500 # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 16310000 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 16310000 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 16310000 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 16310000 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 47083 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 47083 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 36366 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 36366 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 83449 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 83449 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 83449 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 83449 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009473 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003850 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.787879 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007022 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.007022 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007022 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.007022 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 28554.932735 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 28554.932735 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25532.142857 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25532.142857 # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 25567.307692 # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 25567.307692 # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27832.764505 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 27832.764505 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27832.764505 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 27832.764505 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3164503 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3164503 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1890000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1890000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1168500 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1168500 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5054503 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 5054503 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5054503 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5054503 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003398 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003398 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002915 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002915 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.787879 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.787879 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.003188 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.003188 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19778.143750 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19778.143750 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17830.188679 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17830.188679 # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 22471.153846 # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 22471.153846 # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.numCycles 191010 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.BPredUnit.lookups 57179 # Number of BP lookups
system.cpu2.BPredUnit.condPredicted 53988 # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect 1553 # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups 50487 # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits 49441 # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS 815 # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles 29527 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 320031 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 57179 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 50256 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 111848 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 4474 # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles 35937 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles 6751 # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines 20539 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 187993 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.702356 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.156955 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 76145 40.50% 40.50% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 56782 30.20% 70.71% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 6165 3.28% 73.99% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 3347 1.78% 75.77% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 731 0.39% 76.16% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 39077 20.79% 96.94% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 1243 0.66% 97.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 913 0.49% 98.09% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 3590 1.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 187993 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.299351 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.675467 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 35252 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 32290 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 105597 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 5255 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 2848 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 315625 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 2848 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 36036 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 16472 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 14955 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 100655 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 10276 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 313299 # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 219155 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 602465 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 602465 # Number of integer rename lookups
system.cpu2.rename.CommittedMaps 203359 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 15796 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 1243 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 1365 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 12944 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 89370 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 42679 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 42734 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 37374 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 259618 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 6531 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 261379 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 13068 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 11786 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 697 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 187993 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.390366 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.314588 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 73641 39.17% 39.17% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 23139 12.31% 51.48% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 42800 22.77% 74.25% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 43353 23.06% 97.31% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 3352 1.78% 99.09% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 1252 0.67% 99.76% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 187993 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 21 6.71% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 82 26.20% 32.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 210 67.09% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 125670 48.08% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.08% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 93767 35.87% 83.95% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 41942 16.05% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 261379 # Type of FU issued
system.cpu2.iq.rate 1.368405 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 313 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.001197 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 711198 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 279252 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 259224 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 261692 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 37218 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 2690 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 1641 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 2848 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 1926 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 309970 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 89370 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 42679 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 72 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 514 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 1208 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 1722 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 259980 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 88335 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 1399 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 43821 # number of nop insts executed
system.cpu2.iew.exec_refs 130189 # number of memory reference insts executed
system.cpu2.iew.exec_branches 53302 # Number of branches executed
system.cpu2.iew.exec_stores 41854 # Number of stores executed
system.cpu2.iew.exec_rate 1.361081 # Inst execution rate
system.cpu2.iew.wb_sent 259524 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 259224 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 147020 # num instructions producing a value
system.cpu2.iew.wb_consumers 151915 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.357123 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.967778 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitCommittedInsts 294930 # The number of committed instructions
system.cpu2.commit.commitCommittedOps 294930 # The number of committed instructions
system.cpu2.commit.commitSquashedInsts 15032 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 5834 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 1553 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 178395 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.653241 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.030877 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 72759 40.79% 40.79% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 51159 28.68% 69.46% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 6241 3.50% 72.96% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 6697 3.75% 76.72% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 1549 0.87% 77.58% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 37557 21.05% 98.64% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 629 0.35% 98.99% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 989 0.55% 99.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 178395 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 294930 # Number of instructions committed
system.cpu2.commit.committedOps 294930 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 127718 # Number of memory references committed
system.cpu2.commit.loads 86680 # Number of loads committed
system.cpu2.commit.membars 5119 # Number of memory barriers committed
system.cpu2.commit.branches 52122 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 201960 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 486955 # The number of ROB reads
system.cpu2.rob.rob_writes 622786 # The number of ROB writes
system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 3017 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 36810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 246900 # Number of Instructions Simulated
system.cpu2.committedOps 246900 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 246900 # Number of Instructions Simulated
system.cpu2.cpi 0.773633 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 0.773633 # CPI: Total CPI of All Threads
system.cpu2.ipc 1.292602 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 1.292602 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 450556 # number of integer regfile reads
system.cpu2.int_regfile_writes 209704 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
system.cpu2.misc_regfile_reads 131893 # number of misc regfile reads
system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
system.cpu2.icache.replacements 322 # number of replacements
system.cpu2.icache.tagsinuse 84.177245 # Cycle average of tags in use
system.cpu2.icache.total_refs 20042 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 45.757991 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst 84.177245 # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst 0.164409 # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total 0.164409 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 20042 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 20042 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 20042 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 20042 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 20042 # number of overall hits
system.cpu2.icache.overall_hits::total 20042 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 497 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 497 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 497 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 497 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 497 # number of overall misses
system.cpu2.icache.overall_misses::total 497 # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7614500 # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total 7614500 # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst 7614500 # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total 7614500 # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst 7614500 # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total 7614500 # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst 20539 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 20539 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 20539 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 20539 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 20539 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 20539 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024198 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.024198 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024198 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.024198 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024198 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.024198 # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15320.925553 # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 15320.925553 # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 15320.925553 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 15320.925553 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 59 # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst 59 # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst 59 # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total 59 # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5672000 # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total 5672000 # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5672000 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total 5672000 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5672000 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total 5672000 # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021325 # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total 0.021325 # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021325 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total 0.021325 # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12949.771689 # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12949.771689 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12949.771689 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 0 # number of replacements
system.cpu2.dcache.tagsinuse 24.875323 # Cycle average of tags in use
system.cpu2.dcache.total_refs 47216 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 1686.285714 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data 24.875323 # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data 0.048585 # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total 0.048585 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 50709 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 50709 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 40830 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 40830 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 91539 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 91539 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 91539 # number of overall hits
system.cpu2.dcache.overall_hits::total 91539 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 389 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 389 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 528 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 528 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 528 # number of overall misses
system.cpu2.dcache.overall_misses::total 528 # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10172000 # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total 10172000 # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3390500 # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total 3390500 # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1234500 # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total 1234500 # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data 13562500 # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total 13562500 # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data 13562500 # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total 13562500 # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data 51098 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 51098 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 40969 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 40969 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 92067 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 92067 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 92067 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 92067 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007613 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.007613 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003393 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.003393 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005735 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.005735 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005735 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.005735 # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 26149.100257 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 26149.100257 # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24392.086331 # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 24392.086331 # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21657.894737 # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 21657.894737 # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25686.553030 # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 25686.553030 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25686.553030 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 25686.553030 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 234 # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total 234 # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data 269 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data 269 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total 269 # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data 259 # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 259 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2539505 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2539505 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1736500 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1736500 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1057000 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1057000 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4276005 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total 4276005 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4276005 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total 4276005 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003033 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003033 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002539 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002539 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total 0.002813 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002813 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.002813 # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16383.903226 # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16383.903226 # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16697.115385 # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16697.115385 # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18543.859649 # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18543.859649 # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.numCycles 190730 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.BPredUnit.lookups 50135 # Number of BP lookups
system.cpu3.BPredUnit.condPredicted 46886 # Number of conditional branches predicted
system.cpu3.BPredUnit.condIncorrect 1563 # Number of conditional branches incorrect
system.cpu3.BPredUnit.BTBLookups 43380 # Number of BTB lookups
system.cpu3.BPredUnit.BTBHits 42368 # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.BPredUnit.usedRAS 844 # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles 33373 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 273510 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 50135 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 43212 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 99693 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 4441 # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles 43703 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles 6715 # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines 24485 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples 187356 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.459841 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.059659 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0 87663 46.79% 46.79% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 51707 27.60% 74.39% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 8154 4.35% 78.74% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 3276 1.75% 80.49% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 745 0.40% 80.89% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 30183 16.11% 97.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 1182 0.63% 97.63% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 888 0.47% 98.10% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 3558 1.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total 187356 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.262858 # Number of branch fetches per cycle
system.cpu3.fetch.rate 1.434017 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 40875 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 38262 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 91696 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 6999 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 2809 # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts 269218 # Number of instructions handled by decode
system.cpu3.rename.SquashCycles 2809 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 41677 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 21676 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 15745 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 84975 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 13759 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 266737 # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands 184789 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 501822 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 501822 # Number of integer rename lookups
system.cpu3.rename.CommittedMaps 169578 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 15211 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 1292 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 1426 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 16516 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 73298 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 33720 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 35666 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 28418 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 218299 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 222114 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 12726 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 11163 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 773 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 187356 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 1.185518 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.293170 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0 85320 45.54% 45.54% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 28690 15.31% 60.85% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 33902 18.09% 78.95% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 34456 18.39% 97.34% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 3309 1.77% 99.10% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 1236 0.66% 99.76% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 327 0.17% 99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total 187356 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu 22 7.17% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 75 24.43% 31.60% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 210 68.40% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 109540 49.32% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 79567 35.82% 85.14% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 33007 14.86% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total 222114 # Type of FU issued
system.cpu3.iq.rate 1.164547 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 307 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 632004 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 239536 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 220090 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 222421 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 28294 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads 2578 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 1587 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles 2809 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 1854 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 263586 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 73298 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 33720 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 1219 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 53 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 1726 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 220807 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 72290 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 1307 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
system.cpu3.iew.exec_nop 36810 # number of nop insts executed
system.cpu3.iew.exec_refs 105220 # number of memory reference insts executed
system.cpu3.iew.exec_branches 46242 # Number of branches executed
system.cpu3.iew.exec_stores 32930 # Number of stores executed
system.cpu3.iew.exec_rate 1.157694 # Inst execution rate
system.cpu3.iew.wb_sent 220376 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 220090 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 122048 # num instructions producing a value
system.cpu3.iew.wb_consumers 126919 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate 1.153935 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.961621 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitCommittedInsts 248929 # The number of committed instructions
system.cpu3.commit.commitCommittedOps 248929 # The number of committed instructions
system.cpu3.commit.commitSquashedInsts 14631 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 7704 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 1563 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 177833 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 1.399791 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 1.928963 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0 86250 48.50% 48.50% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 44177 24.84% 73.34% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 6214 3.49% 76.84% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 8561 4.81% 81.65% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 1535 0.86% 82.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 28697 16.14% 98.65% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 590 0.33% 98.98% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 996 0.56% 99.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total 177833 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 248929 # Number of instructions committed
system.cpu3.commit.committedOps 248929 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.refs 102853 # Number of memory references committed
system.cpu3.commit.loads 70720 # Number of loads committed
system.cpu3.commit.membars 6986 # Number of memory barriers committed
system.cpu3.commit.branches 45078 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 170050 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads 439993 # The number of ROB reads
system.cpu3.rob.rob_writes 529937 # The number of ROB writes
system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 3374 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 37090 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 206079 # Number of Instructions Simulated
system.cpu3.committedOps 206079 # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total 206079 # Number of Instructions Simulated
system.cpu3.cpi 0.925519 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 0.925519 # CPI: Total CPI of All Threads
system.cpu3.ipc 1.080475 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 1.080475 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 375615 # number of integer regfile reads
system.cpu3.int_regfile_writes 175714 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
system.cpu3.misc_regfile_reads 106918 # number of misc regfile reads
system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
system.cpu3.icache.replacements 323 # number of replacements
system.cpu3.icache.tagsinuse 88.249587 # Cycle average of tags in use
system.cpu3.icache.total_refs 23982 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 439 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 54.628702 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst 88.249587 # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst 0.172362 # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total 0.172362 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 23982 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 23982 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 23982 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 23982 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 23982 # number of overall hits
system.cpu3.icache.overall_hits::total 23982 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses
system.cpu3.icache.overall_misses::total 503 # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7707000 # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total 7707000 # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst 7707000 # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total 7707000 # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst 7707000 # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total 7707000 # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst 24485 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 24485 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 24485 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 24485 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 24485 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 24485 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020543 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.020543 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020543 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.020543 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020543 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.020543 # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15322.067594 # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 15322.067594 # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 15322.067594 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15322.067594 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 15322.067594 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 64 # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst 64 # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst 64 # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total 64 # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 439 # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total 439 # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst 439 # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 439 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 439 # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5684000 # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total 5684000 # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5684000 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total 5684000 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5684000 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total 5684000 # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017929 # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total 0.017929 # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017929 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total 0.017929 # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12947.608200 # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12947.608200 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12947.608200 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 0 # number of replacements
system.cpu3.dcache.tagsinuse 26.048284 # Cycle average of tags in use
system.cpu3.dcache.total_refs 38388 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 1323.724138 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data 26.048284 # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data 0.050876 # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total 0.050876 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 43625 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 43625 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 31927 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 31927 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 16 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 16 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 75552 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 75552 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 75552 # number of overall hits
system.cpu3.dcache.overall_hits::total 75552 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 356 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 356 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 134 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 134 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 490 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses
system.cpu3.dcache.overall_misses::total 490 # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9997000 # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total 9997000 # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3151500 # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total 3151500 # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1323000 # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total 1323000 # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data 13148500 # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total 13148500 # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data 13148500 # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total 13148500 # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data 43981 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 43981 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 32061 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 32061 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 76042 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 76042 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 76042 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 76042 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008094 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004180 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.004180 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.777778 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.777778 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006444 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.006444 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006444 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.006444 # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 28081.460674 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 28081.460674 # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23518.656716 # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 23518.656716 # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 23625 # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 23625 # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 26833.673469 # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 26833.673469 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 26833.673469 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 26833.673469 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2771504 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2771504 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1583000 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1583000 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1148500 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1148500 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4354504 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total 4354504 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4354504 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total 4354504 # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003661 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003661 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003181 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003181 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.777778 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.777778 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003459 # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total 0.003459 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003459 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.003459 # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17214.310559 # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17214.310559 # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15519.607843 # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15519.607843 # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20508.928571 # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20508.928571 # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16557.049430 # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16557.049430 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16557.049430 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16557.049430 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
system.l2c.tagsinuse 436.337885 # Cycle average of tags in use
system.l2c.total_refs 1474 # Total number of references to valid blocks.
system.l2c.sampled_refs 537 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.744879 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 0.838584 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 294.109117 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 59.534191 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 68.191567 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 5.703860 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 2.346215 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 0.730565 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst 4.110047 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data 0.773739 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.004488 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.000908 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.001041 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst 0.000063 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.006658 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 233 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 350 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 428 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst 233 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 350 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 428 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 431 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
system.l2c.demand_hits::total 1474 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 233 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 350 # number of overall hits
system.l2c.overall_hits::cpu1.data 5 # number of overall hits
system.l2c.overall_hits::cpu2.inst 428 # number of overall hits
system.l2c.overall_hits::cpu2.data 11 # number of overall hits
system.l2c.overall_hits::cpu3.inst 431 # number of overall hits
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
system.l2c.overall_hits::total 1474 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 362 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 86 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 10 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst 8 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::total 549 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 20 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 21 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 680 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 362 # number of overall misses
system.l2c.overall_misses::cpu0.data 168 # number of overall misses
system.l2c.overall_misses::cpu1.inst 86 # number of overall misses
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
system.l2c.overall_misses::cpu2.inst 10 # number of overall misses
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
system.l2c.overall_misses::cpu3.inst 8 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 680 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 19202500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 4170000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 4498000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 377500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 449000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 52500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst 386000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 29188000 # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 5156500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 751000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 663000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 658499 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7228999 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 19202500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 9326500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 4498000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1128500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 449000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 715500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 386000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data 710999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 36416999 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 19202500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 9326500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 4498000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1128500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 449000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 715500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 386000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 710999 # number of overall miss cycles
system.l2c.overall_miss_latency::total 36416999 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 595 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 436 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 438 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst 439 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2023 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 23 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 21 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 595 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 436 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 438 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 439 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2154 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 595 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 436 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 438 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 439 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2154 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.608403 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.197248 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.022831 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.018223 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.271379 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.869565 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.962500 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.608403 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.197248 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.022831 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.018223 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.315692 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.608403 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.197248 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.022831 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.018223 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.315692 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53045.580110 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 56351.351351 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52302.325581 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 53928.571429 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 44900 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 48250 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 53165.755920 # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54856.382979 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57769.230769 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 55250 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 54874.916667 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 55183.198473 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 53045.580110 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 55514.880952 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52302.325581 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 56425 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 44900 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 55038.461538 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 48250 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 54692.230769 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 53554.410294 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 53045.580110 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 55514.880952 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52302.325581 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 56425 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 44900 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 55038.461538 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 48250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 54692.230769 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 53554.410294 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst 362 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 84 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 5 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 540 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 20 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 362 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 84 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 5 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 671 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 362 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 84 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 5 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 671 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14801500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3274000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3420500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 291500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 200000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 240000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 22307500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 800000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 840000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 844000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 605000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 3089000 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4012500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 516500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5634000 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 14801500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 7286500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 3420500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 885000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 200000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 556500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 240000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 551500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 27941500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 14801500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 7286500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 3420500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 885000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 200000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 556500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 240000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 551500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 27941500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.266930 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.869565 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.962500 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.311513 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.608403 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.311513 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44243.243243 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 41310.185185 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40333.333333 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40116.883117 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42686.170213 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42625 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 43007.633588 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43372.023810 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43372.023810 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|