1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000107 # Number of seconds simulated
sim_ticks 107049000 # Number of ticks simulated
final_tick 107049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 93620 # Simulator instruction rate (inst/s)
host_op_rate 93620 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10161795 # Simulator tick rate (ticks/s)
host_mem_usage 304708 # Number of bytes of host memory used
host_seconds 10.53 # Real time elapsed on the host
sim_insts 986230 # Number of instructions simulated
sim_ops 986230 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 42560 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 665 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 215228540 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 101037842 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 49024279 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 11957141 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 1793571 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 7772142 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 2989285 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 7772142 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 397574942 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 215228540 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 49024279 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 1793571 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 2989285 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 269035675 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 215228540 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 101037842 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 49024279 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 11957141 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 1793571 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 7772142 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 2989285 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 7772142 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 397574942 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 666 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 42624 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 42624 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 114 # Per bank write bursts
system.physmem.perBankRdBursts::1 42 # Per bank write bursts
system.physmem.perBankRdBursts::2 30 # Per bank write bursts
system.physmem.perBankRdBursts::3 60 # Per bank write bursts
system.physmem.perBankRdBursts::4 66 # Per bank write bursts
system.physmem.perBankRdBursts::5 27 # Per bank write bursts
system.physmem.perBankRdBursts::6 18 # Per bank write bursts
system.physmem.perBankRdBursts::7 24 # Per bank write bursts
system.physmem.perBankRdBursts::8 7 # Per bank write bursts
system.physmem.perBankRdBursts::9 28 # Per bank write bursts
system.physmem.perBankRdBursts::10 23 # Per bank write bursts
system.physmem.perBankRdBursts::11 13 # Per bank write bursts
system.physmem.perBankRdBursts::12 61 # Per bank write bursts
system.physmem.perBankRdBursts::13 38 # Per bank write bursts
system.physmem.perBankRdBursts::14 18 # Per bank write bursts
system.physmem.perBankRdBursts::15 97 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 107021000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 666 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 198 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 276.444444 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 188.969078 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 251.786617 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 36 25.00% 54.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 28 19.44% 74.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 12 8.33% 82.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 7 4.86% 87.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 8 5.56% 93.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 1.39% 94.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 2.08% 96.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation
system.physmem.totQLat 6009250 # Total ticks spent queuing
system.physmem.totMemAccLat 18496750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9022.90 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 27772.90 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 398.17 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 398.17 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.11 # Data bus utilization in percentage
system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 511 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.73 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 160692.19 # Average gap between requests
system.physmem.pageHitRate 76.73 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 37638810 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27872250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 75978045 # Total energy per rank (pJ)
system.physmem_0.averagePower 748.690472 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 47858250 # Time in different power states
system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 51979250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 32994450 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 31946250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 74129175 # Total energy per rank (pJ)
system.physmem_1.averagePower 730.471639 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 55670750 # Time in different power states
system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 45162250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu0.branchPred.lookups 81022 # Number of BP lookups
system.cpu0.branchPred.condPredicted 78376 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 78355 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 75640 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 96.535001 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 214099 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 19687 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 478911 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 81022 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 76285 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 164512 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 1992 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 617 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 187540 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 2.553647 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.214546 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 30407 16.21% 16.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 77695 41.43% 57.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 798 0.43% 58.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 1205 0.64% 58.71% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 612 0.33% 59.04% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 73095 38.98% 98.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 670 0.36% 98.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 402 0.21% 98.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 2656 1.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 187540 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.378432 # Number of branch fetches per cycle
system.cpu0.fetch.rate 2.236867 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 15435 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 18383 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 151822 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 650 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts 468409 # Number of instructions handled by decode
system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 16041 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 2079 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 14982 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 151818 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 1370 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 465227 # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 867 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 318145 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 927822 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 700792 # Number of integer rename lookups
system.cpu0.rename.CommittedMaps 305063 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 13082 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 4377 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 148776 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 75241 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 72733 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 72329 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 389183 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 385745 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 12312 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 11729 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 187540 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 2.056868 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.126403 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 33477 17.85% 17.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 4232 2.26% 20.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 73531 39.21% 59.32% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 73185 39.02% 98.34% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1601 0.85% 99.19% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 889 0.47% 99.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 403 0.21% 99.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 75 0.04% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 187540 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 61 21.11% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.11% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 125 43.25% 64.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 163127 42.29% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 148129 38.40% 80.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 74489 19.31% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 385745 # Type of FU issued
system.cpu0.iq.rate 1.801713 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.000749 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 959350 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 402446 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 383893 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 386034 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 71845 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2655 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 2043 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 463105 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 148776 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 75241 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 990 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 1308 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 384734 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 147791 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 73033 # number of nop insts executed
system.cpu0.iew.exec_refs 222131 # number of memory reference insts executed
system.cpu0.iew.exec_branches 76355 # Number of branches executed
system.cpu0.iew.exec_stores 74340 # Number of stores executed
system.cpu0.iew.exec_rate 1.796991 # Inst execution rate
system.cpu0.iew.wb_sent 384301 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 383893 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 227714 # num instructions producing a value
system.cpu0.iew.wb_consumers 230757 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 1.793063 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.986813 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 13101 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 185078 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 2.431116 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 2.149204 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 33718 18.22% 18.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 75423 40.75% 58.97% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 1935 1.05% 60.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 662 0.36% 60.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 535 0.29% 60.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 71534 38.65% 99.31% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 523 0.28% 99.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 185078 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 449946 # Number of instructions committed
system.cpu0.commit.committedOps 449946 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 219688 # Number of memory references committed
system.cpu0.commit.loads 146121 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
system.cpu0.commit.branches 75454 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 303394 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 72186 16.04% 16.04% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 157988 35.11% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 146205 32.49% 83.65% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 73567 16.35% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 449946 # Class of committed instruction
system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 646481 # The number of ROB reads
system.cpu0.rob.rob_writes 928572 # The number of ROB writes
system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 26559 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 377676 # Number of Instructions Simulated
system.cpu0.committedOps 377676 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 0.566885 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 0.566885 # CPI: Total CPI of All Threads
system.cpu0.ipc 1.764025 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 1.764025 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 688304 # number of integer regfile reads
system.cpu0.int_regfile_writes 310378 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
system.cpu0.misc_regfile_reads 223999 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 2 # number of replacements
system.cpu0.dcache.tags.tagsinuse 141.054653 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 148243 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 866.918129 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.054653 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275497 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.275497 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 598124 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 598124 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 75326 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 75326 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 72968 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 72968 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 148294 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 148294 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 148294 # number of overall hits
system.cpu0.dcache.overall_hits::total 148294 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 561 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 561 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1118 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1118 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1118 # number of overall misses
system.cpu0.dcache.overall_misses::total 1118 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17156000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 17156000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33757980 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 33757980 # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 50913980 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 50913980 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 50913980 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 50913980 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 75887 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 75887 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 73525 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 73525 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 149412 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 149412 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 149412 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 149412 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007393 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007576 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.007576 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007483 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.007483 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007483 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.007483 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30581.105169 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 30581.105169 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60606.786355 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 60606.786355 # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 45540.232558 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 45540.232558 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 380 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 380 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 758 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 758 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 758 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 758 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6883000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6883000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8240500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8240500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15123500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 15123500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15123500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 15123500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002411 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002411 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002407 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002407 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002409 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002409 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37612.021858 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37612.021858 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46556.497175 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46556.497175 # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 315 # number of replacements
system.cpu0.icache.tags.tagsinuse 241.042514 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.042514 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470786 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.470786 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits
system.cpu0.icache.overall_hits::total 5949 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 784 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 784 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 784 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses
system.cpu0.icache.overall_misses::total 784 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40365000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 40365000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 40365000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 40365000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 40365000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 6733 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 6733 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 6733 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116441 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.116441 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51485.969388 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 51485.969388 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 51485.969388 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 51485.969388 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 176 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 176 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 176 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 176 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 176 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 176 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31177000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 31177000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31177000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 31177000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31177000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 31177000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51277.960526 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 50039 # Number of BP lookups
system.cpu1.branchPred.condPredicted 46665 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 42823 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 41749 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 97.492002 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 914 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
system.cpu1.numCycles 161348 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 31303 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 275372 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 50039 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 42663 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 121719 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 21928 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 155480 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.771109 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.178899 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 58088 37.36% 37.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 49421 31.79% 69.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 6835 4.40% 73.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 3518 2.26% 75.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 944 0.61% 76.41% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 30727 19.76% 96.18% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1228 0.79% 96.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 804 0.52% 97.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 3915 2.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 155480 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.310131 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.706696 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 17833 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 58352 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 74506 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 3430 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1349 # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts 260078 # Number of instructions handled by decode
system.cpu1.rename.SquashCycles 1349 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 18539 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 27109 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 13862 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 76429 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 18182 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 256857 # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents 16651 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 180872 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 489824 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 382391 # Number of integer rename lookups
system.cpu1.rename.CommittedMaps 167019 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 13853 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 22657 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 71171 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 33454 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 33920 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 28372 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 213121 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 6586 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 214969 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 13076 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 10906 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 730 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 155480 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 1.382615 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.383057 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 61906 39.82% 39.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 21977 14.13% 53.95% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 32894 21.16% 75.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 32429 20.86% 95.96% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 3365 2.16% 98.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1605 1.03% 99.16% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 896 0.58% 99.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 208 0.13% 99.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 155480 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 79 23.72% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.72% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 45 13.51% 37.24% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 106597 49.59% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 75532 35.14% 84.72% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 32840 15.28% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 214969 # Type of FU issued
system.cpu1.iq.rate 1.332331 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 333 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.001549 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 585768 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 232822 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 213429 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 215302 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 28182 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1503 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 7989 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 254448 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 71171 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 33454 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 1051 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 213962 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 70077 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1007 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 34741 # number of nop insts executed
system.cpu1.iew.exec_refs 102825 # number of memory reference insts executed
system.cpu1.iew.exec_branches 44094 # Number of branches executed
system.cpu1.iew.exec_stores 32748 # Number of stores executed
system.cpu1.iew.exec_rate 1.326090 # Inst execution rate
system.cpu1.iew.wb_sent 213711 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 213429 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 120431 # num instructions producing a value
system.cpu1.iew.wb_consumers 127039 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 1.322787 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.947984 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 13922 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 5856 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 152910 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 1.572631 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 2.035068 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 67472 44.13% 44.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 40678 26.60% 70.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 5251 3.43% 74.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 6680 4.37% 78.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1520 0.99% 79.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 28236 18.47% 97.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 823 0.54% 98.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 947 0.62% 99.15% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1303 0.85% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 152910 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 240471 # Number of instructions committed
system.cpu1.commit.committedOps 240471 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 100469 # Number of memory references committed
system.cpu1.commit.loads 68518 # Number of loads committed
system.cpu1.commit.membars 5139 # Number of memory barriers committed
system.cpu1.commit.branches 43053 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 165641 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 33840 14.07% 14.07% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 101023 42.01% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.08% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 73657 30.63% 86.71% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 31951 13.29% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 240471 # Class of committed instruction
system.cpu1.commit.bw_lim_events 1303 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 405414 # The number of ROB reads
system.cpu1.rob.rob_writes 511356 # The number of ROB writes
system.cpu1.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 201492 # Number of Instructions Simulated
system.cpu1.committedOps 201492 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 0.800766 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 0.800766 # CPI: Total CPI of All Threads
system.cpu1.ipc 1.248804 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 1.248804 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 368266 # number of integer regfile reads
system.cpu1.int_regfile_writes 172947 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
system.cpu1.misc_regfile_reads 104453 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 0 # number of replacements
system.cpu1.dcache.tags.tagsinuse 25.714463 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 38066 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 1312.620690 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.714463 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050224 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.050224 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 295559 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 295559 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 41369 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 41369 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 31720 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 31720 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 73089 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 73089 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 73089 # number of overall hits
system.cpu1.dcache.overall_hits::total 73089 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 504 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 504 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 664 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 664 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 664 # number of overall misses
system.cpu1.dcache.overall_misses::total 664 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9769000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 9769000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3369500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 3369500 # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 693500 # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total 693500 # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 13138500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 13138500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 13138500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 13138500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 41873 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 41873 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 31880 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 31880 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 73753 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 73753 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 73753 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 73753 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012036 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.012036 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005019 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.005019 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.788732 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.009003 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.009003 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.009003 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.009003 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19382.936508 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19382.936508 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21059.375000 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21059.375000 # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12383.928571 # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 12383.928571 # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19786.897590 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 19786.897590 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 385 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 385 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 385 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 385 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2195000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2195000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1746000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1746000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 637500 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 637500 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3941000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 3941000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3941000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 3941000 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004108 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004108 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003356 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003356 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.788732 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.003783 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.003783 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12761.627907 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12761.627907 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16317.757009 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16317.757009 # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11383.928571 # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11383.928571 # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 383 # number of replacements
system.cpu1.icache.tags.tagsinuse 84.275379 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 21349 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 43.042339 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.275379 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164600 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.164600 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 22424 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 22424 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 21349 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 21349 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 21349 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 21349 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 21349 # number of overall hits
system.cpu1.icache.overall_hits::total 21349 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 579 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 579 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 579 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 579 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 579 # number of overall misses
system.cpu1.icache.overall_misses::total 579 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13955500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 13955500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 13955500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 13955500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 13955500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 13955500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 21928 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 21928 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 21928 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 21928 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 21928 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 21928 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026405 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.026405 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026405 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.026405 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026405 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.026405 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24102.763385 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 24102.763385 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 24102.763385 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 24102.763385 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 83 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 83 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 83 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 83 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11502500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 11502500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11502500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 11502500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11502500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 11502500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022619 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.022619 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.022619 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23190.524194 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.branchPred.lookups 42880 # Number of BP lookups
system.cpu2.branchPred.condPredicted 39445 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 1259 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 35521 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 34492 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 97.103122 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
system.cpu2.numCycles 160976 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 36449 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 226588 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 42880 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 35396 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 120624 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles 1157 # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines 27680 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 159581 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.419893 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.036694 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 73772 46.23% 46.23% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 45044 28.23% 74.45% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 9695 6.08% 80.53% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 3476 2.18% 82.71% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 968 0.61% 83.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 20661 12.95% 96.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 1186 0.74% 97.01% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 799 0.50% 97.51% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 3980 2.49% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 159581 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.266375 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.407589 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 17760 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 80804 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 54882 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 4787 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 1338 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 211151 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 1338 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 18439 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 40468 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 13548 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 56825 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 28953 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 208031 # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents 26065 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands 143630 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 381000 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 300757 # Number of integer rename lookups
system.cpu2.rename.CommittedMaps 129882 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 13748 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 1262 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 33404 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 53977 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 23458 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 26723 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 18373 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 168634 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 9408 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 173236 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 12983 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 10808 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 159581 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.085568 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.335871 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 77748 48.72% 48.72% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 30232 18.94% 67.66% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 22868 14.33% 81.99% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 22470 14.08% 96.08% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 3364 2.11% 98.18% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 1606 1.01% 99.19% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 879 0.55% 99.74% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 214 0.13% 99.87% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 159581 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 79 23.94% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.94% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 42 12.73% 36.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 89318 51.56% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.56% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 61054 35.24% 86.80% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 22864 13.20% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 173236 # Type of FU issued
system.cpu2.iq.rate 1.076160 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 330 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.001905 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 506398 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 191064 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 171727 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 173566 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 18193 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 10563 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 81 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 205567 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 53977 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 23458 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 1137 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 1053 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 1483 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 172231 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 52840 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 1005 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 27525 # number of nop insts executed
system.cpu2.iew.exec_refs 75615 # number of memory reference insts executed
system.cpu2.iew.exec_branches 36863 # Number of branches executed
system.cpu2.iew.exec_stores 22775 # Number of stores executed
system.cpu2.iew.exec_rate 1.069917 # Inst execution rate
system.cpu2.iew.wb_sent 171997 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 171727 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 93200 # num instructions producing a value
system.cpu2.iew.wb_consumers 99800 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.066786 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.933868 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 13823 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 8627 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 1259 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 157016 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.220837 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.865055 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 86039 54.80% 54.80% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 33434 21.29% 76.09% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 5238 3.34% 79.43% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 9429 6.01% 85.43% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 1533 0.98% 86.41% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 18255 11.63% 98.03% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 831 0.53% 98.56% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 1302 0.83% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 157016 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 191691 # Number of instructions committed
system.cpu2.commit.committedOps 191691 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 73311 # Number of memory references committed
system.cpu2.commit.loads 51335 # Number of loads committed
system.cpu2.commit.membars 7910 # Number of memory barriers committed
system.cpu2.commit.branches 35845 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 131277 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 26632 13.89% 13.89% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 83838 43.74% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 59245 30.91% 88.54% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 21976 11.46% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 191691 # Class of committed instruction
system.cpu2.commit.bw_lim_events 1302 # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads 360642 # The number of ROB reads
system.cpu2.rob.rob_writes 413593 # The number of ROB writes
system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1395 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 157149 # Number of Instructions Simulated
system.cpu2.committedOps 157149 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.024353 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.024353 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.976226 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.976226 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 286558 # number of integer regfile reads
system.cpu2.int_regfile_writes 135654 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
system.cpu2.misc_regfile_reads 77226 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.dcache.tags.replacements 0 # number of replacements
system.cpu2.dcache.tags.tagsinuse 23.071332 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 27978 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs 999.214286 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.071332 # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045061 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total 0.045061 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses 226658 # Number of tag accesses
system.cpu2.dcache.tags.data_accesses 226658 # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data 34141 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 34141 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 21749 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 21749 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 55890 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 55890 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 55890 # number of overall hits
system.cpu2.dcache.overall_hits::total 55890 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 483 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 483 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 156 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 156 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 639 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 639 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 639 # number of overall misses
system.cpu2.dcache.overall_misses::total 639 # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7783500 # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total 7783500 # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3187000 # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total 3187000 # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 671500 # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total 671500 # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data 10970500 # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total 10970500 # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data 10970500 # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total 10970500 # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data 34624 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 34624 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 21905 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 21905 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 56529 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 56529 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 56529 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 56529 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.013950 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.013950 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007122 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.007122 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.732394 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.011304 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.011304 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.011304 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.011304 # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16114.906832 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 16114.906832 # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20429.487179 # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 20429.487179 # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12913.461538 # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 12913.461538 # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 17168.231612 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 17168.231612 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data 364 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data 364 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 172 # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data 275 # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 275 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1811500 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1811500 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1702500 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1702500 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 619500 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 619500 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3514000 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total 3514000 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3514000 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total 3514000 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004968 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004968 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004702 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004702 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.732394 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total 0.004865 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.004865 # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10531.976744 # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10531.976744 # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16529.126214 # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16529.126214 # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11913.461538 # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11913.461538 # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.icache.tags.replacements 386 # number of replacements
system.cpu2.icache.tags.tagsinuse 77.667456 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 27109 # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs 54.218000 # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.667456 # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151694 # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total 0.151694 # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses 28180 # Number of tag accesses
system.cpu2.icache.tags.data_accesses 28180 # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst 27109 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 27109 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 27109 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 27109 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 27109 # number of overall hits
system.cpu2.icache.overall_hits::total 27109 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 571 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 571 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 571 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 571 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 571 # number of overall misses
system.cpu2.icache.overall_misses::total 571 # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7541500 # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total 7541500 # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst 7541500 # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total 7541500 # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst 7541500 # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total 7541500 # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst 27680 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 27680 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 27680 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 27680 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 27680 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 27680 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020629 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.020629 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020629 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.020629 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020629 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.020629 # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13207.530648 # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 13207.530648 # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 13207.530648 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 13207.530648 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 71 # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst 71 # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst 71 # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total 71 # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6543500 # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total 6543500 # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6543500 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total 6543500 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6543500 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total 6543500 # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.018064 # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total 0.018064 # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total 0.018064 # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13087 # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13087 # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.branchPred.lookups 58611 # Number of BP lookups
system.cpu3.branchPred.condPredicted 55067 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 51125 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 50131 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct 98.055746 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
system.cpu3.numCycles 160611 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles 27021 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 330369 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 58611 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 51037 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 129883 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 2715 # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines 18269 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples 159439 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 2.072071 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.246890 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0 47077 29.53% 29.53% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 55913 35.07% 64.60% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 4932 3.09% 67.69% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 3522 2.21% 69.90% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 934 0.59% 70.48% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 40952 25.69% 96.17% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 1272 0.80% 96.97% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 798 0.50% 97.47% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 4039 2.53% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total 159439 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.364925 # Number of branch fetches per cycle
system.cpu3.fetch.rate 2.056951 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 16993 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 43740 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 94729 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 2610 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 1357 # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts 315004 # Number of instructions handled by decode
system.cpu3.rename.SquashCycles 1357 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 17735 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 17944 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 14128 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 95562 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 12703 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 311495 # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents 10931 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands 220426 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 606441 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 469854 # Number of integer rename lookups
system.cpu3.rename.CommittedMaps 206787 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 13639 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 1207 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 17457 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 89942 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 43802 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 42282 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 38692 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 261084 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 4750 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 261694 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 12498 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 9712 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 614 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 159439 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 1.641342 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.359128 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0 50249 31.52% 31.52% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 16842 10.56% 42.08% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 43259 27.13% 69.21% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 42799 26.84% 96.05% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 3393 2.13% 98.18% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 1616 1.01% 99.20% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 876 0.55% 99.75% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 194 0.12% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total 159439 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu 81 26.21% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.21% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 19 6.15% 32.36% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 209 67.64% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 125700 48.03% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 92778 35.45% 83.49% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 43216 16.51% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total 261694 # Type of FU issued
system.cpu3.iq.rate 1.629365 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 683137 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 278366 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 260191 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 262003 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 38539 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 1484 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles 1357 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 5389 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 51 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 309030 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 159 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 89942 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 43802 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 441 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 1075 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 1516 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 260676 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 89042 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 1018 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
system.cpu3.iew.exec_nop 43196 # number of nop insts executed
system.cpu3.iew.exec_refs 132177 # number of memory reference insts executed
system.cpu3.iew.exec_branches 52784 # Number of branches executed
system.cpu3.iew.exec_stores 43135 # Number of stores executed
system.cpu3.iew.exec_rate 1.623027 # Inst execution rate
system.cpu3.iew.wb_sent 260451 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 260191 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 149829 # num instructions producing a value
system.cpu3.iew.wb_consumers 156442 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate 1.620007 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.957729 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts 13144 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 4136 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 156952 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 1.884863 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 2.121598 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0 54210 34.54% 34.54% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 49323 31.43% 65.96% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 5280 3.36% 69.33% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 4930 3.14% 72.47% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 1531 0.98% 73.45% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 38585 24.58% 98.03% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 839 0.53% 98.56% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 1299 0.83% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total 156952 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 295833 # Number of instructions committed
system.cpu3.commit.committedOps 295833 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.refs 129866 # Number of memory references committed
system.cpu3.commit.loads 87548 # Number of loads committed
system.cpu3.commit.membars 3423 # Number of memory barriers committed
system.cpu3.commit.branches 51706 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 203693 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass 42497 14.37% 14.37% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu 120047 40.58% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.94% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead 90971 30.75% 85.70% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 42318 14.30% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total 295833 # Class of committed instruction
system.cpu3.commit.bw_lim_events 1299 # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads 464044 # The number of ROB reads
system.cpu3.rob.rob_writes 620441 # The number of ROB writes
system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 1172 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 249913 # Number of Instructions Simulated
system.cpu3.committedOps 249913 # Number of Ops (including micro ops) Simulated
system.cpu3.cpi 0.642668 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 0.642668 # CPI: Total CPI of All Threads
system.cpu3.ipc 1.556014 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 1.556014 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 456401 # number of integer regfile reads
system.cpu3.int_regfile_writes 212686 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
system.cpu3.misc_regfile_reads 133817 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
system.cpu3.dcache.tags.replacements 0 # number of replacements
system.cpu3.dcache.tags.tagsinuse 24.217896 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 48316 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs 1725.571429 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.217896 # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047301 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total 0.047301 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses 371433 # Number of tag accesses
system.cpu3.dcache.tags.data_accesses 371433 # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data 49959 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 49959 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 42098 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 42098 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 92057 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 92057 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 92057 # number of overall hits
system.cpu3.dcache.overall_hits::total 92057 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 521 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 521 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 153 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 153 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 674 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 674 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 674 # number of overall misses
system.cpu3.dcache.overall_misses::total 674 # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8076500 # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total 8076500 # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3408500 # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total 3408500 # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 574500 # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total 574500 # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data 11485000 # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total 11485000 # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data 11485000 # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total 11485000 # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data 50480 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 50480 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 42251 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 42251 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 92731 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 92731 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 92731 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 92731 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010321 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.010321 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003621 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.003621 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805970 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007268 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.007268 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007268 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.007268 # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15501.919386 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 15501.919386 # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22277.777778 # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 22277.777778 # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10638.888889 # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 10638.888889 # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 17040.059347 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 17040.059347 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 369 # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 48 # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data 417 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total 417 # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data 417 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total 417 # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1413000 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1413000 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2020500 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2020500 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 520500 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 520500 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3433500 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total 3433500 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3433500 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total 3433500 # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003011 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003011 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002485 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002485 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805970 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805970 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total 0.002771 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.002771 # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9296.052632 # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9296.052632 # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19242.857143 # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19242.857143 # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9638.888889 # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9638.888889 # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.icache.tags.replacements 384 # number of replacements
system.cpu3.icache.tags.tagsinuse 80.866510 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 17696 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs 35.534137 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.866510 # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157942 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total 0.157942 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses 18767 # Number of tag accesses
system.cpu3.icache.tags.data_accesses 18767 # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst 17696 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 17696 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 17696 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 17696 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 17696 # number of overall hits
system.cpu3.icache.overall_hits::total 17696 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 573 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 573 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 573 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 573 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 573 # number of overall misses
system.cpu3.icache.overall_misses::total 573 # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7430000 # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total 7430000 # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst 7430000 # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total 7430000 # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst 7430000 # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total 7430000 # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst 18269 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 18269 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 18269 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 18269 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 18269 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 18269 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.031365 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.031365 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.031365 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.031365 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.031365 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.031365 # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12966.841187 # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 12966.841187 # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 12966.841187 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 12966.841187 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 75 # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst 75 # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst 75 # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total 75 # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6421000 # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total 6421000 # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6421000 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total 6421000 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6421000 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total 6421000 # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.027259 # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total 0.027259 # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.027259 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total 0.027259 # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12893.574297 # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 418.779018 # Cycle average of tags in use
system.l2c.tags.total_refs 2347 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 0.786962 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 287.801372 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 58.040061 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 61.655177 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 5.312296 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2.346047 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 0.677363 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 1.443236 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 0.716504 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.004392 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.000941 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.000022 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.006390 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 25618 # Number of tag accesses
system.l2c.tags.data_accesses 25618 # Number of data accesses
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 491 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 410 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 491 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
system.l2c.demand_hits::total 1670 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 246 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 410 # number of overall hits
system.l2c.overall_hits::cpu1.data 5 # number of overall hits
system.l2c.overall_hits::cpu2.inst 491 # number of overall hits
system.l2c.overall_hits::cpu2.data 11 # number of overall hits
system.l2c.overall_hits::cpu3.inst 491 # number of overall hits
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
system.l2c.overall_hits::total 1670 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 27 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 86 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 9 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst 7 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 679 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 362 # number of overall misses
system.l2c.overall_misses::cpu0.data 169 # number of overall misses
system.l2c.overall_misses::cpu1.inst 86 # number of overall misses
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
system.l2c.overall_misses::cpu2.inst 9 # number of overall misses
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
system.l2c.overall_misses::cpu3.inst 7 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 679 # number of overall misses
system.l2c.ReadExReq_miss_latency::cpu0.data 7390000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1059000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 956500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 1308500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10714000 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27682000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6449000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 632000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 514000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 35277000 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 5980500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 540500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data 82500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data 96500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 6700000 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 27682000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 13370500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 6449000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1599500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 632000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 1039000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 514000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data 1405000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 52691000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 27682000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 13370500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 6449000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1599500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 632000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 1039000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 514000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 1405000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 52691000 # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 608 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 496 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst 500 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst 498 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 2102 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 80 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 12 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data 12 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data 12 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 116 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 608 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 496 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 500 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2349 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 608 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 496 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 500 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2349 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.967391 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173387 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.173387 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.014056 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.289059 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.595395 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.173387 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.018000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.014056 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.289059 # miss rate for overall accesses
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78617.021277 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79708.333333 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 109041.666667 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 81786.259542 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76469.613260 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74988.372093 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 70222.222222 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 73428.571429 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 76028.017241 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79740 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77214.285714 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82500 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 96500 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 79761.904762 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 76469.613260 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 79115.384615 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74988.372093 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 79975 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 70222.222222 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 79923.076923 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 73428.571429 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 108076.923077 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 77600.883652 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 76469.613260 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 79115.384615 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74988.372093 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 79975 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 70222.222222 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 79923.076923 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 73428.571429 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 108076.923077 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 77600.883652 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 6 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 2 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits
system.l2c.UpgradeReq_mshr_misses::cpu0.data 27 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 22 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 89 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 361 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 82 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 3 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 5 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 451 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 7 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 82 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 3 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 5 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 666 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 82 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 3 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 5 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 666 # number of overall MSHR misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 560500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 396000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 438496 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 459499 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 1854495 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6450000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 929000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 836500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1188500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 9404000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 23878500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5430000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 217000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 364000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 29889500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5230500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 470500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 72500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 86500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 5860000 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 23878500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 11680500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 5430000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1399500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 217000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 909000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 364000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 1275000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 45153500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 23878500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 11680500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 5430000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1399500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 217000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 909000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 364000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 1275000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 45153500 # number of overall MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.967391 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.259259 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20842.105263 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20880.761905 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20886.318182 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20837.022472 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68617.021277 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69708.333333 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 99041.666667 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 71786.259542 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72800 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66273.835920 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69740 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 534 # Transaction distribution
system.membus.trans_dist::UpgradeReq 292 # Transaction distribution
system.membus.trans_dist::UpgradeResp 89 # Transaction distribution
system.membus.trans_dist::ReadExReq 161 # Transaction distribution
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1742 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1742 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 233 # Total snoops (count)
system.membus.snoop_fanout::samples 988 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 988 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 988 # Request fanout histogram
system.membus.reqLayer0.occupancy 929005 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
system.toL2Bus.trans_dist::ReadResp 2782 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 677 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 295 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 295 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 681 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 357 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 6585 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1026 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 4937 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 4937 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 4937 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2487961 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 509492 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 443468 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 752993 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 440464 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 407479 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
|