path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000106                       # Number of seconds simulated
sim_ticks                                   105639000                       # Number of ticks simulated
final_tick                                  105639000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 115016                       # Simulator instruction rate (inst/s)
host_op_rate                                   115016                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               12246117                       # Simulator tick rate (ticks/s)
host_mem_usage                                 253808                       # Number of bytes of host memory used
host_seconds                                     8.63                       # Real time elapsed on the host
sim_insts                                      992165                       # Number of instructions simulated
sim_ops                                        992165                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst            23104                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst              768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst             4928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data             1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                42752                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        23104                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst          768                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst         4928                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           29056                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               361                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                12                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                77                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   668                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           218707106                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data           101780592                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst             7270042                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             7875879                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst            46649438                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data            12116737                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             2423347                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7875879                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               404699022                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      218707106                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst        7270042                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst       46649438                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        2423347                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          275049934                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          218707106                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data          101780592                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst            7270042                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            7875879                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst           46649438                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data           12116737                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            2423347                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7875879                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              404699022                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           669                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         669                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    42816                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     42816                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             78                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 114                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  42                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  30                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  60                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  65                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  18                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  24                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 13                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 65                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 38                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 17                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 97                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                       105611000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     669                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       400                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       193                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          144                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      278.222222                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     188.203281                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     257.152031                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             43     29.86%     29.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           39     27.08%     56.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           24     16.67%     73.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           13      9.03%     82.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            6      4.17%     86.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            6      4.17%     90.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            6      4.17%     95.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            2      1.39%     96.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            5      3.47%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            144                       # Bytes accessed per row activation
system.physmem.totQLat                        6117250                       # Total ticks spent queuing
system.physmem.totMemAccLat                  18661000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3345000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9143.87                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27893.87                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         405.30                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      405.30                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.17                       # Data bus utilization in percentage
system.physmem.busUtilRead                       3.17                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.23                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        514                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.83                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       157863.98                       # Average gap between requests
system.physmem.pageHitRate                      76.83                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE         46009250                       # Time in different power states
system.physmem.memoryStateTime::REF           3380000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT          52645250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                    404699022                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 538                       # Transaction distribution
system.membus.trans_dist::ReadResp                537                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              272                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              78                       # Transaction distribution
system.membus.trans_dist::ReadExReq               182                       # Transaction distribution
system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1738                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1738                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port        42752                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               42752                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  42752                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              937500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
system.membus.respLayer1.occupancy            6389922                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              6.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  424.251527                       # Cycle average of tags in use
system.l2c.tags.total_refs                       1658                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      535                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.099065                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks       0.793481                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      289.756161                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data       58.232417                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst        9.250622                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data        0.723175                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst       57.184063                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data        5.359898                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        2.266069                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        0.685642                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.004421                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.000889                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.000141                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000011                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000873                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000082                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000035                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000010                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.006474                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          535                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          117                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.008163                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    20037                       # Number of tag accesses
system.l2c.tags.data_accesses                   20037                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst                250                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                481                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                409                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                486                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1658                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 250                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 481                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 409                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 486                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1658                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                250                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                481                       # number of overall hits
system.l2c.overall_hits::cpu1.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                409                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                486                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   1658                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              363                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               16                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               81                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  550                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            23                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            17                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            18                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            20                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                78                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               363                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                81                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   681                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              363                       # number of overall misses
system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               16                       # number of overall misses
system.l2c.overall_misses::cpu1.data               13                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               81                       # number of overall misses
system.l2c.overall_misses::cpu2.data               20                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                7                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  681                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     25055500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      5652750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      1295250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data        75000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst      5783750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data       523250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       458000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        75000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       38918500                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      6921000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       852750                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data      1047250                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       836500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      9657500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     25055500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     12573750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      1295250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data       927750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      5783750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1570500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       458000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       911500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        48576000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     25055500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     12573750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      1295250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data       927750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      5783750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1570500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       458000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       911500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       48576000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            613                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            497                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            490                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            493                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               2208                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           26                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           17                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           18                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              81                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             613                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             497                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             490                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             493                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2339                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            613                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            497                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            490                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            493                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2339                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.592170                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.032193                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.165306                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.583333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.014199                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.249094                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.884615                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.962963                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.592170                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.032193                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.165306                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.800000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.014199                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.291150                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.592170                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.032193                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.165306                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.800000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.014199                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.291150                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69023.415978                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 76388.513514                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80953.125000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 71404.320988                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        74750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65428.571429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 70760.909091                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73627.659574                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71062.500000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80557.692308                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 69708.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73721.374046                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 69023.415978                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 74843.750000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80953.125000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 71365.384615                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 71404.320988                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data        78525                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 65428.571429                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 70115.384615                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71330.396476                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 69023.415978                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 74843.750000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80953.125000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 71365.384615                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 71404.320988                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data        78525                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 65428.571429                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 70115.384615                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71330.396476                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                12                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 12                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                12                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          362                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           12                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst           77                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             538                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           23                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           17                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           18                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           20                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           78                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          362                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           12                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           77                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              669                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          362                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           12                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           77                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             669                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     20468500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      4740250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       904000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      4615250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data       436250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       236250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     31525500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       230023                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       170017                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       180018                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       200020                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       780078                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5761500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       701250                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       888250                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       687000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      8038000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     20468500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     10501750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst       904000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       763750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      4615250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1324500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       236250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       749500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     39563500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     20468500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     10501750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst       904000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       763750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      4615250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1324500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       236250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       749500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     39563500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.590538                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.024145                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.157143                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.583333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.008114                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.243659                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.884615                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.962963                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.590538                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.024145                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.157143                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.008114                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.286020                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.590538                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.024145                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.157143                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.008114                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.286020                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56542.817680                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64057.432432                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75333.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59938.311688                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 59062.500000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 58597.583643                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58437.500000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        57250                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61358.778626                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56542.817680                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62510.416667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75333.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data        58750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59938.311688                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data        66225                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 59062.500000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 57653.846154                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59138.266069                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56542.817680                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62510.416667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75333.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data        58750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59938.311688                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data        66225                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 59062.500000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 57653.846154                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59138.266069                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.toL2Bus.throughput                  1921108681                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq               2758                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp              2757                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             275                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            275                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              413                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             413                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1225                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          584                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          994                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          361                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          980                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          365                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          986                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          371                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  5866                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39168                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11136                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        31808                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        31360                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        31552                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total             149696                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus                149696                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus           53248                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy            1733986                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              1.6                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy           2820249                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             2.7                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy           1469763                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             1.4                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           2240244                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             2.1                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy           1184253                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             1.1                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy           2220245                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             2.1                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy           1188993                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             1.1                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           2220246                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             2.1                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy           1196995                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             1.1                       # Layer utilization (%)
system.cpu0.branchPred.lookups                  81365                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            78481                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1187                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               78090                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                  75342                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            96.480983                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                    733                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          211279                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             20058                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        480743                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      81365                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             76075                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       164045                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   2674                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1880                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     7123                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  658                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            187323                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.566385                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.225399                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   30153     16.10%     16.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   77599     41.43%     57.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     823      0.44%     57.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                    1078      0.58%     58.54% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     624      0.33%     58.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   72927     38.93%     97.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     691      0.37%     98.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     437      0.23%     98.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2991      1.60%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              187323                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.385107                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.275394                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   15731                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                17849                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   151731                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  675                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  1337                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                468882                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  1337                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   16349                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                   2025                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         14605                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   151742                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                 1265                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                465427                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                    17                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                    18                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents                   756                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands             318792                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups               928161                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          701504                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               304835                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   13957                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               896                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           905                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     4588                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              148468                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              75131                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            72391                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           72142                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    389496                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                964                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   386182                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued               23                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          12213                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined        11099                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           405                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       187323                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.061583                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.125394                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              33109     17.67%     17.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4301      2.30%     19.97% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              73576     39.28%     59.25% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              73130     39.04%     98.29% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1662      0.89%     99.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                894      0.48%     99.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                408      0.22%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                171      0.09%     99.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 72      0.04%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         187323                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     97     34.15%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     34.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    84     29.58%     63.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  103     36.27%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               163788     42.41%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.41% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              147930     38.31%     80.72% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              74464     19.28%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                386182                       # Type of FU issued
system.cpu0.iq.rate                          1.827830                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        284                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000735                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads            959994                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           402726                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       384333                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                386466                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           71762                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2461                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1621                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           12                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  1337                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                   1986                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   48                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             463277                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              160                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               148468                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               75131                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               843                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    43                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                   10                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           323                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1099                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1422                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               385174                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               147630                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1008                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        72817                       # number of nop insts executed
system.cpu0.iew.exec_refs                      221956                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   76403                       # Number of branches executed
system.cpu0.iew.exec_stores                     74326                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.823059                       # Inst execution rate
system.cpu0.iew.wb_sent                        384701                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       384333                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   227933                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   231165                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.819078                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.986019                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts          13622                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1187                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       184699                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.434252                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.147591                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        33306     18.03%     18.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        75499     40.88%     58.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2011      1.09%     60.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          643      0.35%     60.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          527      0.29%     60.63% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        71457     38.69%     99.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          519      0.28%     99.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          249      0.13%     99.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          488      0.26%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       184699                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              449604                       # Number of instructions committed
system.cpu0.commit.committedOps                449604                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        219517                       # Number of memory references committed
system.cpu0.commit.loads                       146007                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     75397                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   303166                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass        72129     16.04%     16.04% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu          157874     35.11%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.16% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead         146091     32.49%     83.65% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite         73510     16.35%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total           449604                       # Class of committed instruction
system.cpu0.commit.bw_lim_events                  488                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      646276                       # The number of ROB reads
system.cpu0.rob.rob_writes                     929096                       # The number of ROB writes
system.cpu0.timesIdled                            317                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          23956                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     377391                       # Number of Instructions Simulated
system.cpu0.committedOps                       377391                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              0.559841                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.559841                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.786221                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.786221                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  688854                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 310766                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 223843                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.tags.replacements              322                       # number of replacements
system.cpu0.icache.tags.tagsinuse          240.566848                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs               6326                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              612                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.336601                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   240.566848                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.469857                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.469857                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          290                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.566406                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses             7735                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses            7735                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst         6326                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           6326                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         6326                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            6326                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         6326                       # number of overall hits
system.cpu0.icache.overall_hits::total           6326                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          797                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          797                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          797                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           797                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          797                       # number of overall misses
system.cpu0.icache.overall_misses::total          797                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     36681496                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     36681496                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     36681496                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     36681496                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     36681496                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     36681496                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         7123                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         7123                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         7123                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         7123                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         7123                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         7123                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.111891                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.111891                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.111891                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.111891                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.111891                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.111891                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46024.461731                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 46024.461731                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46024.461731                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 46024.461731                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46024.461731                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 46024.461731                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs           22                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs           22                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          184                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          184                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          184                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          184                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          184                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          184                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          613                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          613                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          613                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          613                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          613                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          613                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     28176251                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     28176251                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     28176251                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     28176251                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     28176251                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     28176251                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086059                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.086059                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086059                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.086059                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086059                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.086059                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45964.520392                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45964.520392                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45964.520392                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 45964.520392                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45964.520392                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 45964.520392                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          141.515257                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs             148145                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              170                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs           871.441176                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.515257                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.276397                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.276397                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.328125                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           597526                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          597526                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data        75309                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          75309                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        72924                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         72924                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           20                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             20                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       148233                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          148233                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       148233                       # number of overall hits
system.cpu0.dcache.overall_hits::total         148233                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          484                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          484                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          544                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          544                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           22                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           22                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1028                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1028                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1028                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1028                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     15258131                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     15258131                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     32871763                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     32871763                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       427750                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       427750                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     48129894                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     48129894                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     48129894                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     48129894                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        75793                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        75793                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        73468                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        73468                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       149261                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       149261                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       149261                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       149261                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006386                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.006386                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007405                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007405                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.523810                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.523810                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006887                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006887                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006887                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006887                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31525.064050                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 31525.064050                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60426.034926                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 60426.034926                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19443.181818                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 19443.181818                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46818.963035                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 46818.963035                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46818.963035                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 46818.963035                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          754                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               27                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    27.925926                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          301                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          301                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          365                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          365                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          666                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          666                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          666                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          666                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          183                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          183                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          179                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          179                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           22                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           22                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          362                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          362                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6274260                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6274260                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7393227                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7393227                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       382250                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       382250                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     13667487                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     13667487                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     13667487                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     13667487                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002414                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002414                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002436                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002436                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.523810                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.523810                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002425                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002425                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002425                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002425                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34285.573770                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34285.573770                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41302.944134                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41302.944134                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        17375                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        17375                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37755.488950                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37755.488950                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37755.488950                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37755.488950                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                  54588                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            51200                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             1286                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               47257                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                  46317                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            98.010877                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                    875                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu1.numCycles                          167979                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             29917                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        303462                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      54588                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             47192                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       126841                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   2730                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         7060                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles         1096                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    21062                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  421                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            166282                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.824984                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.191628                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   60365     36.30%     36.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   53424     32.13%     68.43% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    6309      3.79%     72.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3483      2.09%     74.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                    1022      0.61%     74.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   35711     21.48%     96.41% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1327      0.80%     97.21% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     762      0.46%     97.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3879      2.33%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              166282                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.324969                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.806547                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   17455                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                52641                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    84496                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 3265                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  1365                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                289136                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  1365                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   18178                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  24205                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         12371                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    85331                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                17772                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                285586                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                 15350                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                    25                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands             200979                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               548958                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          426905                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               186309                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   14670                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1186                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1247                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    22653                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               80668                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              38514                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            38418                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           33330                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    237514                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               6089                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   238789                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               33                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          12748                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        11558                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           612                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       166282                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.436048                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.378738                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              63923     38.44%     38.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              20825     12.52%     50.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              37813     22.74%     73.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              37389     22.49%     96.19% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3420      2.06%     98.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1614      0.97%     99.22% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                862      0.52%     99.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                239      0.14%     99.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                197      0.12%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         166282                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     89     25.65%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.65% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    49     14.12%     39.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  209     60.23%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               116312     48.71%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.71% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               84679     35.46%     84.17% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              37798     15.83%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                238789                       # Type of FU issued
system.cpu1.iq.rate                          1.421541                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        347                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001453                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            644240                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           256392                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       237045                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                239136                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           33095                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2693                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           41                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1647                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  1365                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   6579                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   55                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             282823                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              167                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                80668                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               38514                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1105                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    37                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            41                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           470                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect         1037                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1507                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               237631                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                79596                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1158                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        39220                       # number of nop insts executed
system.cpu1.iew.exec_refs                      117284                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   48640                       # Number of branches executed
system.cpu1.iew.exec_stores                     37688                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.414647                       # Inst execution rate
system.cpu1.iew.wb_sent                        237349                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       237045                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   134973                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   141559                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.411159                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.953475                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts          14310                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           5477                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1286                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       156616                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.714129                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.075319                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        61979     39.57%     39.57% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        45369     28.97%     68.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         5243      3.35%     71.89% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         6285      4.01%     75.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1549      0.99%     76.89% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        33128     21.15%     98.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          818      0.52%     98.57% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7          954      0.61%     99.18% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8         1291      0.82%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       156616                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              268460                       # Number of instructions committed
system.cpu1.commit.committedOps                268460                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        114842                       # Number of memory references committed
system.cpu1.commit.loads                        77975                       # Number of loads committed
system.cpu1.commit.membars                       4761                       # Number of memory barriers committed
system.cpu1.commit.branches                     47591                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   184553                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass        38379     14.30%     14.30% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu          110478     41.15%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.45% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead          82736     30.82%     86.27% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite         36867     13.73%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total           268460                       # Class of committed instruction
system.cpu1.commit.bw_lim_events                 1291                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      437508                       # The number of ROB reads
system.cpu1.rob.rob_writes                     568153                       # The number of ROB writes
system.cpu1.timesIdled                            207                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           1697                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       43298                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     225320                       # Number of Instructions Simulated
system.cpu1.committedOps                       225320                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              0.745513                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.745513                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.341358                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.341358                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  411671                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 192443                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 118908                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.icache.tags.replacements              388                       # number of replacements
system.cpu1.icache.tags.tagsinuse           78.688259                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs              20497                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              497                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            41.241449                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    78.688259                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.153688                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.153688                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          109                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.212891                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses            21559                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses           21559                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst        20497                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          20497                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        20497                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           20497                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        20497                       # number of overall hits
system.cpu1.icache.overall_hits::total          20497                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          565                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          565                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          565                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           565                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          565                       # number of overall misses
system.cpu1.icache.overall_misses::total          565                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      8463744                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      8463744                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      8463744                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      8463744                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      8463744                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      8463744                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        21062                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        21062                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        21062                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        21062                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        21062                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        21062                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.026826                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.026826                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.026826                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.026826                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.026826                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.026826                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14980.077876                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14980.077876                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14980.077876                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14980.077876                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14980.077876                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14980.077876                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            2                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs            2                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           68                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           68                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           68                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          497                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          497                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          497                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          497                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          497                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          497                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      6616756                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      6616756                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      6616756                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      6616756                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      6616756                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      6616756                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023597                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023597                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023597                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.023597                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023597                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.023597                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13313.392354                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13313.392354                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13313.392354                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13313.392354                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13313.392354                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13313.392354                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           24.399537                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              43036                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs                 1484                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    24.399537                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.047655                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.047655                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           333666                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          333666                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data        46059                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          46059                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        36657                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         36657                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        82716                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           82716                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        82716                       # number of overall hits
system.cpu1.dcache.overall_hits::total          82716                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          427                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          427                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          140                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           57                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          567                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           567                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          567                       # number of overall misses
system.cpu1.dcache.overall_misses::total          567                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      5717104                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      5717104                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2840511                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      2840511                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       466006                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       466006                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      8557615                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      8557615                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      8557615                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      8557615                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        46486                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        46486                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        36797                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        36797                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        83283                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        83283                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        83283                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        83283                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009186                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.009186                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003805                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.003805                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.814286                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.814286                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006808                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.006808                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006808                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.006808                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13389.002342                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13389.002342                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20289.364286                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20289.364286                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  8175.543860                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  8175.543860                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15092.795414                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15092.795414                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15092.795414                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15092.795414                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          269                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          269                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           35                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          304                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          304                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          304                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          304                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          158                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          105                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           57                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          263                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          263                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          263                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          263                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1020514                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1020514                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1289239                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1289239                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       351994                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       351994                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2309753                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      2309753                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2309753                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      2309753                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003399                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003399                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002853                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002853                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.814286                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.814286                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003158                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.003158                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003158                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.003158                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  6458.949367                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  6458.949367                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12278.466667                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12278.466667                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  6175.333333                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  6175.333333                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  8782.330798                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total  8782.330798                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  8782.330798                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total  8782.330798                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.branchPred.lookups                  50591                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            46824                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             1298                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               43166                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                  41772                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            96.770606                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                    904                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                          167617                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             31796                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        277876                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      50591                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             42676                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       121192                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   2752                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         7062                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1110                       # Number of stall cycles due to pending traps
system.cpu2.fetch.IcacheWaitRetryStallCycles            3                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                    22366                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  459                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            162543                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.709554                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.176994                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   64711     39.81%     39.81% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   49634     30.54%     70.35% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    6798      4.18%     74.53% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3442      2.12%     76.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     952      0.59%     77.23% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   30771     18.93%     96.16% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1187      0.73%     96.89% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     849      0.52%     97.42% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    4199      2.58%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              162543                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.301825                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.657803                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   17997                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                57677                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    74910                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 3521                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  1376                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                262355                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  1376                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   18679                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  27128                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         12799                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    76466                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                19033                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                259235                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                 17033                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                    25                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents               6                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands             182575                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               494395                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          386046                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               167620                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   14955                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1169                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1235                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    23554                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               71776                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              33725                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            34298                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           28594                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    214929                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               6621                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   216336                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               47                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          13228                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        12296                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           674                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       162543                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.330946                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.384454                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              68368     42.06%     42.06% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              22285     13.71%     55.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              32950     20.27%     76.04% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              32546     20.02%     96.07% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3459      2.13%     98.19% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1594      0.98%     99.17% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                888      0.55%     99.72% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                245      0.15%     99.87% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                208      0.13%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         162543                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     90     24.93%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     24.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    62     17.17%     42.11% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  209     57.89%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               107190     49.55%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.55% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               76124     35.19%     84.74% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              33022     15.26%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                216336                       # Type of FU issued
system.cpu2.iq.rate                          1.290657                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        361                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001669                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            595623                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           234822                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       214628                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                216697                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           28314                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         2909                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           44                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1648                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  1376                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                   7567                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   67                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             256538                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              192                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                71776                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               33725                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1099                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    39                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            44                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           464                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect         1069                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1533                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               215226                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                70571                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             1110                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        34988                       # number of nop insts executed
system.cpu2.iew.exec_refs                      103485                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   44292                       # Number of branches executed
system.cpu2.iew.exec_stores                     32914                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.284034                       # Inst execution rate
system.cpu2.iew.wb_sent                        214935                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       214628                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   121102                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   127756                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.280467                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.947916                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts          14883                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           5947                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1298                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       152800                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.581165                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.037167                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        66891     43.78%     43.78% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        41018     26.84%     70.62% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         5166      3.38%     74.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         6776      4.43%     78.44% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1516      0.99%     79.43% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        28304     18.52%     97.95% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          869      0.57%     98.52% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7          954      0.62%     99.15% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8         1306      0.85%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       152800                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              241602                       # Number of instructions committed
system.cpu2.commit.committedOps                241602                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        100944                       # Number of memory references committed
system.cpu2.commit.loads                        68867                       # Number of loads committed
system.cpu2.commit.membars                       5232                       # Number of memory barriers committed
system.cpu2.commit.branches                     43270                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   166336                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        34059     14.10%     14.10% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu          101367     41.96%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult              0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead          74099     30.67%     86.72% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite         32077     13.28%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total           241602                       # Class of committed instruction
system.cpu2.commit.bw_lim_events                 1306                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      407392                       # The number of ROB reads
system.cpu2.rob.rob_writes                     515662                       # The number of ROB writes
system.cpu2.timesIdled                            212                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           5074                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       43660                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     202311                       # Number of Instructions Simulated
system.cpu2.committedOps                       202311                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              0.828512                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.828512                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.206984                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.206984                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  370344                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 173891                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 105089                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.icache.tags.replacements              378                       # number of replacements
system.cpu2.icache.tags.tagsinuse           84.908829                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs              21796                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              490                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs            44.481633                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    84.908829                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.165838                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.165838                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024          112                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.218750                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses            22856                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses           22856                       # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst        21796                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          21796                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        21796                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           21796                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        21796                       # number of overall hits
system.cpu2.icache.overall_hits::total          21796                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          570                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          570                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          570                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           570                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          570                       # number of overall misses
system.cpu2.icache.overall_misses::total          570                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     13348494                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     13348494                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     13348494                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     13348494                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     13348494                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     13348494                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        22366                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        22366                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        22366                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        22366                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        22366                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        22366                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.025485                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.025485                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.025485                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.025485                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.025485                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.025485                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23418.410526                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 23418.410526                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23418.410526                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 23418.410526                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23418.410526                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 23418.410526                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs          128                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                3                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs    42.666667                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           80                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           80                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           80                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           80                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          490                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          490                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          490                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          490                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          490                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          490                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst     10380255                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total     10380255                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst     10380255                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total     10380255                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst     10380255                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total     10380255                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021908                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021908                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021908                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.021908                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021908                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.021908                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21184.193878                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21184.193878                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21184.193878                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 21184.193878                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21184.193878                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 21184.193878                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           25.893249                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              38186                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1363.785714                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    25.893249                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.050573                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.050573                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           297518                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          297518                       # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data        41817                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          41817                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        31862                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         31862                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           14                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        73679                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           73679                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        73679                       # number of overall hits
system.cpu2.dcache.overall_hits::total          73679                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          422                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          422                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          146                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          146                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           55                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          568                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           568                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          568                       # number of overall misses
system.cpu2.dcache.overall_misses::total          568                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      7291559                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      7291559                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3658011                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      3658011                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       499506                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       499506                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data     10949570                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total     10949570                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data     10949570                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total     10949570                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        42239                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        42239                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        32008                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        32008                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        74247                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        74247                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        74247                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        74247                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.009991                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.009991                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004561                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.004561                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.797101                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.797101                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007650                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.007650                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007650                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.007650                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17278.575829                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 17278.575829                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25054.869863                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 25054.869863                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  9081.927273                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  9081.927273                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19277.411972                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 19277.411972                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19277.411972                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 19277.411972                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          261                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          261                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           40                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           40                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          301                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          301                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          301                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          301                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          161                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          106                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           55                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          267                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1541774                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1541774                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1509739                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1509739                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       389494                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       389494                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3051513                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      3051513                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3051513                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      3051513                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003812                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003812                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003312                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003312                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.797101                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.797101                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003596                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.003596                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003596                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.003596                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9576.236025                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9576.236025                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14242.820755                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14242.820755                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  7081.709091                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  7081.709091                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11428.887640                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11428.887640                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11428.887640                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11428.887640                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.branchPred.lookups                  48151                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            44685                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             1287                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               41038                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                  39836                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            97.071007                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                    888                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
system.cpu3.numCycles                          167273                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             33692                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        260486                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      48151                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             40724                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                       122974                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   2726                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         7060                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles         1076                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    24907                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  418                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            166168                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.567606                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.102870                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   71279     42.90%     42.90% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   48852     29.40%     72.29% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    8282      4.98%     77.28% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3511      2.11%     79.39% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                    1059      0.64%     80.03% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   27347     16.46%     96.49% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1190      0.72%     97.20% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     758      0.46%     97.66% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3890      2.34%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              166168                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.287859                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.557251                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   17558                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                68128                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    67891                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 4168                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  1363                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                246104                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  1363                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   18233                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  33368                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         12463                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    69060                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                24621                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                242881                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                 21589                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                    28                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands             169259                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               456177                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          357242                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               154687                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   14572                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1184                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1245                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    29195                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               65863                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              30140                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            31966                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           25009                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    199372                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               7958                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   202308                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued               33                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          12859                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        11887                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           683                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       166168                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.217491                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.364227                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              75148     45.22%     45.22% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              26256     15.80%     61.02% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              29417     17.70%     78.73% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              29010     17.46%     96.19% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3447      2.07%     98.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1582      0.95%     99.21% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                873      0.53%     99.74% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                228      0.14%     99.88% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                207      0.12%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         166168                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     93     25.83%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.83% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    58     16.11%     41.94% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  209     58.06%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               101290     50.07%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.07% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               71575     35.38%     85.45% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              29443     14.55%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                202308                       # Type of FU issued
system.cpu3.iq.rate                          1.209448                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        360                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001779                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            571177                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           220229                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       200600                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                202668                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           24749                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2800                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1627                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  1363                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                   8604                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   61                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             240098                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              201                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                65863                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               30140                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1100                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    33                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            40                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           473                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect         1038                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1511                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               201185                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                64698                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1123                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        32768                       # number of nop insts executed
system.cpu3.iew.exec_refs                       94032                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   42068                       # Number of branches executed
system.cpu3.iew.exec_stores                     29334                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.202734                       # Inst execution rate
system.cpu3.iew.wb_sent                        200904                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       200600                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   111689                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   118263                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.199237                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.944412                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts          14520                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           7275                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1287                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       156480                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.441238                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.976154                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        74989     47.92%     47.92% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        38816     24.81%     72.73% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         5199      3.32%     76.05% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         8093      5.17%     81.22% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1536      0.98%     82.20% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        24757     15.82%     98.03% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          830      0.53%     98.56% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7          957      0.61%     99.17% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8         1303      0.83%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       156480                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              225525                       # Number of instructions committed
system.cpu3.commit.committedOps                225525                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                         91576                       # Number of memory references committed
system.cpu3.commit.loads                        63063                       # Number of loads committed
system.cpu3.commit.membars                       6559                       # Number of memory barriers committed
system.cpu3.commit.branches                     41035                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   154730                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass        31823     14.11%     14.11% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu           95567     42.38%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.49% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead          69622     30.87%     87.36% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite         28513     12.64%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total           225525                       # Class of committed instruction
system.cpu3.commit.bw_lim_events                 1303                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      394635                       # The number of ROB reads
system.cpu3.rob.rob_writes                     482728                       # The number of ROB writes
system.cpu3.timesIdled                            203                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1105                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       44004                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     187143                       # Number of Instructions Simulated
system.cpu3.committedOps                       187143                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              0.893825                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.893825                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.118788                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.118788                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  341840                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 160726                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                  95629                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.icache.tags.replacements              380                       # number of replacements
system.cpu3.icache.tags.tagsinuse           77.789470                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs              24352                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              493                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs            49.395538                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    77.789470                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.151933                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.151933                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024          113                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.220703                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses            25400                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses           25400                       # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst        24352                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          24352                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        24352                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           24352                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        24352                       # number of overall hits
system.cpu3.icache.overall_hits::total          24352                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          555                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          555                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          555                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           555                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          555                       # number of overall misses
system.cpu3.icache.overall_misses::total          555                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7324995                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      7324995                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      7324995                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      7324995                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      7324995                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      7324995                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        24907                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        24907                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        24907                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        24907                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        24907                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        24907                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.022283                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.022283                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.022283                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.022283                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.022283                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.022283                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13198.189189                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13198.189189                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13198.189189                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13198.189189                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13198.189189                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13198.189189                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           62                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           62                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           62                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           62                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           62                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          493                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          493                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          493                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          493                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          493                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          493                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5824754                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      5824754                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5824754                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      5824754                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5824754                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      5824754                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.019794                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.019794                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.019794                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.019794                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.019794                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.019794                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11814.916836                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11814.916836                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11814.916836                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 11814.916836                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11814.916836                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 11814.916836                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           23.433083                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              34557                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs          1234.178571                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    23.433083                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.045768                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.045768                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           274000                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          274000                       # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data        39491                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          39491                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        28303                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         28303                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           13                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        67794                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           67794                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        67794                       # number of overall hits
system.cpu3.dcache.overall_hits::total          67794                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          432                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          432                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          140                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           57                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          572                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           572                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          572                       # number of overall misses
system.cpu3.dcache.overall_misses::total          572                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      5736963                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      5736963                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2764512                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2764512                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       515508                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       515508                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      8501475                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      8501475                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      8501475                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      8501475                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        39923                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        39923                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        28443                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        28443                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           70                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        68366                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        68366                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        68366                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        68366                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.010821                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.010821                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004922                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.004922                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.814286                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.814286                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008367                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.008367                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008367                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.008367                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13280.006944                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 13280.006944                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19746.514286                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 19746.514286                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data         9044                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total         9044                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14862.718531                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 14862.718531                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14862.718531                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 14862.718531                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          269                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          269                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           33                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          302                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          302                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          302                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          302                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          163                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          270                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          270                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1168525                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1168525                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1299988                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1299988                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       401492                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       401492                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2468513                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2468513                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2468513                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2468513                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004083                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004083                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003762                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003762                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.814286                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.814286                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003949                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003949                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003949                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003949                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  7168.865031                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  7168.865031                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12149.420561                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12149.420561                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  7043.719298                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  7043.719298                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9142.640741                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9142.640741                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9142.640741                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9142.640741                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------