path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000106                       # Number of seconds simulated
sim_ticks                                   105801500                       # Number of ticks simulated
final_tick                                  105801500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  99938                       # Simulator instruction rate (inst/s)
host_op_rate                                    99937                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               10207562                       # Simulator tick rate (ticks/s)
host_mem_usage                                 247464                       # Number of bytes of host memory used
host_seconds                                    10.37                       # Real time elapsed on the host
sim_insts                                     1035849                       # Number of instructions simulated
sim_ops                                       1035849                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst            22848                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst             5120                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst              384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                42240                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        22848                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst         5120                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst          384                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          192                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           28544                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               357                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                80                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                 6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   660                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           215951570                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data           101624268                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst            48392509                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data            12098127                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst             3629438                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             7863783                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             1814719                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7863783                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               399238196                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      215951570                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst       48392509                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst        3629438                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        1814719                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          269788236                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          215951570                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data          101624268                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst           48392509                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data           12098127                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst            3629438                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            7863783                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            1814719                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7863783                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              399238196                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           661                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                            978                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                        42240                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                  42240                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                 71                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                    65                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                    39                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                    74                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                    69                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                    58                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                    38                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                    16                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                    21                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                    30                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                    14                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                   30                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                   13                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                   37                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                   60                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                   74                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                   23                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                       105773500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                     661                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                      0                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                   71                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                       377                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       205                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        59                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                        4077160                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                  20692160                       # Sum of mem lat for all requests
system.physmem.totBusLat                      3305000                       # Total cycles spent in databus access
system.physmem.totBankLat                    13310000                       # Total cycles spent in bank access
system.physmem.avgQLat                        6168.17                       # Average queueing delay per request
system.physmem.avgBankLat                    20136.16                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  31304.33                       # Average memory access latency
system.physmem.avgRdBW                         399.24                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                 399.24                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.12                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.20                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                        465                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   70.35                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       160020.42                       # Average gap between requests
system.cpu0.branchPred.lookups                  82232                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            80005                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1236                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               79512                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                  77444                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            97.399135                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                    525                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               132                       # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          211604                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             16980                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        488068                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      82232                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             77969                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       160105                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3869                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 13032                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1378                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     5906                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  485                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            193984                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.516022                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.216359                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   33879     17.46%     17.46% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   79263     40.86%     58.33% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     605      0.31%     58.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     997      0.51%     59.15% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     467      0.24%     59.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   75310     38.82%     98.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     571      0.29%     98.51% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     376      0.19%     98.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2516      1.30%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              193984                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.388613                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.306516                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   17628                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                14487                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   159104                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  281                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2484                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                484973                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2484                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18279                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                    710                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         13181                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   158767                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  563                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                482144                       # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents                  156                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands             329947                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups               961518                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          961518                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               316491                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   13456                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               888                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           909                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     3585                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              154112                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              77863                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            75108                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           74923                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    403093                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                921                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   400275                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued               92                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          11012                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined         9891                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           362                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       193984                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.063443                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.093968                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              33040     17.03%     17.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4899      2.53%     19.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              76941     39.66%     59.22% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              76443     39.41%     98.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1604      0.83%     99.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                703      0.36%     99.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                261      0.13%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 76      0.04%     99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 17      0.01%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         193984                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     51     22.67%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     22.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    62     27.56%     50.22% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  112     49.78%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               169361     42.31%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.31% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              153636     38.38%     80.69% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              77278     19.31%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                400275                       # Type of FU issued
system.cpu0.iq.rate                          1.891623                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        225                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000562                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads            994851                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           415081                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       398443                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                400500                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           74634                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2277                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           55                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1439                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked            7                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2484                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                    441                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   37                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             479665                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              304                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               154112                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               77863                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               809                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            55                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           346                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1112                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1458                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               399178                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               153293                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1097                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        75651                       # number of nop insts executed
system.cpu0.iew.exec_refs                      230462                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   79264                       # Number of branches executed
system.cpu0.iew.exec_stores                     77169                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.886439                       # Inst execution rate
system.cpu0.iew.wb_sent                        398782                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       398443                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   236156                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   238721                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.882965                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.989255                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts          12542                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1236                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       191500                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.439102                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.136121                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        33551     17.52%     17.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        78896     41.20%     58.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2340      1.22%     59.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          696      0.36%     60.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          545      0.28%     60.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        74448     38.88%     99.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          466      0.24%     99.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          256      0.13%     99.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          302      0.16%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       191500                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              467088                       # Number of instructions committed
system.cpu0.commit.committedOps                467088                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        228259                       # Number of memory references committed
system.cpu0.commit.loads                       151835                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     78311                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   314822                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events                  302                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      669667                       # The number of ROB reads
system.cpu0.rob.rob_writes                     961765                       # The number of ROB writes
system.cpu0.timesIdled                            319                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          17620                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     391961                       # Number of Instructions Simulated
system.cpu0.committedOps                       391961                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total               391961                       # Number of Instructions Simulated
system.cpu0.cpi                              0.539860                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.539860                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.852333                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.852333                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  714059                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 321926                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 232286                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.replacements                   298                       # number of replacements
system.cpu0.icache.tagsinuse               245.557795                       # Cycle average of tags in use
system.cpu0.icache.total_refs                    5162                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                   589                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  8.764007                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   245.557795                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.479605                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.479605                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst         5162                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           5162                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         5162                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            5162                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         5162                       # number of overall hits
system.cpu0.icache.overall_hits::total           5162                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          744                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          744                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          744                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           744                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          744                       # number of overall misses
system.cpu0.icache.overall_misses::total          744                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     26547500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     26547500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     26547500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     26547500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     26547500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     26547500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         5906                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         5906                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         5906                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         5906                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         5906                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         5906                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125974                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.125974                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125974                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.125974                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125974                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.125974                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35682.123656                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 35682.123656                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35682.123656                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 35682.123656                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35682.123656                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 35682.123656                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          154                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          154                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          154                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          154                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          154                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          154                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          590                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          590                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          590                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          590                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          590                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          590                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     21154500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     21154500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     21154500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     21154500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     21154500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     21154500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.099898                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.099898                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.099898                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.099898                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.099898                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.099898                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35855.084746                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35855.084746                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35855.084746                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 35855.084746                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35855.084746                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 35855.084746                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                     2                       # number of replacements
system.cpu0.dcache.tagsinuse               143.429999                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                  153854                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                905.023529                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   143.429999                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.280137                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.280137                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data        78105                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          78105                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        75839                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         75839                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       153944                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          153944                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       153944                       # number of overall hits
system.cpu0.dcache.overall_hits::total         153944                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          475                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          475                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          543                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          543                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data         1018                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total          1018                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data         1018                       # number of overall misses
system.cpu0.dcache.overall_misses::total         1018                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     11909000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     11909000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     24675495                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     24675495                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       605500                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       605500                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     36584495                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     36584495                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     36584495                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     36584495                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        78580                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        78580                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        76382                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        76382                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       154962                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       154962                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       154962                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       154962                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006045                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.006045                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007109                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007109                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006569                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006569                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006569                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006569                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25071.578947                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 25071.578947                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45442.900552                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45442.900552                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28833.333333                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 28833.333333                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35937.617878                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 35937.617878                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35937.617878                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 35937.617878                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          184                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               14                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.142857                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          287                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          287                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          373                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          373                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          660                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          660                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          660                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          660                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          188                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          188                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          170                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          170                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          358                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          358                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          358                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          358                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      5409500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      5409500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      5718500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      5718500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       563500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       563500                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11128000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     11128000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11128000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     11128000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002392                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002392                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002226                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002226                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002310                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002310                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002310                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002310                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28773.936170                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28773.936170                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33638.235294                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33638.235294                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26833.333333                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26833.333333                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31083.798883                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31083.798883                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31083.798883                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31083.798883                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                  58098                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            55415                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             1271                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               51986                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                  51313                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            98.705421                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                    648                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
system.cpu1.numCycles                          174790                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             24349                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        331605                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      58098                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             51961                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       112635                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   3690                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 23829                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         6397                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles          795                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    15584                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  268                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            170350                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.946610                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.217345                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   57715     33.88%     33.88% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   56197     32.99%     66.87% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    4087      2.40%     69.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3199      1.88%     71.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     641      0.38%     71.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   43239     25.38%     96.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1271      0.75%     97.65% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     756      0.44%     98.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3245      1.90%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              170350                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.332387                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.897162                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   27574                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                22245                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                   108585                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 3208                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2341                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                328108                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2341                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   28283                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                   9804                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         11660                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                   105676                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                 6189                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                325946                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                     3                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                   43                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands             230320                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               636644                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          636644                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               217343                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   12977                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1083                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1203                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                     8803                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               95013                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              46485                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            44692                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           41453                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    273191                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               4270                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   273407                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               80                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          10726                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        10333                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           504                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       170350                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.604972                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.301874                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              54964     32.27%     32.27% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              16569      9.73%     41.99% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              46599     27.35%     69.35% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              47325     27.78%     97.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3328      1.95%     99.08% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1208      0.71%     99.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                245      0.14%     99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 59      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         170350                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     17      5.69%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      5.69% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    72     24.08%     29.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  210     70.23%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               130168     47.61%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.61% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               97443     35.64%     83.25% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              45796     16.75%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                273407                       # Type of FU issued
system.cpu1.iq.rate                          1.564203                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        299                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001094                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            717543                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           288232                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       271609                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                273706                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           41212                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2369                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           45                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1440                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2341                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                   1392                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   66                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             323061                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              370                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                95013                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               46485                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1042                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    67                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            45                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           456                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect          928                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1384                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               272209                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                94088                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1198                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        45600                       # number of nop insts executed
system.cpu1.iew.exec_refs                      139806                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   54914                       # Number of branches executed
system.cpu1.iew.exec_stores                     45718                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.557349                       # Inst execution rate
system.cpu1.iew.wb_sent                        271881                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       271609                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   156621                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   161297                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.553916                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.971010                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts          12317                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           3766                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1271                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       161612                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.922772                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.097017                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        52280     32.35%     32.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        52948     32.76%     65.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         6058      3.75%     68.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         4700      2.91%     71.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1571      0.97%     72.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        41692     25.80%     98.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          528      0.33%     98.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1013      0.63%     99.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          822      0.51%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       161612                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              310743                       # Number of instructions committed
system.cpu1.commit.committedOps                310743                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        137689                       # Number of memory references committed
system.cpu1.commit.loads                        92644                       # Number of loads committed
system.cpu1.commit.membars                       3055                       # Number of memory barriers committed
system.cpu1.commit.branches                     54067                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   213879                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events                  822                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      483263                       # The number of ROB reads
system.cpu1.rob.rob_writes                     648465                       # The number of ROB writes
system.cpu1.timesIdled                            226                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           4440                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       36812                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     262828                       # Number of Instructions Simulated
system.cpu1.committedOps                       262828                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total               262828                       # Number of Instructions Simulated
system.cpu1.cpi                              0.665036                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.665036                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.503679                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.503679                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  478110                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 222397                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 141404                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.icache.replacements                   317                       # number of replacements
system.cpu1.icache.tagsinuse                85.239071                       # Cycle average of tags in use
system.cpu1.icache.total_refs                   15102                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                   425                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 35.534118                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst    85.239071                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.166483                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.166483                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst        15102                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          15102                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        15102                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           15102                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        15102                       # number of overall hits
system.cpu1.icache.overall_hits::total          15102                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          482                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          482                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          482                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           482                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          482                       # number of overall misses
system.cpu1.icache.overall_misses::total          482                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     10460500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total     10460500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst     10460500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total     10460500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst     10460500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total     10460500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        15584                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        15584                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        15584                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        15584                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        15584                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        15584                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030929                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.030929                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030929                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.030929                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030929                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.030929                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21702.282158                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 21702.282158                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21702.282158                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 21702.282158                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21702.282158                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 21702.282158                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs           44                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs           44                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           57                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           57                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           57                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           57                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           57                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           57                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          425                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          425                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          425                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          425                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          425                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          425                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      8302000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      8302000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      8302000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      8302000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      8302000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      8302000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027272                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027272                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027272                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.027272                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027272                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.027272                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19534.117647                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19534.117647                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19534.117647                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 19534.117647                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19534.117647                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 19534.117647                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                     0                       # number of replacements
system.cpu1.dcache.tagsinuse                27.071497                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                   51063                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs               1823.678571                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data    27.071497                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.052874                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.052874                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data        52421                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          52421                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        44839                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         44839                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           11                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        97260                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           97260                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        97260                       # number of overall hits
system.cpu1.dcache.overall_hits::total          97260                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          438                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          438                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          141                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          141                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           54                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          579                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           579                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          579                       # number of overall misses
system.cpu1.dcache.overall_misses::total          579                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      8533500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      8533500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3160000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3160000                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       510000                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       510000                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data     11693500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total     11693500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data     11693500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total     11693500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        52859                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        52859                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        44980                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        44980                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           65                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           65                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        97839                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        97839                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        97839                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        97839                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008286                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.008286                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003135                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.003135                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.830769                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.830769                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005918                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.005918                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005918                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.005918                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19482.876712                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19482.876712                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22411.347518                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22411.347518                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  9444.444444                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  9444.444444                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20196.027634                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20196.027634                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20196.027634                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20196.027634                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          286                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          286                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           34                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          320                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          320                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          320                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          320                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          152                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          152                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           54                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          259                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          259                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          259                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          259                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1798500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1798500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1487000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1487000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       402000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       402000                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3285500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      3285500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3285500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      3285500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.002876                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.002876                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002379                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002379                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.830769                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.830769                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.002647                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.002647                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.002647                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.002647                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11832.236842                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11832.236842                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13897.196262                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13897.196262                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  7444.444444                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  7444.444444                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12685.328185                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12685.328185                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12685.328185                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12685.328185                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.branchPred.lookups                  45099                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            42400                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             1262                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               39025                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                  38304                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            98.152466                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                    646                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                          174459                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             32669                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        244823                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      45099                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             38950                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                        90929                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   3703                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 39674                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         6379                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles          712                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    24269                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  265                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            172730                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.417374                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.028063                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   81801     47.36%     47.36% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   47495     27.50%     74.85% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    8404      4.87%     79.72% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3201      1.85%     81.57% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     675      0.39%     81.96% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   25947     15.02%     96.99% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1207      0.70%     97.68% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     760      0.44%     98.12% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    3240      1.88%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              172730                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.258508                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.403327                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   39762                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                34129                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    82888                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 7209                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2363                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                241309                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2363                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   40462                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  21352                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         11989                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    75976                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                14209                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                239275                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                     6                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents                   36                       # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands             165256                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               446077                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          446077                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               152520                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   12736                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1091                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1215                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    16777                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               64738                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              29196                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            31698                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           24168                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    195168                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               8612                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   199473                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued               72                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          10767                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        10430                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           654                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       172730                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.154825                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.283743                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              79387     45.96%     45.96% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              29099     16.85%     62.81% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              29295     16.96%     79.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              30090     17.42%     97.19% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3300      1.91%     99.10% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1204      0.70%     99.79% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                247      0.14%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 52      0.03%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 56      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         172730                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     16      5.67%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      5.67% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    56     19.86%     25.53% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  210     74.47%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu                99688     49.98%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.98% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               71251     35.72%     85.70% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              28534     14.30%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                199473                       # Type of FU issued
system.cpu2.iq.rate                          1.143380                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        282                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001414                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            572030                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           214590                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       197726                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                199755                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           23953                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         2414                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           43                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1398                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2363                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                    870                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   45                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             236415                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              392                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                64738                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               29196                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1054                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    44                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            43                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           459                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect          913                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1372                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               198312                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                63718                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             1161                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        32635                       # number of nop insts executed
system.cpu2.iew.exec_refs                       92179                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   41831                       # Number of branches executed
system.cpu2.iew.exec_stores                     28461                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.136726                       # Inst execution rate
system.cpu2.iew.wb_sent                        197998                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       197726                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   108943                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   113613                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.133367                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.958896                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts          12414                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           7958                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1262                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       163988                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.365838                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.905647                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        80806     49.28%     49.28% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        39854     24.30%     73.58% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         6054      3.69%     77.27% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         8882      5.42%     82.69% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1574      0.96%     83.65% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        24481     14.93%     98.57% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          507      0.31%     98.88% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1010      0.62%     99.50% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          820      0.50%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       163988                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              223981                       # Number of instructions committed
system.cpu2.commit.committedOps                223981                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                         90122                       # Number of memory references committed
system.cpu2.commit.loads                        62324                       # Number of loads committed
system.cpu2.commit.membars                       7244                       # Number of memory barriers committed
system.cpu2.commit.branches                     41003                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   153248                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.bw_lim_events                  820                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      398976                       # The number of ROB reads
system.cpu2.rob.rob_writes                     475157                       # The number of ROB writes
system.cpu2.timesIdled                            219                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           1729                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       37143                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     184944                       # Number of Instructions Simulated
system.cpu2.committedOps                       184944                       # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total               184944                       # Number of Instructions Simulated
system.cpu2.cpi                              0.943307                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.943307                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.060100                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.060100                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  335090                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 157371                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                  93758                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.icache.replacements                   319                       # number of replacements
system.cpu2.icache.tagsinuse                83.416337                       # Cycle average of tags in use
system.cpu2.icache.total_refs                   23791                       # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs                   430                       # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs                 55.327907                       # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst    83.416337                       # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst     0.162923                       # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total        0.162923                       # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst        23791                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          23791                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        23791                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           23791                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        23791                       # number of overall hits
system.cpu2.icache.overall_hits::total          23791                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          478                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          478                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          478                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           478                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          478                       # number of overall misses
system.cpu2.icache.overall_misses::total          478                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      6751000                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      6751000                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      6751000                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      6751000                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      6751000                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      6751000                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        24269                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        24269                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        24269                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        24269                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        24269                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        24269                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.019696                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.019696                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.019696                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.019696                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.019696                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.019696                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14123.430962                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 14123.430962                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14123.430962                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 14123.430962                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14123.430962                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 14123.430962                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           48                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           48                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           48                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           48                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           48                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           48                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          430                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          430                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          430                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          430                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          430                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          430                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      5435000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      5435000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      5435000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      5435000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      5435000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      5435000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.017718                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.017718                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.017718                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.017718                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.017718                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.017718                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12639.534884                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12639.534884                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12639.534884                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12639.534884                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12639.534884                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12639.534884                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.replacements                     0                       # number of replacements
system.cpu2.dcache.tagsinuse                25.649065                       # Cycle average of tags in use
system.cpu2.dcache.total_refs                   33911                       # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs               1169.344828                       # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data    25.649065                       # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data     0.050096                       # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total        0.050096                       # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data        39345                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          39345                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        27592                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         27592                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           15                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        66937                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           66937                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        66937                       # number of overall hits
system.cpu2.dcache.overall_hits::total          66937                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          402                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          402                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          138                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          138                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           53                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           53                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          540                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           540                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          540                       # number of overall misses
system.cpu2.dcache.overall_misses::total          540                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5276000                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      5276000                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2759500                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2759500                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       558000                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       558000                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      8035500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      8035500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      8035500                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      8035500                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        39747                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        39747                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        27730                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        27730                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        67477                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        67477                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        67477                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        67477                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.010114                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.010114                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004977                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.004977                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.779412                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.779412                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.008003                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.008003                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.008003                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.008003                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13124.378109                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 13124.378109                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19996.376812                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 19996.376812                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10528.301887                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 10528.301887                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14880.555556                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 14880.555556                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14880.555556                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 14880.555556                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          241                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          241                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           33                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          274                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          274                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          274                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          274                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          161                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           53                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           53                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          266                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          266                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          266                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          266                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1358500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1358500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1350500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1350500                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       452000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       452000                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      2709000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      2709000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      2709000                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      2709000                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.004051                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.004051                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003787                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003787                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.779412                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.779412                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003942                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.003942                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003942                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.003942                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  8437.888199                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  8437.888199                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 12861.904762                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 12861.904762                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  8528.301887                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  8528.301887                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10184.210526                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10184.210526                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10184.210526                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10184.210526                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.branchPred.lookups                  47073                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            44334                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             1289                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               40998                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                  40129                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            97.880384                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                    665                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
system.cpu3.numCycles                          174149                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             31334                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        257802                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      47073                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             40794                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                        94093                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   3784                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 37693                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         6388                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles          691                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    23091                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  274                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            172622                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.493448                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.066617                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   78529     45.49%     45.49% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   48697     28.21%     73.70% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    7780      4.51%     78.21% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3181      1.84%     80.05% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     739      0.43%     80.48% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   28510     16.52%     97.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1109      0.64%     97.64% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     774      0.45%     98.09% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3303      1.91%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              172622                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.270303                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.480353                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   38095                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                32492                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    86590                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 6639                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2418                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                254216                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2418                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   38798                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  19631                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         12074                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    80231                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                13082                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                251848                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents                   33                       # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands             174600                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               473869                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          473869                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               161804                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   12796                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1100                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1222                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    15769                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               69165                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              31749                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            33643                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           26714                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    206536                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               7999                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   210100                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued              110                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          10964                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        10853                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           623                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       172622                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.217110                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.294923                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              76068     44.07%     44.07% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              27297     15.81%     59.88% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              31861     18.46%     78.34% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              32569     18.87%     97.20% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3286      1.90%     99.11% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1177      0.68%     99.79% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                258      0.15%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 51      0.03%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 55      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         172622                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     11      3.79%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      3.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    69     23.79%     27.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  210     72.41%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               104024     49.51%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.51% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               75016     35.70%     85.22% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              31060     14.78%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                210100                       # Type of FU issued
system.cpu3.iq.rate                          1.206438                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        290                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001380                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            593222                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           225545                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       208328                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                210390                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           26418                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2499                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           46                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1475                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2418                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                    854                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   58                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             249047                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              315                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                69165                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               31749                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1065                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    58                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            46                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           473                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect          935                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1408                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               208934                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                68077                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1166                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        34512                       # number of nop insts executed
system.cpu3.iew.exec_refs                       99056                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   43690                       # Number of branches executed
system.cpu3.iew.exec_stores                     30979                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.199743                       # Inst execution rate
system.cpu3.iew.wb_sent                        208597                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       208328                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   115832                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   120507                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.196263                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.961206                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts          12582                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           7376                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1289                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       163816                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.443357                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.942306                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        76810     46.89%     46.89% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        41800     25.52%     72.40% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6086      3.72%     76.12% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         8257      5.04%     81.16% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1545      0.94%     82.10% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        27022     16.50%     98.60% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          472      0.29%     98.89% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1012      0.62%     99.50% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          812      0.50%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       163816                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              236445                       # Number of instructions committed
system.cpu3.commit.committedOps                236445                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                         96940                       # Number of memory references committed
system.cpu3.commit.loads                        66666                       # Number of loads committed
system.cpu3.commit.membars                       6656                       # Number of memory barriers committed
system.cpu3.commit.branches                     42889                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   161946                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.bw_lim_events                  812                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      411444                       # The number of ROB reads
system.cpu3.rob.rob_writes                     500477                       # The number of ROB writes
system.cpu3.timesIdled                            219                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1527                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       37453                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     196116                       # Number of Instructions Simulated
system.cpu3.committedOps                       196116                       # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total               196116                       # Number of Instructions Simulated
system.cpu3.cpi                              0.887990                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.887990                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.126139                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.126139                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  355696                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 166589                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 100584                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.icache.replacements                   318                       # number of replacements
system.cpu3.icache.tagsinuse                80.204482                       # Cycle average of tags in use
system.cpu3.icache.total_refs                   22614                       # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs                   429                       # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs                 52.713287                       # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst    80.204482                       # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst     0.156649                       # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total        0.156649                       # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst        22614                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          22614                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        22614                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           22614                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        22614                       # number of overall hits
system.cpu3.icache.overall_hits::total          22614                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          477                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          477                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          477                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           477                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          477                       # number of overall misses
system.cpu3.icache.overall_misses::total          477                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6252000                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      6252000                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      6252000                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      6252000                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      6252000                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      6252000                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        23091                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        23091                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        23091                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        23091                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        23091                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        23091                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.020657                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.020657                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.020657                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.020657                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.020657                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.020657                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13106.918239                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13106.918239                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13106.918239                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13106.918239                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13106.918239                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13106.918239                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           48                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           48                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           48                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           48                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           48                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           48                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          429                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          429                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          429                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          429                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          429                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          429                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4992500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      4992500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4992500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      4992500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4992500                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      4992500                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.018579                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.018579                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.018579                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.018579                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.018579                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.018579                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11637.529138                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11637.529138                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11637.529138                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 11637.529138                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11637.529138                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 11637.529138                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.replacements                     0                       # number of replacements
system.cpu3.dcache.tagsinuse                24.557568                       # Cycle average of tags in use
system.cpu3.dcache.total_refs                   36284                       # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs               1295.857143                       # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data    24.557568                       # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data     0.047964                       # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total        0.047964                       # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data        41265                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          41265                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        30070                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         30070                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           15                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        71335                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           71335                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        71335                       # number of overall hits
system.cpu3.dcache.overall_hits::total          71335                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          376                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          376                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          130                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          130                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           59                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           59                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          506                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           506                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          506                       # number of overall misses
system.cpu3.dcache.overall_misses::total          506                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4881500                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      4881500                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2539500                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2539500                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       546000                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       546000                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      7421000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      7421000                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      7421000                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      7421000                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        41641                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        41641                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        30200                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        30200                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           74                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           74                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        71841                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        71841                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        71841                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        71841                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.009030                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.009030                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004305                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.004305                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.797297                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.797297                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.007043                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.007043                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.007043                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.007043                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12982.712766                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 12982.712766                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19534.615385                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 19534.615385                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9254.237288                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  9254.237288                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14666.007905                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 14666.007905                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14666.007905                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 14666.007905                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          218                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          218                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           30                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           30                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          248                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          248                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          248                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          248                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          158                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          100                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          100                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           59                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           59                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          258                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          258                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          258                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          258                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1328000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1328000                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1243000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1243000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       428000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       428000                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2571000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2571000                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2571000                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2571000                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003794                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003794                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003311                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003311                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.797297                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.797297                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003591                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003591                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003591                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003591                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  8405.063291                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  8405.063291                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data        12430                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total        12430                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  7254.237288                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  7254.237288                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9965.116279                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9965.116279                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9965.116279                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9965.116279                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.replacements                             0                       # number of replacements
system.l2c.tagsinuse                       425.230692                       # Cycle average of tags in use
system.l2c.total_refs                            1445                       # Total number of references to valid blocks.
system.l2c.sampled_refs                           527                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          2.741935                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks            0.824596                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst           289.832857                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data            59.073855                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst            61.730806                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data             5.603647                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst             4.388881                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data             0.760374                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst             2.293580                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data             0.722095                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.000013                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.004422                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.000901                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.000942                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000086                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst            0.000067                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data            0.000012                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst            0.000035                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data            0.000011                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.006489                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst                230                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                342                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                418                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                423                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1445                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 230                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 342                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 418                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 423                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1445                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                230                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                342                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                418                       # number of overall hits
system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                423                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   1445                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              360                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               83                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               12                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                6                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  544                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            18                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            19                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            16                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            18                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                71                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               360                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                83                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                12                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 6                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   675                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              360                       # number of overall misses
system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               83                       # number of overall misses
system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               12                       # number of overall misses
system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                6                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  675                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     18237500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      4615000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      4399500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data       666000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst       728500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data        68500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       248500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        68500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       29032000                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      5403000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       996000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       869000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       756000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      8024000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     18237500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     10018000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      4399500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data      1662000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst       728500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data       937500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       248500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       824500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        37056000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     18237500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     10018000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      4399500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data      1662000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst       728500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data       937500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       248500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       824500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       37056000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            590                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            425                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            430                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            429                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               1989                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           19                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           16                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           18                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              74                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             590                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             425                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             430                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             429                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2120                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            590                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            425                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            430                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            429                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2120                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.610169                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.195294                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.583333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.027907                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.013986                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.273504                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.857143                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.959459                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.610169                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.195294                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.027907                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.013986                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.318396                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.610169                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.195294                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.027907                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.013986                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.318396                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 50659.722222                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 62364.864865                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53006.024096                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 95142.857143                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 60708.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data        68500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 41416.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        68500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 53367.647059                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 57478.723404                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76615.384615                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72416.666667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data        63000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 61251.908397                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 50659.722222                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 59630.952381                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 53006.024096                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        83100                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 60708.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 72115.384615                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 41416.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 63423.076923                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 54897.777778                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 50659.722222                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 59630.952381                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 53006.024096                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        83100                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 60708.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 72115.384615                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 41416.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 63423.076923                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 54897.777778                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu0.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                14                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 14                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                14                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          358                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           80                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst            6                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             530                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           18                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           19                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           16                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           18                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           71                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          358                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           80                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              661                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          358                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           80                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             661                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     13753074                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3705088                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      3257128                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data       578261                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst       230760                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data        56252                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst        86256                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        56252                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     21723071                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       184010                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       190518                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       161513                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       191511                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       727552                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4247116                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       838760                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       720020                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       607520                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      6413416                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     13753074                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      7952204                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst      3257128                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data      1417021                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst       230760                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data       776272                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst        86256                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       663772                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     28136487                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     13753074                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      7952204                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst      3257128                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data      1417021                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst       230760                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data       776272                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst        86256                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       663772                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     28136487                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.606780                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.188235                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.013953                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.006993                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.266466                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.857143                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.959459                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.606780                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.188235                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.013953                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.006993                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.311792                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.606780                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.188235                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.013953                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.006993                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.311792                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38416.407821                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.756757                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.100000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608.714286                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        38460                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        56252                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        28752                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        56252                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.926415                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        64520                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        38460                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        28752                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 42566.546142                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        38460                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        28752                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 42566.546142                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------