path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000111                       # Number of seconds simulated
sim_ticks                                   110970500                       # Number of ticks simulated
final_tick                                  110970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 128659                       # Simulator instruction rate (inst/s)
host_op_rate                                   128659                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               13699808                       # Simulator tick rate (ticks/s)
host_mem_usage                                 244656                       # Number of bytes of host memory used
host_seconds                                     8.10                       # Real time elapsed on the host
sim_insts                                     1042156                       # Number of instructions simulated
sim_ops                                       1042156                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst            22784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst             4608                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data             1280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                42176                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        22784                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst          832                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst         4608                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           28480                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               356                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                72                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                20                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   659                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst           205315827                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            96890615                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst             7497488                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             7497488                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst            41524549                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data            11534597                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst             2306919                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             7497488                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               380064972                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst      205315827                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst        7497488                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst       41524549                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst        2306919                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          256644784                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst          205315827                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           96890615                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst            7497488                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            7497488                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst           41524549                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data           11534597                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst            2306919                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            7497488                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              380064972                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           660                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         660                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    42240                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     42240                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             77                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 115                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  39                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  29                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  60                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  65                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  27                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  18                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  24                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 23                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 12                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 60                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 38                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 17                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 98                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                       110942500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     660                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       400                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       194                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        54                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          148                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      274.594595                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     184.768834                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     255.591879                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             47     31.76%     31.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           39     26.35%     58.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           23     15.54%     73.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           12      8.11%     81.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           10      6.76%     88.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            5      3.38%     91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            5      3.38%     95.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            1      0.68%     95.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            6      4.05%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            148                       # Bytes accessed per row activation
system.physmem.totQLat                        5904750                       # Total ticks spent queuing
system.physmem.totMemAccLat                  18279750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      3300000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        8946.59                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27696.59                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         380.64                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      380.64                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.97                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        505                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.52                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       168094.70                       # Average gap between requests
system.physmem.pageHitRate                      76.52                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE         48408000                       # Time in different power states
system.physmem.memoryStateTime::REF           3640000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT          57233250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                    380064972                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 529                       # Transaction distribution
system.membus.trans_dist::ReadResp                528                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              287                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              77                       # Transaction distribution
system.membus.trans_dist::ReadExReq               162                       # Transaction distribution
system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1714                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1714                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port        42176                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               42176                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  42176                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              921500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy            6294424                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              5.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  416.952741                       # Cycle average of tags in use
system.l2c.tags.total_refs                       1442                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      526                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.741445                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks       0.799591                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      285.006820                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data       58.406933                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst        8.706163                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data        0.731992                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst       54.635838                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data        5.407858                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        2.562888                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        0.694658                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.004349                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.000891                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.000133                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000011                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000834                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000083                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000039                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000011                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.006362                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          526                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          179                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.008026                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    18236                       # Number of tag accesses
system.l2c.tags.data_accesses                   18236                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst                229                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst                409                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst                349                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data                  5                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst                423                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                   1442                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst                 229                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 409                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 349                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 423                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1442                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                229                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                409                       # number of overall hits
system.l2c.overall_hits::cpu1.data                 11                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                349                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                423                       # number of overall hits
system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
system.l2c.overall_hits::total                   1442                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst              359                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst               19                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst               75                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst                7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                  543                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data            22                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            21                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            17                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            17                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                77                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst               359                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                19                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                75                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                20                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                 7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   674                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              359                       # number of overall misses
system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               19                       # number of overall misses
system.l2c.overall_misses::cpu1.data               13                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               75                       # number of overall misses
system.l2c.overall_misses::cpu2.data               20                       # number of overall misses
system.l2c.overall_misses::cpu3.inst                7                       # number of overall misses
system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
system.l2c.overall_misses::total                  674                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst     24479500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data      5371500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst      1394250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst      5296000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data       494750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst       438500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total       37623500                       # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data      7056000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       894000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data      1355500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       863500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total     10169000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     24479500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data     12427500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst      1394250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data       968500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      5296000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1850250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       438500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       938000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        47792500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     24479500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data     12427500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst      1394250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data       968500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      5296000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1850250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       438500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       938000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       47792500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst            588                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst            428                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst            424                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst            430                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total               1985                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           25                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           21                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           17                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              80                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             588                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             428                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             424                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             430                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                2116                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            588                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            428                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            424                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            430                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               2116                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.610544                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.044393                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.176887                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.583333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst      0.016279                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.273552                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.880000                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.962500                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.610544                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.044393                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.176887                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.800000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.016279                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.318526                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.610544                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.044393                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.176887                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.800000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.016279                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.318526                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68188.022284                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 72587.837838                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73381.578947                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70613.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 70678.571429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 62642.857143                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 69288.213628                       # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 75063.829787                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data        74500                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 104269.230769                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 71958.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 77625.954198                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 68188.022284                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 73973.214286                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73381.578947                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 70613.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 92512.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 62642.857143                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 72153.846154                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 70908.753709                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 68188.022284                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 73973.214286                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73381.578947                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 70613.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 92512.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 62642.857143                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 72153.846154                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 70908.753709                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu0.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                14                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 14                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                14                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst          357                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst           13                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst           72                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total             529                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data           22                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           21                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           17                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           17                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           77                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          357                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           72                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           20                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              660                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          357                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           72                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           20                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             660                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     19908750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data      4459500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       858750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      4235250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data       408750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       258500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total     30254500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       220022                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       218520                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       170017                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       170017                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total       778576                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5892000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       743000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      1197000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       713000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      8545000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     19908750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data     10351500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst       858750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       805500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      4235250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1605750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       258500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       775500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     38799500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     19908750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data     10351500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst       858750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       805500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      4235250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1605750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       258500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       775500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     38799500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.030374                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.169811                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.583333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.009302                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.266499                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.880000                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.962500                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.030374                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.169811                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.009302                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.311909                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.030374                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.169811                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.009302                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.311909                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55766.806723                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60263.513514                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66057.692308                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58822.916667                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        64625                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 57191.871456                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10405.714286                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.376623                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62680.851064                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61916.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 92076.923077                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 59416.666667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 65229.007634                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55766.806723                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61616.071429                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66057.692308                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61961.538462                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58822.916667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 80287.500000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        64625                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59653.846154                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58787.121212                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55766.806723                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61616.071429                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66057.692308                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61961.538462                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58822.916667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 80287.500000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        64625                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59653.846154                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58787.121212                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.toL2Bus.throughput                  1688665006                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq               2536                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp              2535                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             290                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            290                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              392                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             392                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1175                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          586                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          856                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          364                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          848                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          367                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          860                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          358                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  5414                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        37568                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11136                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        27392                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        27136                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        27520                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total             135424                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus                135424                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus           51968                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy            1625975                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              1.5                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy           2708248                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             2.4                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy           1463019                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             1.3                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           1929745                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             1.7                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy           1153498                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             1.0                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy           1921995                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             1.7                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy           1183735                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             1.1                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           1936494                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             1.7                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy           1159999                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             1.0                       # Layer utilization (%)
system.cpu0.branchPred.lookups                  83070                       # Number of BP lookups
system.cpu0.branchPred.condPredicted            80870                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect             1218                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups               80399                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                  78350                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            97.451461                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                    512                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect               132                       # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          221942                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             17233                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                        493008                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                      83070                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches             78862                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                       161826                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                   3812                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles                 13755                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1482                       # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines                     5835                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  491                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples            196747                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             2.505797                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.214858                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                   34921     17.75%     17.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   80152     40.74%     58.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                     578      0.29%     58.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                     974      0.50%     59.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                     477      0.24%     59.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                   76267     38.76%     98.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                     570      0.29%     98.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                     349      0.18%     98.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                    2459      1.25%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total              196747                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.374287                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       2.221337                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                   17711                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles                15452                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                   160920                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles                  218                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                  2446                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts                490118                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                  2446                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                   18323                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                    441                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles         14289                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                   160585                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles                  663                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts                487271                       # Number of instructions processed by rename
system.cpu0.rename.SQFullEvents                   294                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands             333181                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups               971741                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups          733988                       # Number of integer rename lookups
system.cpu0.rename.CommittedMaps               320207                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                   12974                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts               868                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts           890                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                     3239                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads              155891                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores              78785                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            76033                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           75852                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                    407472                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded                912                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                   404753                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued              136                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined          10781                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined         9726                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved           353                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples       196747                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.057226                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.098946                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0              34174     17.37%     17.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1               4673      2.38%     19.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2              77781     39.53%     59.28% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3              77469     39.37%     98.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4               1629      0.83%     99.48% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                654      0.33%     99.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                260      0.13%     99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                 91      0.05%     99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                 16      0.01%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total         196747                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                     60     26.43%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     26.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                    55     24.23%     50.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                  112     49.34%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu               171127     42.28%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              155427     38.40%     80.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite              78199     19.32%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total                404753                       # Type of FU issued
system.cpu0.iq.rate                          1.823688                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                        227                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.000561                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads           1006616                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes           419219                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses       402934                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses                404980                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads           75562                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads         2198                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores         1432                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                  2446                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                    397                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                   44                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts             484968                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts              314                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts               155891                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts               78785                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               800                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                    9                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect           343                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect         1106                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts                1449                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts               403684                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               155095                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts             1069                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                        76584                       # number of nop insts executed
system.cpu0.iew.exec_refs                      233191                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                   80195                       # Number of branches executed
system.cpu0.iew.exec_stores                     78096                       # Number of stores executed
system.cpu0.iew.exec_rate                    1.818872                       # Inst execution rate
system.cpu0.iew.wb_sent                        403263                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                       402934                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                   238926                       # num instructions producing a value
system.cpu0.iew.wb_consumers                   241439                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      1.815492                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.989592                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts          12279                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts             1218                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples       194301                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.432628                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     2.139595                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0        34596     17.81%     17.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1        79813     41.08%     58.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2         2261      1.16%     60.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3          671      0.35%     60.39% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4          526      0.27%     60.66% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        75370     38.79%     99.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6          456      0.23%     99.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7          240      0.12%     99.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8          368      0.19%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total       194301                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts              472662                       # Number of instructions committed
system.cpu0.commit.committedOps                472662                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                        231046                       # Number of memory references committed
system.cpu0.commit.loads                       153693                       # Number of loads committed
system.cpu0.commit.membars                         84                       # Number of memory barriers committed
system.cpu0.commit.branches                     79240                       # Number of branches committed
system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                   318538                       # Number of committed integer instructions.
system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass        75972     16.07%     16.07% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu          165560     35.03%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead         153777     32.53%     83.63% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite         77353     16.37%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total           472662                       # Class of committed instruction
system.cpu0.commit.bw_lim_events                  368                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                      677713                       # The number of ROB reads
system.cpu0.rob.rob_writes                     972345                       # The number of ROB writes
system.cpu0.timesIdled                            334                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          25195                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                     396606                       # Number of Instructions Simulated
system.cpu0.committedOps                       396606                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              0.559603                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.559603                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.786980                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.786980                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                  722190                       # number of integer regfile reads
system.cpu0.int_regfile_writes                 325483                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
system.cpu0.misc_regfile_reads                 235015                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
system.cpu0.icache.tags.replacements              297                       # number of replacements
system.cpu0.icache.tags.tagsinuse          241.252317                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs               5079                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              587                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs             8.652470                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.252317                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471196                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.471196                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          290                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.566406                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses             6422                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses            6422                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst         5079                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total           5079                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst         5079                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total            5079                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst         5079                       # number of overall hits
system.cpu0.icache.overall_hits::total           5079                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          756                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          756                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          756                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           756                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          756                       # number of overall misses
system.cpu0.icache.overall_misses::total          756                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     35519995                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     35519995                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     35519995                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     35519995                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     35519995                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     35519995                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst         5835                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total         5835                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst         5835                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total         5835                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst         5835                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total         5835                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.129563                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.129563                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.129563                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.129563                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.129563                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.129563                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46984.120370                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 46984.120370                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46984.120370                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 46984.120370                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46984.120370                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 46984.120370                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          168                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          168                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          168                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          168                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          168                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          168                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          588                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          588                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          588                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          588                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          588                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          588                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     27366252                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     27366252                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     27366252                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     27366252                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     27366252                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     27366252                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.100771                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.100771                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.100771                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46541.244898                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46541.244898                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46541.244898                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 46541.244898                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46541.244898                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 46541.244898                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          141.985956                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs             155741                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              170                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs           916.123529                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.985956                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277316                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.277316                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.328125                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           627612                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          627612                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data        79059                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          79059                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        76768                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         76768                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data       155827                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total          155827                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data       155827                       # number of overall hits
system.cpu0.dcache.overall_hits::total         155827                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          413                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          413                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          543                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          543                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data          956                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total           956                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data          956                       # number of overall misses
system.cpu0.dcache.overall_misses::total          956                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     12955987                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total     12955987                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     33432506                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total     33432506                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       404750                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       404750                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     46388493                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     46388493                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     46388493                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     46388493                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        79472                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        79472                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        77311                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        77311                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data       156783                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total       156783                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data       156783                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total       156783                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005197                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.005197                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007024                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007024                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006098                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.006098                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006098                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.006098                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31370.428571                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 31370.428571                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 61569.992634                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 61569.992634                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48523.528243                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 48523.528243                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48523.528243                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 48523.528243                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          692                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               24                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    28.833333                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          226                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          226                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          368                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total          368                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          594                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          594                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          594                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          594                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          187                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          187                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          175                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          175                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          362                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          362                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          362                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      5995003                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      5995003                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7531728                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7531728                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       361250                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       361250                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     13526731                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     13526731                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     13526731                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     13526731                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002353                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002353                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002264                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002264                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002309                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.002309                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002309                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.002309                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32058.839572                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32058.839572                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43038.445714                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43038.445714                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37366.660221                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37366.660221                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37366.660221                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37366.660221                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                  52187                       # Number of BP lookups
system.cpu1.branchPred.condPredicted            49510                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect             1259                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups               46153                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                  45385                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            98.335969                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                    643                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
system.cpu1.numCycles                          177799                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles             28925                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                        291186                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                      52187                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches             46028                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                       103264                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                   3653                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles                 32544                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles         7803                       # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles          785                       # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines                    20583                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                  266                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples            175643                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.657829                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.130344                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                   72379     41.21%     41.21% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   52711     30.01%     71.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                    6570      3.74%     74.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                    3206      1.83%     76.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                     681      0.39%     77.17% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   34861     19.85%     97.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                    1219      0.69%     97.71% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                     754      0.43%     98.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                    3262      1.86%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total              175643                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.293517                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.637726                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                   34549                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles                28563                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                    96884                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                 5527                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                  2317                       # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts                287488                       # Number of instructions handled by decode
system.cpu1.rename.SquashCycles                  2317                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                   35238                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                  16093                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles         11725                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                    91623                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles                10844                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts                285400                       # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.RenamedOperands             199084                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups               545686                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups          424083                       # Number of integer rename lookups
system.cpu1.rename.CommittedMaps               186368                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                   12716                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts              1090                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts          1211                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                    13408                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads               80706                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores              38119                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads            38742                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           33075                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                    236041                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded               6768                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                   238678                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued               59                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined          10581                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined        10451                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved           572                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples       175643                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        1.358881                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.308073                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0              69713     39.69%     39.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1              23816     13.56%     53.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2              38346     21.83%     75.08% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3              38982     22.19%     97.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4               3247      1.85%     99.12% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               1165      0.66%     99.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                266      0.15%     99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                 49      0.03%     99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                 59      0.03%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total         175643                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                     17      6.42%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                    38     14.34%     20.75% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                  210     79.25%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu               115728     48.49%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.49% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead               85517     35.83%     84.32% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite              37433     15.68%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total                238678                       # Type of FU issued
system.cpu1.iq.rate                          1.342404                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                        265                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.001110                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads            653323                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes           253430                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses       236861                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                238943                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           32850                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads         2336                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores         1422                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                  2317                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                    666                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                   39                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts             282498                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts              328                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                80706                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts               38119                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts              1050                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                    38                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents            40                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect           465                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect          907                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                1372                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts               237512                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                79760                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts             1166                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        39689                       # number of nop insts executed
system.cpu1.iew.exec_refs                      117113                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                   48963                       # Number of branches executed
system.cpu1.iew.exec_stores                     37353                       # Number of stores executed
system.cpu1.iew.exec_rate                    1.335846                       # Inst execution rate
system.cpu1.iew.wb_sent                        237151                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                       236861                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                   133843                       # num instructions producing a value
system.cpu1.iew.wb_consumers                   138503                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      1.332184                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.966355                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts          12124                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls           6196                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts             1259                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples       165523                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     1.633344                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     2.016153                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0        67946     41.05%     41.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1        47096     28.45%     69.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2         6082      3.67%     73.18% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3         7142      4.31%     77.49% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4         1575      0.95%     78.44% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        33355     20.15%     98.59% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6          510      0.31%     98.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7         1001      0.60%     99.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8          816      0.49%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total       165523                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts              270356                       # Number of instructions committed
system.cpu1.commit.committedOps                270356                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                        115067                       # Number of memory references committed
system.cpu1.commit.loads                        78370                       # Number of loads committed
system.cpu1.commit.membars                       5484                       # Number of memory barriers committed
system.cpu1.commit.branches                     48146                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                   185335                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass        38938     14.40%     14.40% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu          110867     41.01%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.41% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead          83854     31.02%     86.43% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite         36697     13.57%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total           270356                       # Class of committed instruction
system.cpu1.commit.bw_lim_events                  816                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                      446600                       # The number of ROB reads
system.cpu1.rob.rob_writes                     567283                       # The number of ROB writes
system.cpu1.timesIdled                            213                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                           2156                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                       44141                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                     225934                       # Number of Instructions Simulated
system.cpu1.committedOps                       225934                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              0.786951                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        0.786951                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              1.270727                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        1.270727                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                  409872                       # number of integer regfile reads
system.cpu1.int_regfile_writes                 191136                       # number of integer regfile writes
system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 118682                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu1.icache.tags.replacements              318                       # number of replacements
system.cpu1.icache.tags.tagsinuse           79.885573                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs              20107                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              428                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            46.978972                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    79.885573                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.156027                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.156027                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses            21011                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses           21011                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst        20107                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total          20107                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst        20107                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total           20107                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst        20107                       # number of overall hits
system.cpu1.icache.overall_hits::total          20107                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          476                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          476                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          476                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           476                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          476                       # number of overall misses
system.cpu1.icache.overall_misses::total          476                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7353244                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      7353244                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      7353244                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      7353244                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      7353244                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      7353244                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst        20583                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total        20583                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst        20583                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total        20583                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst        20583                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total        20583                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023126                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.023126                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023126                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.023126                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023126                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.023126                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15447.991597                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15447.991597                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15447.991597                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15447.991597                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15447.991597                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15447.991597                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs           13                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           48                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total           48                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst           48                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total           48                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst           48                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total           48                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          428                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          428                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          428                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          428                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          428                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          428                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5927255                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      5927255                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5927255                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      5927255                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5927255                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      5927255                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.020794                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.020794                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.020794                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.020794                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.020794                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.020794                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13848.726636                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13848.726636                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13848.726636                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13848.726636                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13848.726636                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13848.726636                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           24.706566                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              42694                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs          1524.785714                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    24.706566                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.048255                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.048255                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           334614                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          334614                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data        46543                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          46543                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        36491                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         36491                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           12                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        83034                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           83034                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        83034                       # number of overall hits
system.cpu1.dcache.overall_hits::total          83034                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          352                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          352                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          140                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           54                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          492                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           492                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          492                       # number of overall misses
system.cpu1.dcache.overall_misses::total          492                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4522597                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      4522597                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3033762                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      3033762                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       535508                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       535508                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      7556359                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      7556359                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      7556359                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      7556359                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        46895                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        46895                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        36631                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        36631                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           66                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        83526                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        83526                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        83526                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        83526                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.007506                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.007506                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003822                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.003822                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.818182                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.818182                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005890                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.005890                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005890                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.005890                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12848.286932                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12848.286932                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21669.728571                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21669.728571                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  9916.814815                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  9916.814815                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15358.453252                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15358.453252                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15358.453252                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15358.453252                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          195                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          195                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           32                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total           32                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          227                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          227                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          227                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          227                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          157                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          157                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          108                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           54                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          265                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          265                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          265                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          265                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1099522                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1099522                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1387488                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1387488                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       427492                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       427492                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2487010                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      2487010                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2487010                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      2487010                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003348                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003348                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002948                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002948                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.818182                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.818182                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003173                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.003173                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003173                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.003173                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  7003.324841                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  7003.324841                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12847.111111                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12847.111111                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  7916.518519                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  7916.518519                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  9384.943396                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total  9384.943396                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  9384.943396                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total  9384.943396                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.branchPred.lookups                  51191                       # Number of BP lookups
system.cpu2.branchPred.condPredicted            48468                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect             1308                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups               44993                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                  44297                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            98.453093                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                    684                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                          177434                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles             28865                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                        285908                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                      51191                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches             44981                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                       100768                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                   3816                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles                 31184                       # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles         7805                       # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles         1366                       # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines                    19788                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes                  272                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples            172424                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.658168                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.138146                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                   71656     41.56%     41.56% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                   51257     29.73%     71.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                    6128      3.55%     74.84% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                    3186      1.85%     76.69% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                     695      0.40%     77.09% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                   34284     19.88%     96.97% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                    1167      0.68%     97.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                     773      0.45%     98.10% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                    3278      1.90%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total              172424                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.288507                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       1.611348                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                   34386                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles                27902                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                    94859                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles                 5040                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                  2432                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts                282267                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                  2432                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                   35111                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                  14773                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles         12374                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                    90050                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles                 9879                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts                280008                       # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.RenamedOperands             196247                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups               536665                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups          417354                       # Number of integer rename lookups
system.cpu2.rename.CommittedMaps               183125                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                   13122                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts              1115                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts          1240                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                    12503                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads               79020                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores              37489                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads            37725                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores           32426                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                    232155                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded               6357                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                   234096                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued              107                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined          11107                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined        11056                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved           607                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples       172424                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.357676                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.313193                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0              69134     40.10%     40.10% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1              22467     13.03%     53.13% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2              37714     21.87%     75.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3              38330     22.23%     97.23% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4               3239      1.88%     99.11% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5               1151      0.67%     99.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6                279      0.16%     99.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7                 54      0.03%     99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8                 56      0.03%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total         172424                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                     12      4.40%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      4.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                    51     18.68%     23.08% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                  210     76.92%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu               114033     48.71%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.71% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead               83276     35.57%     84.29% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite              36787     15.71%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total                234096                       # Type of FU issued
system.cpu2.iq.rate                          1.319341                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                        273                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.001166                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads            640996                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes           249665                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses       232273                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses                234369                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads           32149                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads         2502                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation           46                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores         1485                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                  2432                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                    787                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles                   45                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts             277138                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts              365                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts                79020                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts               37489                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts              1072                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                    45                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents            46                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect           464                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect          971                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts                1435                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts               232944                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts                77967                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts             1152                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        38626                       # number of nop insts executed
system.cpu2.iew.exec_refs                      114664                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                   47841                       # Number of branches executed
system.cpu2.iew.exec_stores                     36697                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.312849                       # Inst execution rate
system.cpu2.iew.wb_sent                        232563                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                       232273                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                   131430                       # num instructions producing a value
system.cpu2.iew.wb_consumers                   136123                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.309067                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.965524                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts          12771                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls           5750                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts             1308                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples       162187                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.630001                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.017893                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0        66847     41.22%     41.22% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1        46010     28.37%     69.58% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2         6109      3.77%     73.35% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3         6666      4.11%     77.46% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4         1557      0.96%     78.42% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5        32708     20.17%     98.59% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6          471      0.29%     98.88% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7         1007      0.62%     99.50% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8          812      0.50%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total       162187                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts              264365                       # Number of instructions committed
system.cpu2.commit.committedOps                264365                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                        112522                       # Number of memory references committed
system.cpu2.commit.loads                        76518                       # Number of loads committed
system.cpu2.commit.membars                       5033                       # Number of memory barriers committed
system.cpu2.commit.branches                     47000                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                   181641                       # Number of committed integer instructions.
system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        37787     14.29%     14.29% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu          109023     41.24%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.53% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead          81551     30.85%     86.38% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite         36004     13.62%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total           264365                       # Class of committed instruction
system.cpu2.commit.bw_lim_events                  812                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                      437924                       # The number of ROB reads
system.cpu2.rob.rob_writes                     556709                       # The number of ROB writes
system.cpu2.timesIdled                            223                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                           5010                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                       44506                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                     221545                       # Number of Instructions Simulated
system.cpu2.committedOps                       221545                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              0.800894                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        0.800894                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              1.248605                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        1.248605                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                  402715                       # number of integer regfile reads
system.cpu2.int_regfile_writes                 188101                       # number of integer regfile writes
system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu2.misc_regfile_reads                 116228                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu2.icache.tags.replacements              317                       # number of replacements
system.cpu2.icache.tags.tagsinuse           81.450670                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs              19300                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              424                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs            45.518868                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    81.450670                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.159083                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.159083                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024          107                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.208984                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses            20212                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses           20212                       # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst        19300                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total          19300                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst        19300                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total           19300                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst        19300                       # number of overall hits
system.cpu2.icache.overall_hits::total          19300                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          488                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          488                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          488                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           488                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          488                       # number of overall misses
system.cpu2.icache.overall_misses::total          488                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     11534741                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total     11534741                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst     11534741                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total     11534741                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst     11534741                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total     11534741                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst        19788                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total        19788                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst        19788                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total        19788                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst        19788                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total        19788                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024661                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.024661                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024661                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.024661                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024661                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.024661                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23636.764344                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 23636.764344                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23636.764344                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 23636.764344                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23636.764344                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 23636.764344                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs           85                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs           85                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           64                       # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total           64                       # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst           64                       # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total           64                       # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst           64                       # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total           64                       # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          424                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          424                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          424                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          424                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          424                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          424                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      9234505                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      9234505                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      9234505                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      9234505                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      9234505                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      9234505                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021427                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021427                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021427                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.021427                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021427                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.021427                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21779.492925                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21779.492925                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21779.492925                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 21779.492925                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21779.492925                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 21779.492925                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           26.136002                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              42041                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1501.464286                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.136002                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051047                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.051047                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           327476                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          327476                       # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data        45457                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          45457                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        35794                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         35794                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        81251                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           81251                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        81251                       # number of overall hits
system.cpu2.dcache.overall_hits::total          81251                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          345                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          345                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           58                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          484                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           484                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          484                       # number of overall misses
system.cpu2.dcache.overall_misses::total          484                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5375808                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      5375808                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3387510                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      3387510                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       561006                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       561006                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      8763318                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      8763318                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      8763318                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      8763318                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        45802                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        45802                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        35933                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        35933                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           71                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        81735                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        81735                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        81735                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        81735                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.007532                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.007532                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003868                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.003868                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.816901                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.816901                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005922                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.005922                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005922                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.005922                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15582.052174                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 15582.052174                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24370.575540                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 24370.575540                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  9672.517241                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  9672.517241                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18106.028926                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 18106.028926                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18106.028926                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 18106.028926                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          184                       # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total          184                       # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           33                       # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data          217                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total          217                       # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data          217                       # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total          217                       # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          161                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          106                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           58                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          267                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          267                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          267                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1467781                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1467781                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1796490                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1796490                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       444994                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       444994                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3264271                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      3264271                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3264271                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      3264271                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003515                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003515                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002950                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002950                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.816901                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.816901                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003267                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.003267                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003267                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.003267                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9116.652174                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9116.652174                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16948.018868                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16948.018868                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  7672.310345                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  7672.310345                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12225.734082                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12225.734082                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12225.734082                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12225.734082                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.branchPred.lookups                  47572                       # Number of BP lookups
system.cpu3.branchPred.condPredicted            44838                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect             1269                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups               41556                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits                  40675                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            97.879969                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                    650                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
system.cpu3.numCycles                          177088                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles             31611                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                        260615                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                      47572                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches             41325                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                        95272                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                   3721                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles                 37783                       # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles         7803                       # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles          790                       # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines                    23344                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes                  257                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples            175638                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.483819                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.061741                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0                   80366     45.76%     45.76% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                   49379     28.11%     73.87% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                    7947      4.52%     78.40% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                    3182      1.81%     80.21% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                     669      0.38%     80.59% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                   28809     16.40%     96.99% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                    1228      0.70%     97.69% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                     757      0.43%     98.12% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                    3301      1.88%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total              175638                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.268635                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       1.471669                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles                   38601                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles                32457                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                    87595                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles                 6808                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles                  2374                       # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts                256826                       # Number of instructions handled by decode
system.cpu3.rename.SquashCycles                  2374                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles                   39299                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles                  20012                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles         11695                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                    81034                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles                13421                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts                254587                       # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.RenamedOperands             176229                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups               478476                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups          373673                       # Number of integer rename lookups
system.cpu3.rename.CommittedMaps               163264                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                   12965                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts              1094                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts          1216                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                    16061                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads               69948                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores              32037                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads            34088                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores           26994                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                    208399                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded               8161                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                   212159                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued              124                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined          10835                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined        11026                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved           608                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples       175638                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        1.207933                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.292111                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0              77942     44.38%     44.38% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1              27771     15.81%     60.19% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2              32234     18.35%     78.54% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3              32910     18.74%     97.28% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4               3253      1.85%     99.13% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5               1156      0.66%     99.79% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6                263      0.15%     99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7                 52      0.03%     99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total         175638                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                     12      4.44%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                     0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                      0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      4.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead                    48     17.78%     22.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite                  210     77.78%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu               104799     49.40%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.40% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead               76027     35.83%     85.23% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite              31333     14.77%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total                212159                       # Type of FU issued
system.cpu3.iq.rate                          1.198043                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                        270                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.001273                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads            600350                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes           227441                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses       210302                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses                212429                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads           26730                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads         2459                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation           46                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores         1447                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles                  2374                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                    705                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles                   44                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts             251552                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts              401                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts                69948                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts               32037                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts              1046                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                    44                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents            46                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect           464                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect          910                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts                1374                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts               210966                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts                68906                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts             1193                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        34992                       # number of nop insts executed
system.cpu3.iew.exec_refs                      100151                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                   44184                       # Number of branches executed
system.cpu3.iew.exec_stores                     31245                       # Number of stores executed
system.cpu3.iew.exec_rate                    1.191306                       # Inst execution rate
system.cpu3.iew.wb_sent                        210604                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                       210302                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                   116846                       # num instructions producing a value
system.cpu3.iew.wb_consumers                   121503                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      1.187556                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.961672                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts          12453                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls           7553                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts             1269                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples       165461                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     1.444927                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.940782                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0        77418     46.79%     46.79% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1        42307     25.57%     72.36% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2         6087      3.68%     76.04% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3         8486      5.13%     81.17% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4         1577      0.95%     82.12% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5        27301     16.50%     98.62% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6          474      0.29%     98.91% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7         1005      0.61%     99.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8          806      0.49%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total       165461                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts              239079                       # Number of instructions committed
system.cpu3.commit.committedOps                239079                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                         98079                       # Number of memory references committed
system.cpu3.commit.loads                        67489                       # Number of loads committed
system.cpu3.commit.membars                       6836                       # Number of memory barriers committed
system.cpu3.commit.branches                     43385                       # Number of branches committed
system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                   163585                       # Number of committed integer instructions.
system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass        34172     14.29%     14.29% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu           99992     41.82%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.12% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead          74325     31.09%     87.21% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite         30590     12.79%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total           239079                       # Class of committed instruction
system.cpu3.commit.bw_lim_events                  806                       # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads                      415600                       # The number of ROB reads
system.cpu3.rob.rob_writes                     505444                       # The number of ROB writes
system.cpu3.timesIdled                            214                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                           1450                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                       44852                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                     198071                       # Number of Instructions Simulated
system.cpu3.committedOps                       198071                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              0.894063                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        0.894063                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              1.118489                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        1.118489                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads                  358875                       # number of integer regfile reads
system.cpu3.int_regfile_writes                 168004                       # number of integer regfile writes
system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
system.cpu3.misc_regfile_reads                 101700                       # number of misc regfile reads
system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
system.cpu3.icache.tags.replacements              319                       # number of replacements
system.cpu3.icache.tags.tagsinuse           77.082229                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs              22869                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              430                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs            53.183721                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    77.082229                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.150551                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.150551                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024          111                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.216797                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses            23774                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses           23774                       # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst        22869                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total          22869                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst        22869                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total           22869                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst        22869                       # number of overall hits
system.cpu3.icache.overall_hits::total          22869                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          475                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          475                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          475                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           475                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          475                       # number of overall misses
system.cpu3.icache.overall_misses::total          475                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6365994                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      6365994                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      6365994                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      6365994                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      6365994                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      6365994                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst        23344                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total        23344                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst        23344                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total        23344                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst        23344                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total        23344                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.020348                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.020348                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.020348                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.020348                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.020348                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.020348                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13402.092632                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13402.092632                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13402.092632                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13402.092632                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13402.092632                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13402.092632                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           45                       # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total           45                       # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst           45                       # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total           45                       # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst           45                       # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total           45                       # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          430                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          430                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          430                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          430                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          430                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          430                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5107006                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      5107006                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5107006                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      5107006                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5107006                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      5107006                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.018420                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.018420                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.018420                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.018420                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.018420                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.018420                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11876.758140                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11876.758140                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11876.758140                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 11876.758140                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11876.758140                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 11876.758140                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           23.636588                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              36715                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs          1266.034483                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    23.636588                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.046165                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.046165                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           291244                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          291244                       # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data        41825                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          41825                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        30388                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         30388                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           15                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        72213                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           72213                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        72213                       # number of overall hits
system.cpu3.dcache.overall_hits::total          72213                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          334                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          334                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          131                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          131                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           56                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          465                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           465                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          465                       # number of overall misses
system.cpu3.dcache.overall_misses::total          465                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4213650                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      4213650                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2829011                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2829011                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       511006                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       511006                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      7042661                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      7042661                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      7042661                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      7042661                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        42159                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        42159                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        30519                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        30519                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        72678                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        72678                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        72678                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        72678                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007922                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.007922                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004292                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.004292                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.788732                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.788732                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.006398                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.006398                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.006398                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.006398                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12615.718563                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 12615.718563                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21595.503817                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 21595.503817                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9125.107143                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  9125.107143                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15145.507527                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 15145.507527                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15145.507527                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 15145.507527                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          173                       # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total          173                       # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           31                       # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total           31                       # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data          204                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total          204                       # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data          204                       # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total          204                       # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          161                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          100                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          100                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           56                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          261                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          261                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          261                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          261                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1077518                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1077518                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1290489                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1290489                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       398994                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       398994                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2368007                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      2368007                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2368007                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      2368007                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003819                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003819                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003277                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003277                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.788732                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.788732                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003591                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.003591                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003591                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.003591                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6692.658385                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6692.658385                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12904.890000                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12904.890000                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  7124.892857                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  7124.892857                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9072.823755                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9072.823755                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9072.823755                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9072.823755                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------