path: root/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000265                       # Number of seconds simulated
sim_ticks                                   264840500                       # Number of ticks simulated
final_tick                                  264840500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 139043                       # Simulator instruction rate (inst/s)
host_op_rate                                   139043                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               55594555                       # Simulator tick rate (ticks/s)
host_mem_usage                                 242988                       # Number of bytes of host memory used
host_seconds                                     4.76                       # Real time elapsed on the host
sim_insts                                      662366                       # Number of instructions simulated
sim_ops                                        662366                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst              448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst             3712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data             1472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data              960                       # Number of bytes read from this memory
system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst          448                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst         3712                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst                 7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst                58                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data                23                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data                15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst            68871642                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            39873056                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst             1691584                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             3624823                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst            14015983                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             5558062                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst              966620                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data             3624823                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               138226593                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst       68871642                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst        1691584                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst       14015983                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst         966620                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           85545829                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst           68871642                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           39873056                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst            1691584                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            3624823                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst           14015983                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            5558062                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst             966620                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data            3624823                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              138226593                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.workload.num_syscalls                  89                       # Number of system calls
system.cpu0.numCycles                          529681                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                     158238                       # Number of instructions committed
system.cpu0.committedOps                       158238                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses               108984                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts        25976                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                      108984                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads             315110                       # number of times the integer registers were read
system.cpu0.num_int_register_writes            110590                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_mem_refs                        73853                       # number of memory refs
system.cpu0.num_load_insts                      48895                       # Number of load instructions
system.cpu0.num_store_insts                     24958                       # Number of store instructions
system.cpu0.num_idle_cycles                  0.002000                       # Number of idle cycles
system.cpu0.num_busy_cycles              529680.998000                       # Number of busy cycles
system.cpu0.not_idle_fraction                1.000000                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.000000                       # Percentage of idle cycles
system.cpu0.Branches                            26841                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                23568     14.89%     14.89% # Class of executed instruction
system.cpu0.op_class::IntAlu                    60795     38.40%     53.29% # Class of executed instruction
system.cpu0.op_class::IntMult                       0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     53.29% # Class of executed instruction
system.cpu0.op_class::MemRead                   48979     30.94%     84.23% # Class of executed instruction
system.cpu0.op_class::MemWrite                  24958     15.77%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                    158300                       # Class of executed instruction
system.cpu0.dcache.tags.replacements                2                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          145.090849                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs              73323                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs              167                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs           439.059880                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.090849                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.283381                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.283381                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          165                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.322266                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses           295643                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses          295643                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data        48717                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total          48717                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data        24724                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total         24724                       # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data        73441                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total           73441                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data        73441                       # number of overall hits
system.cpu0.dcache.overall_hits::total          73441                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data          168                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total          168                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total          183                       # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data          351                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total           351                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data          351                       # number of overall misses
system.cpu0.dcache.overall_misses::total          351                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      5149000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total      5149000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7867000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total      7867000                       # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       395000                       # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total       395000                       # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data     13016000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total     13016000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data     13016000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total     13016000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data        48885                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total        48885                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data        24907                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total        24907                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data        73792                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total        73792                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data        73792                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total        73792                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003437                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.003437                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007347                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.007347                       # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004757                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.004757                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004757                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.004757                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038                       # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692                       # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692                       # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
system.cpu0.dcache.writebacks::total                1                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          168                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total          168                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          183                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total          183                       # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data          351                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data          351                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total          351                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4981000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4981000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7684000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7684000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       369000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total       369000                       # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     12665000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total     12665000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     12665000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total     12665000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003437                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003437                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007347                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007347                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004757                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.004757                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004757                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.004757                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038                       # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692                       # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692                       # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083                       # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements              215                       # number of replacements
system.cpu0.icache.tags.tagsinuse          211.456411                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs             157834                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           337.974304                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   211.456411                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.413001                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.413001                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses           158768                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses          158768                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst       157834                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total         157834                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst       157834                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total          157834                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst       157834                       # number of overall hits
system.cpu0.icache.overall_hits::total         157834                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
system.cpu0.icache.overall_misses::total          467                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     20139500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total     20139500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst     20139500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total     20139500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst     20139500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total     20139500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst       158301                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total       158301                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst       158301                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total       158301                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst       158301                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total       158301                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002950                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.002950                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002950                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.002950                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002950                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.002950                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 43125.267666                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 43125.267666                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks          215                       # number of writebacks
system.cpu0.icache.writebacks::total              215                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          467                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     19672500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total     19672500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     19672500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total     19672500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     19672500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total     19672500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002950                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002950                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002950                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.002950                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002950                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.002950                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                          529680                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                     168829                       # Number of instructions committed
system.cpu1.committedOps                       168829                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses               111193                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts        32827                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                      111193                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads             275699                       # number of times the integer registers were read
system.cpu1.num_int_register_writes            104505                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_mem_refs                        54535                       # number of memory refs
system.cpu1.num_load_insts                      41264                       # Number of load instructions
system.cpu1.num_store_insts                     13271                       # Number of store instructions
system.cpu1.num_idle_cycles              73879.862241                       # Number of idle cycles
system.cpu1.num_busy_cycles              455800.137759                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.860520                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.139480                       # Percentage of idle cycles
system.cpu1.Branches                            34479                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                25261     14.96%     14.96% # Class of executed instruction
system.cpu1.op_class::IntAlu                    74858     44.33%     59.29% # Class of executed instruction
system.cpu1.op_class::IntMult                       0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.29% # Class of executed instruction
system.cpu1.op_class::MemRead                   55471     32.85%     92.14% # Class of executed instruction
system.cpu1.op_class::MemWrite                  13271      7.86%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                    168861                       # Class of executed instruction
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse           26.495164                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs              28944                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs           964.800000                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.495164                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.051748                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.051748                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses           218364                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses          218364                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data        41094                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total          41094                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data        13094                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total         13094                       # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data        54188                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total           54188                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data        54188                       # number of overall hits
system.cpu1.dcache.overall_hits::total          54188                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data          163                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total          163                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data          107                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total          107                       # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data           55                       # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data          270                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total           270                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data          270                       # number of overall misses
system.cpu1.dcache.overall_misses::total          270                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      2920000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total      2920000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2149500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total      2149500                       # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       245500                       # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total       245500                       # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data      5069500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total      5069500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data      5069500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total      5069500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data        41257                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total        41257                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data        13201                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total        13201                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data           68                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data        54458                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total        54458                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data        54458                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total        54458                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003951                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.003951                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.008105                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.008105                       # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.808824                       # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total     0.808824                       # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.004958                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.004958                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.004958                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.004958                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047                       # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4463.636364                       # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total  4463.636364                       # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          163                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           55                       # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data          270                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data          270                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2757000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2757000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      2042500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total      2042500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       190500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total       190500                       # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4799500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total      4799500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4799500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total      4799500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003951                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003951                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.008105                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.008105                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.808824                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.808824                       # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.004958                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.004958                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.004958                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.004958                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047                       # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  3463.636364                       # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  3463.636364                       # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926                       # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements              280                       # number of replacements
system.cpu1.icache.tags.tagsinuse           67.000483                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs             168496                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs           460.371585                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst    67.000483                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.130860                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.130860                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses           169228                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses          169228                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst       168496                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         168496                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst       168496                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          168496                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst       168496                       # number of overall hits
system.cpu1.icache.overall_hits::total         168496                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
system.cpu1.icache.overall_misses::total          366                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      5681500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total      5681500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst      5681500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total      5681500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst      5681500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total      5681500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst       168862                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total       168862                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst       168862                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total       168862                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst       168862                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total       168862                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002167                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.002167                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002167                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.002167                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002167                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.002167                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15523.224044                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15523.224044                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks          280                       # number of writebacks
system.cpu1.icache.writebacks::total              280                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst          366                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5315500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total      5315500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5315500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total      5315500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5315500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total      5315500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002167                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002167                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002167                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.002167                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002167                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.002167                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.numCycles                          529681                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                     165415                       # Number of instructions committed
system.cpu2.committedOps                       165415                       # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses               110386                       # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
system.cpu2.num_conditional_control_insts        31522                       # number of instructions that are conditional controls
system.cpu2.num_int_insts                      110386                       # number of integer instructions
system.cpu2.num_fp_insts                            0                       # number of float instructions
system.cpu2.num_int_register_reads             277687                       # number of times the integer registers were read
system.cpu2.num_int_register_writes            105904                       # number of times the integer registers were written
system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu2.num_mem_refs                        55033                       # number of memory refs
system.cpu2.num_load_insts                      40858                       # Number of load instructions
system.cpu2.num_store_insts                     14175                       # Number of store instructions
system.cpu2.num_idle_cycles              74150.001720                       # Number of idle cycles
system.cpu2.num_busy_cycles              455530.998280                       # Number of busy cycles
system.cpu2.not_idle_fraction                0.860010                       # Percentage of non-idle cycles
system.cpu2.idle_fraction                    0.139990                       # Percentage of idle cycles
system.cpu2.Branches                            33177                       # Number of branches fetched
system.cpu2.op_class::No_OpClass                23956     14.48%     14.48% # Class of executed instruction
system.cpu2.op_class::IntAlu                    74457     45.00%     59.48% # Class of executed instruction
system.cpu2.op_class::IntMult                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::IntDiv                        0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatAdd                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatCmp                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatCvt                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatMult                     0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatDiv                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::FloatSqrt                     0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdAdd                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdAlu                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdCmp                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdCvt                       0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdMisc                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdMult                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdShift                     0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdSqrt                      0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.48% # Class of executed instruction
system.cpu2.op_class::MemRead                   52859     31.95%     91.43% # Class of executed instruction
system.cpu2.op_class::MemWrite                  14175      8.57%    100.00% # Class of executed instruction
system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu2.op_class::total                    165447                       # Class of executed instruction
system.cpu2.dcache.tags.replacements                0                       # number of replacements
system.cpu2.dcache.tags.tagsinuse           27.486829                       # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs              30625                       # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs          1056.034483                       # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data    27.486829                       # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data     0.053685                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total     0.053685                       # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses           220352                       # Number of tag accesses
system.cpu2.dcache.tags.data_accesses          220352                       # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data        40687                       # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total          40687                       # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data        13994                       # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total         13994                       # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data        54681                       # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total           54681                       # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data        54681                       # number of overall hits
system.cpu2.dcache.overall_hits::total          54681                       # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data          163                       # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total          163                       # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data          108                       # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data           58                       # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data          271                       # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total           271                       # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data          271                       # number of overall misses
system.cpu2.dcache.overall_misses::total          271                       # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      3093500                       # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total      3093500                       # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2328000                       # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total      2328000                       # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       260500                       # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total       260500                       # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data      5421500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total      5421500                       # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data      5421500                       # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total      5421500                       # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data        40850                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total        40850                       # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data        14102                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total        14102                       # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data           71                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data        54952                       # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total        54952                       # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data        54952                       # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total        54952                       # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003990                       # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total     0.003990                       # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.007658                       # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total     0.007658                       # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.816901                       # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total     0.816901                       # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004932                       # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total     0.004932                       # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004932                       # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total     0.004932                       # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607                       # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607                       # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556                       # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556                       # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  4491.379310                       # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total  4491.379310                       # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055                       # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055                       # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055                       # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          163                       # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          108                       # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           58                       # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data          271                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total          271                       # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data          271                       # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total          271                       # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2930500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2930500                       # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      2220000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total      2220000                       # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       202500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total       202500                       # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      5150500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total      5150500                       # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      5150500                       # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total      5150500                       # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003990                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003990                       # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.007658                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.007658                       # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.816901                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.816901                       # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004932                       # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total     0.004932                       # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004932                       # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total     0.004932                       # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607                       # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607                       # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556                       # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556                       # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  3491.379310                       # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  3491.379310                       # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055                       # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055                       # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055                       # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu2.icache.tags.replacements              280                       # number of replacements
system.cpu2.icache.tags.tagsinuse           69.407713                       # Cycle average of tags in use
system.cpu2.icache.tags.total_refs             165082                       # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs           451.043716                       # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst    69.407713                       # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst     0.135562                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total     0.135562                       # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses           165814                       # Number of tag accesses
system.cpu2.icache.tags.data_accesses          165814                       # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst       165082                       # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total         165082                       # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst       165082                       # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total          165082                       # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst       165082                       # number of overall hits
system.cpu2.icache.overall_hits::total         165082                       # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
system.cpu2.icache.overall_misses::total          366                       # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      8101000                       # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total      8101000                       # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst      8101000                       # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total      8101000                       # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst      8101000                       # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total      8101000                       # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst       165448                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total       165448                       # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst       165448                       # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total       165448                       # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst       165448                       # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total       165448                       # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002212                       # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total     0.002212                       # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002212                       # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total     0.002212                       # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002212                       # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total     0.002212                       # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781                       # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781                       # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781                       # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 22133.879781                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781                       # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 22133.879781                       # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
system.cpu2.icache.writebacks::writebacks          280                       # number of writebacks
system.cpu2.icache.writebacks::total              280                       # number of writebacks
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst          366                       # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      7735000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total      7735000                       # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      7735000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total      7735000                       # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      7735000                       # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total      7735000                       # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002212                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002212                       # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002212                       # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total     0.002212                       # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002212                       # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total     0.002212                       # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781                       # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781                       # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781                       # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781                       # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781                       # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.numCycles                          529680                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.committedInsts                     169884                       # Number of instructions committed
system.cpu3.committedOps                       169884                       # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses               110793                       # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
system.cpu3.num_conditional_control_insts        33553                       # number of instructions that are conditional controls
system.cpu3.num_int_insts                      110793                       # number of integer instructions
system.cpu3.num_fp_insts                            0                       # number of float instructions
system.cpu3.num_int_register_reads             271193                       # number of times the integer registers were read
system.cpu3.num_int_register_writes            102450                       # number of times the integer registers were written
system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu3.num_mem_refs                        53409                       # number of memory refs
system.cpu3.num_load_insts                      41060                       # Number of load instructions
system.cpu3.num_store_insts                     12349                       # Number of store instructions
system.cpu3.num_idle_cycles              74420.861217                       # Number of idle cycles
system.cpu3.num_busy_cycles              455259.138783                       # Number of busy cycles
system.cpu3.not_idle_fraction                0.859498                       # Percentage of non-idle cycles
system.cpu3.idle_fraction                    0.140502                       # Percentage of idle cycles
system.cpu3.Branches                            35208                       # Number of branches fetched
system.cpu3.op_class::No_OpClass                25987     15.29%     15.29% # Class of executed instruction
system.cpu3.op_class::IntAlu                    74660     43.94%     59.23% # Class of executed instruction
system.cpu3.op_class::IntMult                       0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::IntDiv                        0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::FloatAdd                      0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::FloatCmp                      0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::FloatCvt                      0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::FloatMult                     0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::FloatDiv                      0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::FloatSqrt                     0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdAdd                       0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdAddAcc                    0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdAlu                       0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdCmp                       0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdCvt                       0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdMisc                      0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdMult                      0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdMultAcc                   0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdShift                     0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdShiftAcc                  0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdSqrt                      0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdFloatAdd                  0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdFloatAlu                  0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdFloatCmp                  0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdFloatCvt                  0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdFloatDiv                  0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdFloatMisc                 0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdFloatMult                 0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     59.23% # Class of executed instruction
system.cpu3.op_class::MemRead                   56920     33.50%     92.73% # Class of executed instruction
system.cpu3.op_class::MemWrite                  12349      7.27%    100.00% # Class of executed instruction
system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu3.op_class::total                    169916                       # Class of executed instruction
system.cpu3.dcache.tags.replacements                0                       # number of replacements
system.cpu3.dcache.tags.tagsinuse           25.679518                       # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs              26969                       # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs           929.965517                       # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.679518                       # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data     0.050155                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total     0.050155                       # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses           213856                       # Number of tag accesses
system.cpu3.dcache.tags.data_accesses          213856                       # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data        40892                       # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total          40892                       # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data        12169                       # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total         12169                       # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data        53061                       # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total           53061                       # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data        53061                       # number of overall hits
system.cpu3.dcache.overall_hits::total          53061                       # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data          161                       # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total          161                       # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data          107                       # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total          107                       # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data           57                       # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data          268                       # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total           268                       # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data          268                       # number of overall misses
system.cpu3.dcache.overall_misses::total          268                       # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      2856500                       # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total      2856500                       # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2210000                       # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total      2210000                       # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       258500                       # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total       258500                       # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data      5066500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total      5066500                       # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data      5066500                       # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total      5066500                       # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data        41053                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total        41053                       # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data        12276                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total        12276                       # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data        53329                       # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total        53329                       # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data        53329                       # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total        53329                       # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003922                       # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total     0.003922                       # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.008716                       # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total     0.008716                       # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.802817                       # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total     0.802817                       # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005025                       # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total     0.005025                       # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005025                       # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total     0.005025                       # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025                       # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025                       # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607                       # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607                       # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4535.087719                       # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total  4535.087719                       # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746                       # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746                       # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746                       # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          161                       # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data          268                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data          268                       # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2695500                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2695500                       # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      2103000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total      2103000                       # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       201500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total       201500                       # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4798500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total      4798500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4798500                       # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total      4798500                       # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003922                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003922                       # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.008716                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.008716                       # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.802817                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.802817                       # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.005025                       # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total     0.005025                       # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.005025                       # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total     0.005025                       # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025                       # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025                       # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607                       # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607                       # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  3535.087719                       # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  3535.087719                       # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746                       # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746                       # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746                       # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu3.icache.tags.replacements              281                       # number of replacements
system.cpu3.icache.tags.tagsinuse           64.991831                       # Cycle average of tags in use
system.cpu3.icache.tags.total_refs             169550                       # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs              367                       # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs           461.989101                       # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst    64.991831                       # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst     0.126937                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total     0.126937                       # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses           170284                       # Number of tag accesses
system.cpu3.icache.tags.data_accesses          170284                       # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst       169550                       # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total         169550                       # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst       169550                       # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total          169550                       # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst       169550                       # number of overall hits
system.cpu3.icache.overall_hits::total         169550                       # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total           367                       # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst          367                       # number of overall misses
system.cpu3.icache.overall_misses::total          367                       # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5473500                       # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total      5473500                       # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst      5473500                       # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total      5473500                       # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst      5473500                       # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total      5473500                       # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst       169917                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total       169917                       # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst       169917                       # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total       169917                       # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst       169917                       # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total       169917                       # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002160                       # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total     0.002160                       # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002160                       # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total     0.002160                       # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002160                       # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total     0.002160                       # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937                       # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937                       # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937                       # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 14914.168937                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937                       # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 14914.168937                       # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
system.cpu3.icache.writebacks::writebacks          281                       # number of writebacks
system.cpu3.icache.writebacks::total              281                       # number of writebacks
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst          367                       # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst          367                       # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5106500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total      5106500                       # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5106500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total      5106500                       # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5106500                       # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total      5106500                       # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002160                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002160                       # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002160                       # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total     0.002160                       # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002160                       # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total     0.002160                       # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937                       # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937                       # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937                       # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937                       # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937                       # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                        0                       # number of replacements
system.l2c.tags.tagsinuse                  347.318197                       # Cycle average of tags in use
system.l2c.tags.total_refs                       1714                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                      429                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.995338                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks       0.882018                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      230.794628                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data       54.021394                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst        6.166785                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data        0.835671                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst       46.779239                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data        6.090035                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst        0.944334                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data        0.804093                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.000013                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.003522                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.000824                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.000094                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.000013                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.000714                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.000093                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.000014                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.000012                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.005300                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          429                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          374                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.006546                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                    19669                       # Number of tag accesses
system.l2c.tags.data_accesses                   19669                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total               1                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks          495                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total             495                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst           182                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst           352                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst           301                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst           357                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total              1192                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data            9                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data            3                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data            9                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total               26                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                 352                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst                 301                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data                   3                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst                 357                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
system.l2c.demand_hits::total                    1218                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
system.l2c.overall_hits::cpu1.inst                352                       # number of overall hits
system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
system.l2c.overall_hits::cpu2.inst                301                       # number of overall hits
system.l2c.overall_hits::cpu2.data                  3                       # number of overall hits
system.l2c.overall_hits::cpu3.inst                357                       # number of overall hits
system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
system.l2c.overall_hits::total                   1218                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data            15                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data            17                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data            16                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                76                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data             14                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data             15                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst          285                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst           14                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst           65                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst           10                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total             374                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data           66                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data            8                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total             78                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst                14                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data                16                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst                65                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data                23                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst                10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
system.l2c.demand_misses::total                   594                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
system.l2c.overall_misses::cpu1.inst               14                       # number of overall misses
system.l2c.overall_misses::cpu1.data               16                       # number of overall misses
system.l2c.overall_misses::cpu2.inst               65                       # number of overall misses
system.l2c.overall_misses::cpu2.data               23                       # number of overall misses
system.l2c.overall_misses::cpu3.inst               10                       # number of overall misses
system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
system.l2c.overall_misses::total                  594                       # number of overall misses
system.l2c.ReadExReq_miss_latency::cpu0.data      5892000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data       842000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data       896000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data       840000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total      8470000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst     16964000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst       821500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst      3820000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst       553500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total     22159000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data      3927500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data       118500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data       476000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data       118000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total      4640000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst     16964000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data      9819500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst       821500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data       960500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst      3820000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data      1372000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst       553500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data       958000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total        35269000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst     16964000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data      9819500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst       821500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data       960500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst      3820000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data      1372000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst       553500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data       958000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total       35269000                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks          495                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total          495                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data           15                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data           16                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              78                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data           14                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data           15                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst          467                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst          366                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst          366                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst          367                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total          1566                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data           71                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data           11                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data           11                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data           11                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total          104                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst             366                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data              26                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst             367                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total                1812                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst            366                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data             26                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.974359                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.610278                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.038251                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.177596                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.027248                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.238825                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.929577                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.181818                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.727273                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.181818                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.750000                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.038251                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.640000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.177596                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.884615                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.027248                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.640000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.327815                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.038251                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.640000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.177596                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.884615                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.027248                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.327815                       # miss rate for overall accesses
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 59515.151515                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 60142.857143                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 59733.333333                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data        60000                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 59647.887324                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59522.807018                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 58678.571429                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58769.230769                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst        55350                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 59248.663102                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 59507.575758                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data        59250                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        59500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        59000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 59487.179487                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 59522.807018                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 59512.121212                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 58678.571429                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 60031.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 58769.230769                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 59652.173913                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst        55350                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data        59875                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 59375.420875                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 59522.807018                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 59512.121212                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 58678.571429                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 60031.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 58769.230769                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 59652.173913                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst        55350                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data        59875                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 59375.420875                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            7                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            7                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            6                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total           20                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 22                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                22                       # number of overall MSHR hits
system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data           15                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data           17                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data           16                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           76                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data           14                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data           15                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          285                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst            7                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           58                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            4                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total          354                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data           66                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data            8                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total           76                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst           58                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data           23                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst           58                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data           23                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1418500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       762498                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       864497                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       813997                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      3859492                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4902000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       702000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       746000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       700000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total      7050000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     14114000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst       351500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      2872000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       199000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total     17536500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      3267500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data        49500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       396000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data        49500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total      3762500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst     14114000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data      8169500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst       351500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data       751500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst      2872000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data      1142000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst       199000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data       749500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total     28349000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst     14114000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data      8169500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst       351500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data       751500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst      2872000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data      1142000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst       199000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data       749500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total     28349000                       # number of overall MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.974359                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.158470                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.010899                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.226054                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.090909                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.727273                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.090909                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.730769                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.158470                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.010899                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.158470                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.010899                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50660.714286                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 50833.200000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 50852.764706                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 50874.812500                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 50782.789474                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49515.151515                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50142.857143                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49733.333333                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        50000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 49647.887324                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49522.807018                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50214.285714                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49517.241379                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        49750                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49538.135593                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data        49500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        49500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        49500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49522.807018                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50214.285714                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data        50100                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49517.241379                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49652.173913                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        49750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49966.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 49561.188811                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49522.807018                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50214.285714                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data        50100                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49517.241379                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49652.173913                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        49750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49966.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 49561.188811                       # average overall mshr miss latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp                430                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              271                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              76                       # Transaction distribution
system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
system.membus.trans_dist::ReadExResp              142                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           430                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1557                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                   1557                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        36608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   36608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              261                       # Total snoops (count)
system.membus.snoop_fanout::samples               915                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     915    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 915                       # Request fanout histogram
system.membus.reqLayer0.occupancy              677632                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2936000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests         3980                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests         1113                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         1865                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadResp              2221                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean          495                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq             273                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp            273                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq              428                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp             428                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq          1566                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq          655                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1077                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          579                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          849                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          365                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          849                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          372                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          852                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          366                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                  5309                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39040                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        10944                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        30912                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        30912                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        31040                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total                 147712                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                            1032                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples             2922                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.269678                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.154527                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                   1002     34.29%     34.29% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                    787     26.93%     61.23% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    476     16.29%     77.52% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                    657     22.48%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total               2922                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy            3050992                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              1.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy            700999                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy            495500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy            552489                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy            432972                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy            552491                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy            434474                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy            553492                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy            427974                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------