blob: df50fe29d42f02f4ff649e04a80ece2f52a45fb3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000262 # Number of seconds simulated
sim_ticks 261623500 # Number of ticks simulated
final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 776063 # Simulator instruction rate (inst/s)
host_op_rate 776047 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 307506962 # Simulator tick rate (ticks/s)
host_mem_usage 231300 # Number of bytes of host memory used
host_seconds 0.85 # Real time elapsed on the host
sim_insts 660239 # Number of instructions simulated
sim_ops 660239 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory
system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory
system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 523247 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 158010 # Number of instructions committed
system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls
system.cpu0.num_int_insts 108832 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read
system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 73739 # number of memory refs
system.cpu0.num_load_insts 48819 # Number of load instructions
system.cpu0.num_store_insts 24920 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
system.cpu0.num_busy_cycles 523247 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 215 # number of replacements
system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use
system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits
system.cpu0.icache.overall_hits::total 157606 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
system.cpu0.icache.overall_misses::total 467 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 2 # number of replacements
system.cpu0.dcache.tagsinuse 145.601248 # Cycle average of tags in use
system.cpu0.dcache.total_refs 73215 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 438.413174 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 145.601248 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.284377 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.284377 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 48647 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 48647 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 24686 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 24686 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 73333 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 73333 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 73333 # number of overall hits
system.cpu0.dcache.overall_hits::total 73333 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses
system.cpu0.dcache.overall_misses::total 345 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4649500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7005000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 7005000 # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 363500 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 363500 # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 11654500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 11654500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 11654500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 11654500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 48809 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 48809 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 24869 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 24869 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 73678 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 73678 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 73678 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 73678 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003319 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.003319 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007359 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.007359 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004683 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.004683 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004683 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4325500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6639000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6639000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10964500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003319 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003319 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007359 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007359 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.004683 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.004683 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26700.617284 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26700.617284 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36278.688525 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36278.688525 # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11980.769231 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 523247 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 173283 # Number of instructions committed
system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 637 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls
system.cpu1.num_int_insts 108736 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read
system.cpu1.num_int_register_writes 93825 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 48621 # number of memory refs
system.cpu1.num_load_insts 40031 # Number of load instructions
system.cpu1.num_store_insts 8590 # Number of store instructions
system.cpu1.num_idle_cycles 68750.001737 # Number of idle cycles
system.cpu1.num_busy_cycles 454496.998263 # Number of busy cycles
system.cpu1.not_idle_fraction 0.868609 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.131391 # Percentage of idle cycles
system.cpu1.icache.replacements 280 # number of replacements
system.cpu1.icache.tagsinuse 65.593035 # Cycle average of tags in use
system.cpu1.icache.total_refs 172950 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 472.540984 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 65.593035 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.128111 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.128111 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 172950 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 172950 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 172950 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 172950 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 172950 # number of overall hits
system.cpu1.icache.overall_hits::total 172950 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
system.cpu1.icache.overall_misses::total 366 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5373500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5373500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5373500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5373500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5373500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5373500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 173316 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 173316 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 173316 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 173316 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 173316 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 173316 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002112 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.002112 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002112 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.002112 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002112 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.002112 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14681.693989 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14681.693989 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14681.693989 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14681.693989 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4641500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4641500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4641500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 4641500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4641500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 4641500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.002112 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.002112 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.693989 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 0 # number of replacements
system.cpu1.dcache.tagsinuse 25.918058 # Cycle average of tags in use
system.cpu1.dcache.total_refs 19532 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 651.066667 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 25.918058 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.050621 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.050621 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 39847 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 39847 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 8412 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 8412 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 48259 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 48259 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 48259 # number of overall hits
system.cpu1.dcache.overall_hits::total 48259 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 177 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 177 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses
system.cpu1.dcache.overall_misses::total 282 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3316000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3316000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1875500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 1875500 # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 659500 # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total 659500 # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 5191500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 5191500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 5191500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 5191500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 40024 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 40024 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 8517 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 8517 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 48541 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 48541 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 48541 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 48541 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004422 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.004422 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012328 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.012328 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.774648 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.774648 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005810 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.005810 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005810 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.005810 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18734.463277 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 18734.463277 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17861.904762 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17861.904762 # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11990.909091 # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 11990.909091 # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18409.574468 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18409.574468 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 177 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 282 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 282 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 282 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 282 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2962000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2962000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1665500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 549500 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4627500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4627500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4627500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004422 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012328 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012328 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.005810 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.005810 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 9990.909091 # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.numCycles 523246 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 160665 # Number of instructions committed
system.cpu2.committedOps 160665 # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses 113639 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu2.num_func_calls 637 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 27518 # number of instructions that are conditional controls
system.cpu2.num_int_insts 113639 # number of integer instructions
system.cpu2.num_fp_insts 0 # number of float instructions
system.cpu2.num_int_register_reads 306682 # number of times the integer registers were read
system.cpu2.num_int_register_writes 118721 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu2.num_mem_refs 62290 # number of memory refs
system.cpu2.num_load_insts 42488 # Number of load instructions
system.cpu2.num_store_insts 19802 # Number of store instructions
system.cpu2.num_idle_cycles 69015.869837 # Number of idle cycles
system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles
system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles
system.cpu2.icache.replacements 281 # number of replacements
system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use
system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst 67.731754 # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst 0.132289 # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total 0.132289 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 160331 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 160331 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 160331 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 160331 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 160331 # number of overall hits
system.cpu2.icache.overall_hits::total 160331 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses
system.cpu2.icache.overall_misses::total 367 # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5321500 # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total 5321500 # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst 5321500 # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total 5321500 # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst 5321500 # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total 5321500 # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst 160698 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 160698 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 160698 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 160698 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 160698 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 160698 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002284 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.002284 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002284 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.002284 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002284 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.002284 # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14500 # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14500 # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14500 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 367 # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4587500 # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total 4587500 # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4587500 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total 4587500 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4587500 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total 4587500 # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002284 # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12500 # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12500 # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 0 # number of replacements
system.cpu2.dcache.tagsinuse 26.833050 # Cycle average of tags in use
system.cpu2.dcache.total_refs 41851 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 1443.137931 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data 26.833050 # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data 0.052408 # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total 0.052408 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 42328 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 42328 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 19626 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 19626 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 61954 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 61954 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 61954 # number of overall hits
system.cpu2.dcache.overall_hits::total 61954 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 106 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 106 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 258 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 258 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 258 # number of overall misses
system.cpu2.dcache.overall_misses::total 258 # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1938000 # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total 1938000 # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2155000 # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total 2155000 # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 612500 # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total 612500 # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data 4093000 # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total 4093000 # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data 4093000 # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total 4093000 # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42480 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 42480 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 19732 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 19732 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 62212 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 62212 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 62212 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 62212 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003578 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.003578 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005372 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.005372 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.852941 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004147 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.004147 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004147 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.004147 # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12750 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 12750 # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20330.188679 # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 20330.188679 # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10560.344828 # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 10560.344828 # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 15864.341085 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 15864.341085 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data 258 # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 258 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1634000 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1634000 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1943000 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1943000 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 496500 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 496500 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3577000 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total 3577000 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3577000 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total 3577000 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003578 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003578 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005372 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005372 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.852941 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total 0.004147 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.004147 # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10750 # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10750 # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18330.188679 # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18330.188679 # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8560.344828 # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8560.344828 # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.numCycles 523246 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.committedInsts 168281 # Number of instructions committed
system.cpu3.committedOps 168281 # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses 108796 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 637 # number of times a function call or return occured
system.cpu3.num_conditional_control_insts 33752 # number of instructions that are conditional controls
system.cpu3.num_int_insts 108796 # number of integer instructions
system.cpu3.num_fp_insts 0 # number of float instructions
system.cpu3.num_int_register_reads 262371 # number of times the integer registers were read
system.cpu3.num_int_register_writes 98980 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu3.num_mem_refs 51213 # number of memory refs
system.cpu3.num_load_insts 40064 # Number of load instructions
system.cpu3.num_store_insts 11149 # Number of store instructions
system.cpu3.num_idle_cycles 69253.869381 # Number of idle cycles
system.cpu3.num_busy_cycles 453992.130619 # Number of busy cycles
system.cpu3.not_idle_fraction 0.867646 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0.132354 # Percentage of idle cycles
system.cpu3.icache.replacements 280 # number of replacements
system.cpu3.icache.tagsinuse 70.063196 # Cycle average of tags in use
system.cpu3.icache.total_refs 167948 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 458.874317 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst 70.063196 # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst 0.136842 # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total 0.136842 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 167948 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 167948 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 167948 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 167948 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 167948 # number of overall hits
system.cpu3.icache.overall_hits::total 167948 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 366 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 366 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 366 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 366 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 366 # number of overall misses
system.cpu3.icache.overall_misses::total 366 # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7343000 # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total 7343000 # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst 7343000 # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total 7343000 # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst 7343000 # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total 7343000 # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst 168314 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 168314 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 168314 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 168314 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 168314 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 168314 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002175 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002175 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002175 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 20062.841530 # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 20062.841530 # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 20062.841530 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 20062.841530 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 366 # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst 366 # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 366 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6611000 # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total 6611000 # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6611000 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total 6611000 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6611000 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total 6611000 # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 18062.841530 # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 0 # number of replacements
system.cpu3.dcache.tagsinuse 27.713697 # Cycle average of tags in use
system.cpu3.dcache.total_refs 24536 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 846.068966 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data 27.713697 # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data 0.054128 # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total 0.054128 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 39885 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 39885 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 10974 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 10974 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 50859 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 50859 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 50859 # number of overall hits
system.cpu3.dcache.overall_hits::total 50859 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 172 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 172 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 104 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 104 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 276 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 276 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 276 # number of overall misses
system.cpu3.dcache.overall_misses::total 276 # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3405000 # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total 3405000 # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1971500 # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total 1971500 # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 653500 # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total 653500 # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data 5376500 # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total 5376500 # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data 5376500 # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total 5376500 # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data 40057 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 40057 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 11078 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 11078 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 69 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 51135 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 51135 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 51135 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 51135 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004294 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.004294 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009388 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.009388 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797101 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005397 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.005397 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005397 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.005397 # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 19796.511628 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 19796.511628 # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18956.730769 # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 18956.730769 # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11881.818182 # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 11881.818182 # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 19480.072464 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 19480.072464 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data 276 # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 276 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3061000 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3061000 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1763500 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1763500 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 543500 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 543500 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4824500 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total 4824500 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4824500 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total 4824500 # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004294 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004294 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009388 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009388 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797101 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total 0.005397 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.005397 # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17796.511628 # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17796.511628 # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16956.730769 # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16956.730769 # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9881.818182 # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9881.818182 # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
system.l2c.tagsinuse 349.154335 # Cycle average of tags in use
system.l2c.total_refs 1221 # Total number of references to valid blocks.
system.l2c.sampled_refs 429 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.846154 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 0.889459 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 231.842883 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 54.217473 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 6.219466 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 0.812784 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 1.917796 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 0.863537 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst 46.262373 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data 6.128563 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst 0.000706 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data 0.000094 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.005328 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst 306 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data 3 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1221 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 306 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 3 # number of demand (read+write) hits
system.l2c.demand_hits::total 1221 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 352 # number of overall hits
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
system.l2c.overall_hits::cpu3.inst 306 # number of overall hits
system.l2c.overall_hits::cpu3.data 3 # number of overall hits
system.l2c.overall_hits::total 1221 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst 60 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data 8 # number of ReadReq misses
system.l2c.ReadReq_misses::total 449 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 85 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 15 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 60 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 23 # number of demand (read+write) misses
system.l2c.demand_misses::total 591 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
system.l2c.overall_misses::cpu1.inst 14 # number of overall misses
system.l2c.overall_misses::cpu1.data 16 # number of overall misses
system.l2c.overall_misses::cpu2.inst 12 # number of overall misses
system.l2c.overall_misses::cpu2.data 16 # number of overall misses
system.l2c.overall_misses::cpu3.inst 60 # number of overall misses
system.l2c.overall_misses::cpu3.data 23 # number of overall misses
system.l2c.overall_misses::total 591 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 14917500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 3451000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 697500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 100000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 601000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 104500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst 3071500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data 410000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 23353000 # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 5169500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 736000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 737500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 793500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7436500 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 14917500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 8620500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 697500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 836000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 601000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 842000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 3071500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data 1203500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 30789500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 14917500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 8620500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 697500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 836000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 601000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 842000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 3071500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 1203500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 30789500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 367 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst 366 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 87 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 15 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 367 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 366 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 367 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 366 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.032698 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.163934 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.727273 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.268862 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.977011 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.032698 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.163934 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.884615 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.326159 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.032698 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.163934 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.884615 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.326159 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52342.105263 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52287.878788 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49821.428571 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 50000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 50083.333333 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 52250 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51191.666667 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data 51250 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52011.135857 # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52217.171717 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52571.428571 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52678.571429 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52900 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52369.718310 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52342.105263 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52245.454545 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 49821.428571 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52250 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 50083.333333 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 52625 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 51191.666667 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 52326.086957 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52097.292724 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52342.105263 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52245.454545 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 49821.428571 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 50083.333333 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 52625 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 51191.666667 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 52326.086957 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52097.292724 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst 7 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst 7 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 7 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 9 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 2 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst 53 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data 7 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 85 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 15 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 9 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 16 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 53 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 22 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 9 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 16 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 53 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 22 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11406500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 282500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 360000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 80000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 2120000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 280000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 17209000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1124491 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 722495 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 800000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 761996 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 3408982 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 565000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 566500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 609500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5701000 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 11406500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 282500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 605000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 360000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 646500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 2120000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 889500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 22910000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 11406500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 282500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 605000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 360000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 646500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 2120000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 889500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 22910000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.636364 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.977011 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.930233 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40138.611111 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40105.052632 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40105.670588 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40357.142857 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40464.285714 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40633.333333 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40147.887324 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|