path: root/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000653                       # Number of seconds simulated
sim_ticks                                   652606500                       # Number of ticks simulated
final_tick                                  652606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                              176079756                       # Simulator tick rate (ticks/s)
host_mem_usage                                 355636                       # Number of bytes of host memory used
host_seconds                                     3.71                       # Real time elapsed on the host
system.physmem.bytes_read::cpu0                 80014                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                 82049                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                 81047                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                 79011                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                 80501                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                 83900                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                 78451                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                 80299                       # Number of bytes read from this memory
system.physmem.bytes_read::total               645272                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks       398848                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5221                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5261                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5379                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5376                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5284                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5253                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5355                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5238                       # Number of bytes written to this memory
system.physmem.bytes_written::total            441215                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  10966                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  11048                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  10991                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  11034                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  11075                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  11072                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  10915                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  11125                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 88226                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            6232                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5221                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5261                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5376                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5284                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5253                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5355                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5238                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                48599                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                122606808                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                125725073                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                124189692                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                121069894                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                123353047                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                128561392                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                120211797                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                123043519                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               988761221                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         611161550                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                 8000227                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                 8061519                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                 8242333                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                 8237736                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                 8096763                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                 8049261                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                 8205557                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                 8026276                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              676081222                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         611161550                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0               130607035                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1               133786593                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2               132432025                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3               129307630                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4               131449809                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5               136610653                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6               128417354                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7               131069795                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1664842443                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                   1664833249                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               85134                       # Transaction distribution
system.membus.trans_dist::ReadResp              85128                       # Transaction distribution
system.membus.trans_dist::WriteReq              42367                       # Transaction distribution
system.membus.trans_dist::WriteResp             42365                       # Transaction distribution
system.membus.trans_dist::Writeback              6232                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            57414                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           46744                       # Transaction distribution
system.membus.trans_dist::ReadExReq             48586                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3092                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side       417062                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count                        417062                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side      1086481                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size                    1086481                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                1086481                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           286485584                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization              43.9                       # Layer utilization (%)
system.membus.respLayer0.occupancy          311361500                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization             47.7                       # Layer utilization (%)
system.l2c.tags.replacements                         13254                       # number of replacements
system.l2c.tags.tagsinuse                       783.820018                       # Cycle average of tags in use
system.l2c.tags.total_refs                          149317                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                         14065                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                         10.616210                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks          726.472153                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0                  7.679894                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1                  7.566050                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2                  7.311161                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3                  6.856177                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4                  7.195523                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5                  6.988954                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6                  6.739476                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7                  7.010629                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks           0.709445                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0                 0.007500                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1                 0.007389                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2                 0.007140                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3                 0.006695                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4                 0.007027                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5                 0.006825                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6                 0.006582                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7                 0.006846                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total                0.765449                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0                   10635                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1                   10552                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2                   10744                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3                   10808                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4                   10723                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5                   10748                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6                   10725                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7                   10838                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  85773                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks           74336                       # number of Writeback hits
system.l2c.Writeback_hits::total                74336                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0                  332                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  322                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  337                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  354                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  332                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  353                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  349                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  378                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2757                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  1930                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  1860                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  1868                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  1850                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  1871                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  1809                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  1953                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  1858                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                14999                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0                    12565                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    12412                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    12612                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    12658                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    12594                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    12557                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    12678                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    12696                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  100772                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   12565                       # number of overall hits
system.l2c.overall_hits::cpu1                   12412                       # number of overall hits
system.l2c.overall_hits::cpu2                   12612                       # number of overall hits
system.l2c.overall_hits::cpu3                   12658                       # number of overall hits
system.l2c.overall_hits::cpu4                   12594                       # number of overall hits
system.l2c.overall_hits::cpu5                   12557                       # number of overall hits
system.l2c.overall_hits::cpu6                   12678                       # number of overall hits
system.l2c.overall_hits::cpu7                   12696                       # number of overall hits
system.l2c.overall_hits::total                 100772                       # number of overall hits
system.l2c.ReadReq_misses::cpu0                   751                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1                   742                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2                   744                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3                   696                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4                   727                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5                   735                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6                   708                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7                   698                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 5801                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0               1964                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               1929                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               1920                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               1880                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               1830                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               1887                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               1921                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               1963                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             15294                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4321                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4353                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4358                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4233                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4361                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4404                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4224                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4317                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              34571                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0                   5072                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   5095                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   5102                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   4929                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   5088                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   5139                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   4932                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   5015                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 40372                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  5072                       # number of overall misses
system.l2c.overall_misses::cpu1                  5095                       # number of overall misses
system.l2c.overall_misses::cpu2                  5102                       # number of overall misses
system.l2c.overall_misses::cpu3                  4929                       # number of overall misses
system.l2c.overall_misses::cpu4                  5088                       # number of overall misses
system.l2c.overall_misses::cpu5                  5139                       # number of overall misses
system.l2c.overall_misses::cpu6                  4932                       # number of overall misses
system.l2c.overall_misses::cpu7                  5015                       # number of overall misses
system.l2c.overall_misses::total                40372                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0        46656500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1        45888000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2        46214500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3        43225999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4        45481000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5        44732500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6        43604500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7        43142000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      358944999                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0     54482000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     56107500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     54698000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     55749000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     51718500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     55828000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     55452500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     58605500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    442641000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     232354499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     234531000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     234959000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     228552499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     234872500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     237965000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     227719000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     232651999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1863605497                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0        279010999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        280419000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        281173500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        271778498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        280353500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        282697500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        271323500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        275793999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2222550496                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       279010999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       280419000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       281173500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       271778498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       280353500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       282697500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       271323500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       275793999                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2222550496                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0               11386                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1               11294                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2               11488                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3               11504                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4               11450                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5               11483                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6               11433                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7               11536                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              91574                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks        74336                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total            74336                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2296                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2251                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2257                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2234                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2162                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2240                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2270                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2341                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           18051                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6251                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6213                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6226                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6083                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6232                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6213                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6177                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6175                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            49570                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                17637                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                17507                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                17714                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                17587                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                17682                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                17696                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                17610                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                17711                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              141144                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               17637                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               17507                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               17714                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               17587                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               17682                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               17696                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               17610                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               17711                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             141144                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0           0.065958                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1           0.065699                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2           0.064763                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3           0.060501                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4           0.063493                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5           0.064008                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6           0.061926                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7           0.060506                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.063348                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.855401                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.856952                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.850687                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.841540                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.846438                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.842411                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.846256                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.838531                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.847266                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.691249                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.700628                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.699968                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.695874                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.699775                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.708836                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.683827                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.699109                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.697418                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0            0.287577                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.291026                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.288021                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.280264                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.287750                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.290405                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.280068                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.283157                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.286034                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.287577                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.291026                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.288021                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.280264                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.287750                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.290405                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.280068                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.283157                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.286034                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 62125.832224                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 61843.665768                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 62116.263441                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 62106.320402                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 62559.834938                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 60860.544218                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 61588.276836                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 61808.022923                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 61876.400448                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 27740.325866                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 29086.314152                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 28488.541667                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 29653.723404                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 28261.475410                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 29585.585586                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 28866.475794                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 29855.068772                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 28942.134170                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 53773.316131                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 53878.015162                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 53914.410280                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 53993.030711                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 53857.486815                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 54033.832879                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 53910.748106                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 53892.054436                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53906.612392                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 55010.055008                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 55038.076546                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 55110.446884                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 55138.668695                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 55100.923742                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 55010.215995                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 55012.875101                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 54993.818345                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 55051.780838                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 55010.055008                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 55038.076546                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 55110.446884                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 55138.668695                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 55100.923742                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 55010.215995                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 55012.875101                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 54993.818345                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 55051.780838                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             13487                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                     1906                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      7.076076                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks                6233                       # number of writebacks
system.l2c.writebacks::total                     6233                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0                  6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1                  8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2                  8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3                  3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4                  6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5                  4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6                  5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7                  5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                45                       # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total              2                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5                6                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total              30                       # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                   9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                  11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                  11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                   6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                  11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                  10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                   9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                   8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 75                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                  9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                 11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                 11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                  6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                 11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                 10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                  9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                  8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                75                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0              745                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1              734                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2              736                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3              693                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4              721                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5              731                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6              703                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7              693                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            5756                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          1963                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          1929                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          1920                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          1879                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          1830                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          1887                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          1921                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          1963                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        15292                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4318                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4350                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4355                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4230                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4356                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4398                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4220                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4314                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         34541                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              5063                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              5084                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              5091                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              4923                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              5077                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              5129                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              4923                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              5007                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            40297                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             5063                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             5084                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             5091                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             4923                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             5077                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             5129                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             4923                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             5007                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           40297                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0     37430000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1     36700000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2     36861500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3     34765499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4     36517000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5     35579500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6     34789500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7     34507000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    287149999                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     80503500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     79250000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     78828500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     77220000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     75116000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     77478500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     78872500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     80473500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    627742500                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    179980999                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    181689000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    182122000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    177202499                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    181963000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    184511000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    176480500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    180371999                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1444320997                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    217410999                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    218389000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    218983500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    211967998                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    218480000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    220090500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    211270000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    214878999                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   1731470996                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    217410999                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    218389000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    218983500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    211967998                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    218480000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    220090500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    211270000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    214878999                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   1731470996                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    408599000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    409928000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    408199000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    411446500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    412339500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    409840000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    407063000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    414602500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3282017500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    219448000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    222166000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    226500000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    227574000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    224253000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    222853000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    225951500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    221581000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1790326500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    628047000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    632094000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    634699000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    639020500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    636592500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    632693000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    633014500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    636183500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5072344000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0      0.065431                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1      0.064990                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2      0.064067                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3      0.060240                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4      0.062969                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5      0.063659                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6      0.061489                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7      0.060073                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.062856                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.854965                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.856952                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.850687                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.841092                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.846438                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.842411                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.846256                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.838531                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.847155                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.690769                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.700145                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.699486                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.695381                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.698973                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.707871                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.683180                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.698623                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.696813                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.287067                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.290398                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.287400                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.279923                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.287128                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.289840                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.279557                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.282706                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.285503                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.287067                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.290398                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.287400                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.279923                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.287128                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.289840                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.279557                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.282706                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.285503                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50241.610738                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1        50000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50083.559783                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50166.665224                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50647.711512                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48672.366621                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49487.197724                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49793.650794                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 49887.074183                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41010.443199                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41083.462934                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41056.510417                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41096.327834                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41046.994536                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41059.088500                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41058.042686                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40995.160469                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41050.385823                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41681.565308                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41767.586207                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41819.058553                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41891.843735                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41772.956841                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41953.387904                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41820.023697                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41810.848169                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41814.683912                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 42941.141418                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 42956.136900                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 43013.847967                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 43056.672354                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 43033.287374                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.996296                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 42914.889295                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 42915.717795                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 42967.739435                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 42941.141418                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 42956.136900                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 43013.847967                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 43056.672354                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 43033.287374                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.996296                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 42914.889295                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 42915.717795                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 42967.739435                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.funcbus.throughput                           0                       # Throughput (bytes/s)
system.funcbus.data_through_bus                     0                       # Total data (bytes)
system.toL2Bus.throughput                 51078499831                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq             368070                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            368059                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             42367                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            42365                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback            74336                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           28719                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          28718                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           155928                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          155926                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side       118285                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side       118639                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side       118896                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side       119078                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side       118813                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side       118602                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side       118904                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side       119137                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count                       950354                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side      1731443                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side      1726092                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side      1741657                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side      1748194                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side      1742487                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side      1735937                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side      1741406                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side      1745057                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size                  13912273                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus              13912273                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus        19421888                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy          652560490                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization            100.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         157373515                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization            24.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         158243013                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization            24.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         157858027                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization            24.2                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         157862988                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization            24.2                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy         158148657                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization            24.2                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy         157838676                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization            24.2                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy         158178516                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization            24.2                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy         157763244                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization            24.2                       # Layer utilization (%)
system.cpu0.num_reads                           98977                       # number of read accesses completed
system.cpu0.num_writes                          53590                       # number of write accesses completed
system.cpu0.num_copies                              0                       # number of copy accesses completed
system.cpu0.l1c.tags.replacements                    21970                       # number of replacements
system.cpu0.l1c.tags.tagsinuse                  393.709596                       # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs                      13350                       # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs                    22370                       # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs                     0.596781                       # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0           393.709596                       # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0            0.768964                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total           0.768964                       # Average percentage of cache occupancy
system.cpu0.l1c.ReadReq_hits::cpu0               8685                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8685                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1118                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1118                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9803                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9803                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9803                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9803                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            35704                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           35704                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23289                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23289                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             58993                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            58993                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            58993                       # number of overall misses
system.cpu0.l1c.overall_misses::total           58993                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0    937059642                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total    937059642                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0    866806760                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total    866806760                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   1803866402                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   1803866402                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   1803866402                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   1803866402                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          44389                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         44389                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         24407                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        24407                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           68796                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          68796                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          68796                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         68796                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.804343                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.804343                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.954193                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.954193                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.857506                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.857506                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.857506                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.857506                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26245.228602                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 26245.228602                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37219.578342                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 37219.578342                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 30577.634669                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 30577.634669                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 30577.634669                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 30577.634669                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs      1018391                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               62068                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs    16.407666                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks           9494                       # number of writebacks
system.cpu0.l1c.writebacks::total                9494                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        35704                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        35704                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23289                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23289                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        58993                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        58993                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        58993                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        58993                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    860700776                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total    860700776                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    817560778                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total    817560778                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1678261554                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   1678261554                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1678261554                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   1678261554                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    703193894                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    703193894                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0   1636775658                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total   1636775658                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   2339969552                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   2339969552                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.804343                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.804343                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.954193                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.954193                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.857506                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.857506                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.857506                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.857506                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24106.564419                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24106.564419                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35105.018592                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35105.018592                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28448.486329                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28448.486329                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28448.486329                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28448.486329                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                           99824                       # number of read accesses completed
system.cpu1.num_writes                          53636                       # number of write accesses completed
system.cpu1.num_copies                              0                       # number of copy accesses completed
system.cpu1.l1c.tags.replacements                    22223                       # number of replacements
system.cpu1.l1c.tags.tagsinuse                  395.298418                       # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs                      13436                       # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs                    22630                       # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs                     0.593725                       # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1           395.298418                       # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1            0.772067                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total           0.772067                       # Average percentage of cache occupancy
system.cpu1.l1c.ReadReq_hits::cpu1               8757                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8757                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1135                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1135                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1                9892                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total               9892                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1               9892                       # number of overall hits
system.cpu1.l1c.overall_hits::total              9892                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            36260                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           36260                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           23033                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          23033                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             59293                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            59293                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            59293                       # number of overall misses
system.cpu1.l1c.overall_misses::total           59293                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1    947629716                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total    947629716                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1    858813201                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total    858813201                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   1806442917                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   1806442917                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   1806442917                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   1806442917                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          45017                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         45017                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         24168                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        24168                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           69185                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          69185                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          69185                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         69185                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.805473                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.805473                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.953037                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.953037                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.857021                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.857021                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.857021                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.857021                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26134.299945                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 26134.299945                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 37286.206790                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 37286.206790                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 30466.377431                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 30466.377431                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 30466.377431                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 30466.377431                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs      1020302                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               62395                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs    16.352304                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks           9512                       # number of writebacks
system.cpu1.l1c.writebacks::total                9512                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36260                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        36260                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23033                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        23033                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        59293                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        59293                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        59293                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        59293                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    870111848                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total    870111848                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    810087173                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total    810087173                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1680199021                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   1680199021                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1680199021                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   1680199021                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    702431869                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    702431869                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1   1631991143                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total   1631991143                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   2334423012                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   2334423012                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.805473                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.805473                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.953037                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.953037                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.857021                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.857021                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.857021                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.857021                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23996.465747                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23996.465747                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35170.719099                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 35170.719099                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.223972                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.223972                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.223972                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.223972                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                           99336                       # number of read accesses completed
system.cpu2.num_writes                          53403                       # number of write accesses completed
system.cpu2.num_copies                              0                       # number of copy accesses completed
system.cpu2.l1c.tags.replacements                    22214                       # number of replacements
system.cpu2.l1c.tags.tagsinuse                  394.859577                       # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs                      13307                       # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs                    22614                       # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs                     0.588441                       # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2           394.859577                       # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2            0.771210                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total           0.771210                       # Average percentage of cache occupancy
system.cpu2.l1c.ReadReq_hits::cpu2               8708                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8708                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1070                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1070                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9778                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9778                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9778                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9778                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            36160                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           36160                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           22990                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          22990                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             59150                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            59150                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            59150                       # number of overall misses
system.cpu2.l1c.overall_misses::total           59150                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2    947354858                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total    947354858                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2    856510547                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total    856510547                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   1803865405                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   1803865405                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   1803865405                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   1803865405                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          44868                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         44868                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         24060                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        24060                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           68928                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          68928                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          68928                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         68928                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805920                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.805920                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955528                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.955528                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.858142                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.858142                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.858142                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.858142                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26198.972843                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 26198.972843                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37255.787168                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 37255.787168                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 30496.456551                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 30496.456551                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 30496.456551                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 30496.456551                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs      1016435                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               62092                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs    16.369822                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks           9582                       # number of writebacks
system.cpu2.l1c.writebacks::total                9582                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36160                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        36160                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        22990                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        22990                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        59150                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        59150                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        59150                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        59150                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    870067956                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total    870067956                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    807866531                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total    807866531                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1677934487                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   1677934487                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1677934487                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   1677934487                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    699720514                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    699720514                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2   1649553128                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total   1649553128                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   2349273642                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   2349273642                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805920                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805920                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955528                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.955528                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858142                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.858142                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858142                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.858142                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24061.613827                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24061.613827                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35139.910004                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35139.910004                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28367.446948                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28367.446948                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28367.446948                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28367.446948                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                          100000                       # number of read accesses completed
system.cpu3.num_writes                          53536                       # number of write accesses completed
system.cpu3.num_copies                              0                       # number of copy accesses completed
system.cpu3.l1c.tags.replacements                    22464                       # number of replacements
system.cpu3.l1c.tags.tagsinuse                  397.838914                       # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs                      13424                       # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs                    22862                       # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs                     0.587175                       # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3           397.838914                       # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3            0.777029                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total           0.777029                       # Average percentage of cache occupancy
system.cpu3.l1c.ReadReq_hits::cpu3               8781                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8781                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1109                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1109                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3                9890                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total               9890                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3               9890                       # number of overall hits
system.cpu3.l1c.overall_hits::total              9890                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            36107                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           36107                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           23001                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          23001                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             59108                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            59108                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            59108                       # number of overall misses
system.cpu3.l1c.overall_misses::total           59108                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3    940989779                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total    940989779                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3    850325185                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total    850325185                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   1791314964                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   1791314964                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   1791314964                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   1791314964                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          44888                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         44888                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         24110                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        24110                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           68998                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          68998                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          68998                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         68998                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.804380                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.804380                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954002                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.954002                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.856663                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.856663                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.856663                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.856663                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26061.145457                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 26061.145457                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36969.052867                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 36969.052867                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 30305.795561                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 30305.795561                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 30305.795561                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 30305.795561                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs      1013074                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               62000                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs    16.339903                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks           9786                       # number of writebacks
system.cpu3.l1c.writebacks::total                9786                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36107                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        36107                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23001                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        23001                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        59108                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        59108                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        59108                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        59108                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    863727177                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total    863727177                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    801703041                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total    801703041                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1665430218                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   1665430218                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1665430218                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   1665430218                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    709371346                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    709371346                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3   1619504156                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total   1619504156                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   2328875502                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   2328875502                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.804380                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.804380                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954002                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954002                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.856663                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.856663                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.856663                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.856663                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23921.322098                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23921.322098                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34855.138516                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34855.138516                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28176.054307                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28176.054307                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28176.054307                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28176.054307                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                           99830                       # number of read accesses completed
system.cpu4.num_writes                          54064                       # number of write accesses completed
system.cpu4.num_copies                              0                       # number of copy accesses completed
system.cpu4.l1c.tags.replacements                    22082                       # number of replacements
system.cpu4.l1c.tags.tagsinuse                  393.544066                       # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs                      13201                       # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs                    22486                       # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs                     0.587076                       # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4           393.544066                       # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4            0.768641                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total           0.768641                       # Average percentage of cache occupancy
system.cpu4.l1c.ReadReq_hits::cpu4               8712                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              8712                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1102                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1102                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4                9814                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total               9814                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4               9814                       # number of overall hits
system.cpu4.l1c.overall_hits::total              9814                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            35977                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           35977                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           23176                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          23176                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             59153                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            59153                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            59153                       # number of overall misses
system.cpu4.l1c.overall_misses::total           59153                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4    943945635                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total    943945635                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4    856485364                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total    856485364                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   1800430999                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   1800430999                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   1800430999                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   1800430999                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          44689                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         44689                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         24278                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        24278                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           68967                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          68967                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          68967                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         68967                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.805053                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.805053                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.954609                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.954609                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.857700                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.857700                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.857700                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.857700                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26237.474915                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 26237.474915                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 36955.702623                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 36955.702623                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 30436.850185                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 30436.850185                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 30436.850185                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 30436.850185                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs      1017670                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               62294                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs    16.336565                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks           9622                       # number of writebacks
system.cpu4.l1c.writebacks::total                9622                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        35977                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        35977                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23176                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        23176                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        59153                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        59153                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        59153                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        59153                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    867154515                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total    867154515                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    807437346                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total    807437346                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1674591861                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   1674591861                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1674591861                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   1674591861                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    707224870                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    707224870                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4   1620907679                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total   1620907679                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   2328132549                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   2328132549                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.805053                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.805053                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.954609                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.954609                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.857700                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.857700                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.857700                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.857700                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24103.024571                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24103.024571                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34839.374612                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34839.374612                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28309.500127                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28309.500127                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28309.500127                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28309.500127                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                           99630                       # number of read accesses completed
system.cpu5.num_writes                          53500                       # number of write accesses completed
system.cpu5.num_copies                              0                       # number of copy accesses completed
system.cpu5.l1c.tags.replacements                    22051                       # number of replacements
system.cpu5.l1c.tags.tagsinuse                  395.592742                       # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs                      13484                       # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs                    22450                       # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs                     0.600624                       # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5           395.592742                       # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5            0.772642                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total           0.772642                       # Average percentage of cache occupancy
system.cpu5.l1c.ReadReq_hits::cpu5               8824                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8824                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1160                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1160                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                9984                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               9984                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               9984                       # number of overall hits
system.cpu5.l1c.overall_hits::total              9984                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36108                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36108                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23031                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23031                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             59139                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            59139                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            59139                       # number of overall misses
system.cpu5.l1c.overall_misses::total           59139                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5    948980493                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total    948980493                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5    861190152                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total    861190152                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   1810170645                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   1810170645                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   1810170645                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   1810170645                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          44932                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         44932                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         24191                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        24191                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           69123                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          69123                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          69123                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         69123                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.803614                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.803614                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952048                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.952048                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.855562                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.855562                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.855562                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.855562                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26281.724078                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 26281.724078                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37392.651296                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 37392.651296                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 30608.746259                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 30608.746259                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 30608.746259                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 30608.746259                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs      1024769                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               62427                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs    16.415477                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks           9521                       # number of writebacks
system.cpu5.l1c.writebacks::total                9521                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36108                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36108                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23031                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23031                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        59139                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        59139                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        59139                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        59139                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    871850549                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total    871850549                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    812508000                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total    812508000                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1684358549                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   1684358549                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1684358549                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   1684358549                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    704255884                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    704255884                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5   1614286606                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total   1614286606                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   2318542490                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   2318542490                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.803614                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.803614                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952048                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952048                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.855562                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.855562                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.855562                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.855562                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24145.633904                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24145.633904                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35278.884981                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35278.884981                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28481.349854                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28481.349854                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28481.349854                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28481.349854                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                           99897                       # number of read accesses completed
system.cpu6.num_writes                          53584                       # number of write accesses completed
system.cpu6.num_copies                              0                       # number of copy accesses completed
system.cpu6.l1c.tags.replacements                    22385                       # number of replacements
system.cpu6.l1c.tags.tagsinuse                  395.582005                       # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs                      13337                       # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs                    22793                       # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs                     0.585136                       # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6           395.582005                       # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6            0.772621                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total           0.772621                       # Average percentage of cache occupancy
system.cpu6.l1c.ReadReq_hits::cpu6               8715                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8715                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1094                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1094                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                9809                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               9809                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               9809                       # number of overall hits
system.cpu6.l1c.overall_hits::total              9809                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            36235                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           36235                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           23035                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          23035                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             59270                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            59270                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            59270                       # number of overall misses
system.cpu6.l1c.overall_misses::total           59270                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6    950668375                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total    950668375                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6    850880053                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total    850880053                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   1801548428                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   1801548428                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   1801548428                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   1801548428                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          44950                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         44950                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         24129                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        24129                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           69079                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          69079                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          69079                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         69079                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806118                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.806118                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.954660                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.954660                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.858003                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.858003                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.858003                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.858003                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26236.190838                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 26236.190838                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36938.574040                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 36938.574040                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 30395.620516                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 30395.620516                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 30395.620516                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 30395.620516                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs      1011987                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               61933                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs    16.340029                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks           9690                       # number of writebacks
system.cpu6.l1c.writebacks::total                9690                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36235                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        36235                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23035                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        23035                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        59270                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        59270                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        59270                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        59270                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    873220563                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total    873220563                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    802141037                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total    802141037                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1675361600                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   1675361600                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1675361600                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   1675361600                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    697661939                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    697661939                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6   1639994129                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total   1639994129                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   2337656068                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   2337656068                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806118                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806118                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.954660                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.954660                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858003                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.858003                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858003                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.858003                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24098.815041                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24098.815041                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34822.706186                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34822.706186                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28266.603678                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28266.603678                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28266.603678                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28266.603678                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           99207                       # number of read accesses completed
system.cpu7.num_writes                          53401                       # number of write accesses completed
system.cpu7.num_copies                              0                       # number of copy accesses completed
system.cpu7.l1c.tags.replacements                    22143                       # number of replacements
system.cpu7.l1c.tags.tagsinuse                  394.587693                       # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs                      13403                       # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs                    22544                       # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs                     0.594526                       # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7           394.587693                       # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7            0.770679                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total           0.770679                       # Average percentage of cache occupancy
system.cpu7.l1c.ReadReq_hits::cpu7               8635                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8635                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1078                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1078                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                9713                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               9713                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               9713                       # number of overall hits
system.cpu7.l1c.overall_hits::total              9713                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            36141                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           36141                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           23098                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          23098                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             59239                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            59239                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            59239                       # number of overall misses
system.cpu7.l1c.overall_misses::total           59239                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7    942615817                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total    942615817                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7    859348059                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total    859348059                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   1801963876                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   1801963876                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   1801963876                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   1801963876                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          44776                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         44776                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         24176                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        24176                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           68952                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          68952                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          68952                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         68952                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.807151                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.807151                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.955410                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.955410                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.859134                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.859134                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.859134                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.859134                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26081.619684                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 26081.619684                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37204.435839                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 37204.435839                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 30418.539746                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 30418.539746                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 30418.539746                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 30418.539746                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs      1024987                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               62690                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs    16.350088                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks           9629                       # number of writebacks
system.cpu7.l1c.writebacks::total                9629                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36141                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        36141                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23098                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        23098                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        59239                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        59239                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        59239                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        59239                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    865505701                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total    865505701                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    810567819                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total    810567819                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1676073520                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   1676073520                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1676073520                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   1676073520                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    711693302                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    711693302                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7   1603062205                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total   1603062205                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   2314755507                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   2314755507                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.807151                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.807151                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.955410                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.955410                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.859134                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.859134                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.859134                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.859134                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23948.028582                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23948.028582                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35092.554290                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35092.554290                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28293.413461                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28293.413461                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28293.413461                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28293.413461                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------